Accelerating the next technology revolution

Copyright ©2012

SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center

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Interconnect Opportunities –

A SEMATECH Perspective

Sitaram Arkalgud

Sr. Director– Interconnect/3D IC

8th Annual Japan Symposium

June 26, 2012

Tokyo, Japan

Portions of this document are SEMATECH confidential, as marked

The Interconnect Space

• TSVs are just entering mainstream – Considerable issues around scaling (TSV and C2C interconnects), cost, thermal

management and thin wafer/die handling

• Cu will continue to be interconnect mainstay for many years – Resistance will rise exponentially with scaling

– Considerable work on addressing issues at member companies, universities, consortia

– Need to address weakest link in interconnect scheme • Chip to chip (medium term driven by BW) or within chip (near term)

• Power and signal mismatches between different chips will gate 3D stacking

• ~Terabit/s data handling are contemplated for 2nd/3rd gen wide I/O DRAMs

• Mixed electrical/optical approaches may be the only option

• Next generation options – Optical: nanophotonics

– Electrical: graphene, nanowires and CNT

Product functionality and power efficient performance at the right cost are the interconnect drivers

22 June 2012 2

2013

3D Roadmap

2012

memory memory Logic

Si TSV interposer

memory memory

Heat Sink and

TIM

3D Interposer

Common Industry Needs - Materials and Process Evaluations

- Thermal Management

- Materials, EDA

- Understanding Costs

- Reference flows, BOM to CoO

- Technology Maturity & Standards

- Supply Chain

- Interfaces and handoffs

- Pathfinding Tools

- Performance, power, floor planning

2015 2020

3D+

memory memory Logic

Si TSV interposer

memory

memory

Heat Sink and TIM

NAND Analog

NGI?

Production

Development

Pre-Development

22 June 2012 3

2013

3D Interconnect Roadmap

2012

memory memory Logic

Si TSV interposer

memory memory

Heat Sink and

TIM

3D Interposer

2015 2020

3D+

memory memory Logic

Si TSV interposer

memory

memory

Heat Sink and TIM

NAND Analog

NGI?

Production

Development

Pre-Development

Courtesy: WWW.Intel.com

First gen products underway Common Industry Needs - Materials and Process Evaluations

- Thermal Management

- Materials, EDA

- Understanding Costs

- Reference flows, BOM to CoO

- Technology Maturity & Standards

- Supply Chain

- Interfaces and handoffs

- Pathfinding Tools

- Performance, power, floor planning

22 June 2012 4

Mission of Materials and Emerging Technologies

Develop infrastructure for 3D transition in semiconductor industry

• Infrastructure development:

• Materials: Identify and down select

• Tools/Processes: Develop with universities/suppliers and harden

• Mechanisms: Fundamental understanding for manufacturability & scalability

• Models: Develop approaches to aid characterization and reliability assessment

• Key modules that enable acceleration of new technologies for

manufacturing

• Core competencies

• Narrow options: data driven consensus

• Standardize methods: data driven benchmarking

• Minimize cost, risk and avoid duplication

• Leverage resources from industry eco-system

• Address problems that are difficult for any individual company to tackle

• Nurture partnerships with suppliers and academia to execute mission

22 June 2012 5

• Demonstrate manufacturability of key 3D processes

needed for future generations • Low temperature Cu direct bonding process

• Underfill material development and assessment methodology

for thermal management

• 20: 1 aspect ratio TSV test structures and associated

challenges

• Materials and process development for thin wafer handling,

temporary bonding and room temperature debonding

• Test structure development for package interactions and

reliability monitoring

• Enable and assess next generation 3D stacking

implementation needs by driving

inspection/metrology, standards and specifications

through 3D EC

• Gap assessment for feasible Next Generation

Interconnect options

Key Activities

22 June 2012 6

Cu-Cu Direct Bond – Throughput

Improvements

• Conventional process (400ºC)

has a throughput of ~0.5 WPH – Vacuum requirement and high bond

temperature negatively influence tool

throughput

• Feasibility of low temperature

(~200ºC, 5 min) process

demonstrated on blankets – Process below Pb-free reflow

temperatures introduces compatibility

with all modern packaging materials

• New tool concept proposed to

increase throughput to 30 WPH

– 88% reduction in COO

POR

Low T

Process

New Tool

Concept

Cu-Cu bond

Interface

200ºC/10min

High Resolution TEM

195 C / 5 minute

bond E. Stinzianni

R Edgeworth 22 June 2012 7

TSV Module Roadmap Via Middle Gap Identification by TSV Node

TSV Scaling Issues

• Increasing Aspect Ratio

• Dielectric Liner Coverage and Continuity

• Barrier-Seed Coverage and Continuity

• Void-Free Cu Fill

• Increasing RC Delay

• Dielectric Liner Thickness

• Cu Volume

• Thermo-mechanical Performance

• Improves with scaling, but remains a

concern for device performance (KOZ)

and reliability in increasingly fragile ULK

dielectric layers

• Bond and Thin Unit Process Development

• Thin Wafer/Die Handling

Module Process TSV Node

5µm × 50µm 2µm × 40µm

TSV

LTH

RIE

WETS

MTR

INS

MTL

PLT

FRN

CMP

Ready for HVM

Ready for Initial Ramp-Up

Not Ready

Identify tool, material, and

process gaps in the

fabrication of high aspect

ratio (20:1) TSVs; use

cost-modeling to identify

the HVM-capable

solutions that best

address these gaps.

B Sapp 22 June 2012 8

Scaling of Chip to Chip Interconnects

Bonding Method

C4 FC (Contolled

Collapse Chip

Connect)

C2 FC

(Chip Connect)

TC/LR (Local

Reflow) FC TC FC

Schematic Diagram

Major Bump Pitch Range at

Application > 130 um 140 um ~ 60 um 80 um ~ 20 um < 30 um

Bonding Method

Conventional

Reflow

Reflow with Cu

pillar

Thermal

Compression

with Cu pillar

Thermal

Compression

Bump Metallurgy Solder (SnAg or

SnAgCu)

Cu + Solder

(SnAg or Sn)

Cu + Solder

(SnAg or Sn)

Cap

Cu

Bump Collapse Yes No No No

Underfill Method - Capillary

- No flow

- Capillary

- No flow

- Wafer Level

- No flow

- Wafer Level

- No flow

- Wafer Level

M-S Suh 22 June 2012 9

Scaling of Chip to Chip Interconnects

Bonding Method

C4 FC (Contolled

Collapse Chip

Connect)

C2 FC

(Chip Connect)

TC/LR (Local

Reflow) FC TC FC

Schematic Diagram

Major Bump Pitch Range at

Application > 130 um 140 um ~ 60 um 80 um ~ 20 um < 30 um

Bonding Method

Conventional

Reflow

Reflow with Cu

pillar

Thermal

Compression

with Cu pillar

Thermal

Compression

Bump Metallurgy Solder (SnAg or

SnAgCu)

Cu + Solder

(SnAg or Sn)

Cu + Solder

(SnAg or Sn)

Cap

Cu

Bump Collapse Yes No No No

Underfill Method - Capillary

- No flow

- Capillary

- No flow

- Wafer Level

- No flow

- Wafer Level

- No flow

- Wafer Level

2012 TSV

2014/15 TSV

M-S Suh 22 June 2012 10

Next Generation Interconnect

• All options will leverage 3D IC in some form

• We will use our 3D IC capability to narrow down options for manufacturability

22 June 2012 11

University

Research

Member Company

Implementation

2012 2017

SEMATECH testbed for materials, processes

and tool evaluations

Doped Copper

Silver

Gold

Graphene

Carbon Nanotubes

Nanowires

Superconductors

2D Conductors

Optical Interposer

Optical Onchip

Better evaluated at MC

Futuristic

Difficult to implement in fab

Still in research mode

Futuristic

Futuristic

Narr

ow

to

1-2

“m

ost lik

ely

” o

ptio

ns

Attributes of CNT and Graphene

• Both graphene and carbon nanotubes promise superior properties compared to Cu

– Virtually ballistic transport

– Higher reliability

– Higher thermal conductivity

Si Cu Graphene CNT

Resistivity (u.ohm.cm) 1.68 1 1

Current density (A/cm2) 10E6 10E8 10E9

Carrier Mobility (cm2/Vs) 450 200,000 100,000

Thermal Conductivity (W/mK) 400 5000 3000

22 June 2012 12

GNR – Modeling and Status

• Naeemi plot vs Murali plot

A Naeemi and J Meindl, IEEE TED (56) 9, 2009 R Murali et al EDL(30) 96 2009

• Graphene shows considerable promise with large MFP (virtually ballistic), mobility,

thermal conductivity and EM resistance

• Still relatively immature

• Minimizing edge effects and demonstrating low resistivity is key for interconnects

Attractive

alternatives to Cu

Resistivity shows

increase with scaling!

22 June 2012 13

CNT Status*

* Adapted from “M Nihei “CNT/Graphene Technologies for Advanced Interconnects” IITC Short Course, June 3 2012 San Jose, CA”

MIRAI-Selete ==>

AIST, LEAPSamsung ==> KAIST

VIACARBON ==>

LETI, CambridgeIMEC

TechnologyRequirement

Process Single Damascene Single Damascene Single Damascene Single Damascene

Catalyst/Bottom

Electrode

Co

particle/TiN/Ta/CuCo film/Ti/TiN Fe film/AlCu Ni film/TiN

CNT Growth

Temperature

< 400CThermal CVD C2H2

365 - 450C

Remote Plasma

CVD, CH4/H2, 600C

Thermal CVD,

C2H2/H2/He, 580C

Thermal CVD,

C2H4/H2/Ar, 400 -

470C

CNT Density

(/cm2)> 10E12 10E11 - 10E12 4*10E11 2.5*10E12 7*10E10 ~ 2*10E11

Top Electrode< 400C CMP Ti/Cu (RT) CMP Ti/Al (500C) CMP Ti/Pt (RT) CMP Ti/Au (400C)

Resistivity

(mWcm)

~10 (W), ~2

(Cu)

10 (52 W @ f

70nm, 450C)

73 (293 W@f

80nm)

390k (10 kW@f

1000nm)

28k (7.9 kW@f

300nm)

Current density

(A/cm2)> 10E7 2*10E8 ---------- ---------- ----------

• CNT has properties similar to graphene

• Still relatively immature

• Demonstrating low resistivity is key for interconnects

22 June 2012 14

Electrical Interconnect Limitations

Bandwidth Limitations – Wires are not scalable

Maximum Bandwidth:

Bandwidth is fundamentally limited by the

available area (e.g. once all area is used there is

no more capacity)

Power Limitations - Total interconnect power is

too high

~50% of Total Chip Power

Expected to rise to >80%

Cannot increase total power. Limited to ~200W.

Signal Integrity and Latency Limitations

RC Delay will increase considerably with scaling

Bµ1016 Area

Length2

D. Miller, J. Parallel and Dist.

Comp. 41, 4252 (1997)

D. Miller, Proc IEEE 97, 1166 (2009)

Sam Naffziger, AMD Fellow,

2011 VLSI Symposium Keynote

Source: IBM

SEMATECH Confidential 22 June 2012 15

Why Silicon Photonics?

All components of a Silicon Photonic Interconnect have been demonstrated:

Silicon photonics is a promising technology:

High Bandwidth (>200 THz)

Low Power (<100 fJ/bit)

Compact Devices (< 2mm3)

Compatible with Fiber Optics

Seamless CMOS Integration

Silicon Photonic Circuit

Laser Electro-Optic Modulator Photodetector

Intel/UCSB – III-V Bonded Laser

MIT – Ge Laser Cornell University – Microring Modulator

Intel – Ge Detector

K-W Ang 22 June 2012 16

SEMATECH’s Si Photonic Building

Blocks Lasers Modulators Detectors Waveguides

Interconnects Heaters Gratings Switches

SEMATECH has designed a complete Silicon Photonic device library

The device library uses a 300mm reference flow

The interconnects will be integrated into a 3D CMOS process

K-W Ang 22 June 2012 17

Stages Cu 2D Cu 3D Optical Graphene CNT

Concept X X X X X

Mechanisms X X X X X

Reference Flow X X X

Materials Selection X X X

Device Feasibility X X X

Module Development X X

Equipment Hardening X X

Infrastructure X X

Reliability X X

HVM X X

C&F

UPD

Module

Interconnect Options

Maturity of Interconnect Options

Best candidate for

Next Generation HVM

Relatively immature

22 June 2012 18

Enablement Center

• Very successful program

– Focus is on enabling standards (http://wiki.sematech.org) and ensuring chip interoperability

• Obtained considerable industry attention

– Attracted several new members since Jan 2011 start

• Analog Devices, Altera, Invensas, NIST, On Semiconductor, Qualcomm

• Increased program diversity

– Network has expanded considerably

• Strong relationship with SRC, SEMI, SI2, JEDEC

• Fabless companies, OSATs and universities

• 3D Enablement Center playbook is a template for NGI – Reference flow(s)

– Gap analysis

– Standards and specifications

– Forward looking option assessments with pathfinding tools

22 June 2012 19

3D Members and Partners

22 June 2012 20

Summary

• Interconnect Center is addressing material and tool gaps by leveraging

existing capabilities in 3D program

– TSV and advanced package interactions • Thin wafer/die handling

• Cu-Cu direct bonding

• Underfill

• TSV scaling, infrastructure gaps

– Working on gaps for next generation interconnect

• Enhancing linkage to key research institutions and universities to

translate concepts from lab to fab

• Interconnect continues to require engagement of larger section of the

supply chain

– Fabless, packaging, suppliers, universities

22 June 2012 21

22 June 2012 22