interconnect-trns line termination

ELE-863 VLSI Circuits and Systems for DataCommunications

Interconnects

Fei Yuan, Ph.D, P.Eng.Department of Electrical & Computer Engineering

Ryerson UniversityCopyright c Fei Yuan

Copyright (c) F. Yuan (1)

Preface

This chapter covers the essentials of the design of on-chip andon-board interconnects. An emphasis is given to the transmission

line effect of interconnects, termination schemes, and impedancematching networks.

The materials covered in this chapter are an essential part of the

4th-year elective course ELE-863 VLSI Circuits and Systems forData Communications offered by the Department of Electrical and

Computer Engineering at Ryerson University, Toronto, Ontario,Canada. The materials of this chapter are drawn from various

published texts and research papers. Some of the major referencesare listed at the end of the chapter. Students are strongly

encouraged to read the cited references in the chapter to gainfurther knowledge of the subjects covered in this chapter.

The materials of this chapter can be freely distributed for

educational purposes only. Please report any error of this lecturenote to Professor Fei Yuan via email at [email protected].


Chapter Outline

Introduction

Thickness of Interconnects

Minimum Width of Interconnects

Resistance of Interconnects

Capacitance of Interconnects

Inductance of Interconnects

Modeling of Interconnects

Transmission Line Effect

Termination Schemes

Impedance-Matching Networks

References


Introduction

Interconnects in ICs

Typical interconnects encountered in ICs include metal layers,

silicidated poly layers, silicided n+ and p+ diffusion layers, viasconnecting different metal layers, contacts connecting metal layers

and diffusion regions, and contacts connecting metal and polylayers.

The scaling of MOS devices has been more aggressive than the

scaling of the height of interconnects the performance of ICs, inparticular, the propagation delay, is largely affected by

interconnects.

Table 1: Scaling of interconnects.

Parameters CMOS-0.35 CMOS-0.25 CMOS-0.18 CMOS-0.13

VDD 3.3V 2.5V 1.8V 1.2V(24% drop) (28% drop) (33% drop)

Lmin 0.35m 0.25m 0.18m 0.13m(29% drop) (28% drop) (38% drop)

Min. width 0.5m 0.32m 0.23m 0.16mof metal-1 (36% drop) (28% drop) (30% drop)

Min. width 0.35m 0.25m 0.22m 0.12mof poly (29% drop) (12% drop) (45% drop)

VIA12 0.5m 0.36m 0.26m 0.20m(28% drop) (28% drop) (23% drop)

Contact 0.4m 0.3m 0.22m 0.16m(25% drop) (27% drop) (27% drop)

Min. height 6700A 5700A 5300Aof metal-1 (15% drop) (7% drop)

Number of 3 metal 5 metal 6 metal 8 metalmetal layers layers layers layers layers


Introduction (contd)

The number of metal layers has been increased significantly tocombat the increased complexity of systems interconnectsconstitute a very significant portion of ICs placement androuting of interconnects that minimize the propagation delay of andinterference among interconnects have become a major research

area in design of VLSI systems.


Thickness of Interconnects

The thickness (height) of interconnects is set by process technologyand can not be changed by designers.

Thickness of interconnects has been scaled down moderately, mainlydue to the resultant increase in the resistance of interconnects,especially global interconnects.

The top metal layer has the largest thickness. It has the highestcurrent rating per unit width and the lowest capacitance per unitarea to the substrate. This layer should only be used for global

signals (VDD, VSS, and clock), spiral inductors, and bonding pads.

All other metal layers typically have the same thickness. They are

usually used for local wiring, stacked spiral inductors, andmulti-layer bonding pads.


The Min. Width of Interconnects

The min. width of metal layers has been scaled down aggressivelyto reduce the silicon area for routing interconnects.

The top metal layer has the largest min. width lower resistanceper unit width.

The contact size and the via size have been scaled down

aggressively, in consistency with the scaling of the minimum widthof interconnects.

The min. width of poly has also been scaled down aggressively.


Resistance of Interconnects

Sheet Resistance Definition of sheet resistance

R = L

WH=

H

L

W= R2

L

W, (1)

where R2 =

His the sheet resistance with unit , L=interconnect

length, W=interconnect width, H=interconnect height, and=resistivity of interconnects. Note that sheet resistance is a

process-dependent parameter and can not be changed by designers.

n-well layers have a large sheet resistance (approximately500-1k). It is normally used as resistors and should not be used

for interconnects.

n+ layers without silicidation has a moderate sheet resistance(approximately 50 100). It should not be used forinterconnects.

n+ and p+ layers with silicidation have a low sheet resistance(typically less than 10). It can be used for local interconnects. For

digitally oriented CMOS technologies, often only n+/p+-layers withsilicidation are available. Note that the sheet resistances of n+ andp+ layers with silicidation are comparable as they are largely

determined by the resistance of the silicide layer.

Poly layers in standard digital CMOS processes are silicided.Typical sheet resistance of silicided poly layers is R28. They canbe used for local interconnects.


Resistance of Interconnects (contd)

Contact resistance - the resistance between (i) contact-n+ diffusion,(ii) contact-p+ diffusion, (iii) contact-ploy. The contact resistance isusually below 10 per contact. To reduce contact-induced parasitic

resistance, multiple contacts should be used.

Via resistance - for 3-metal CMOS technologies, Via12 (betweenMetal-1 and Metal-2) and Via23 (between Metal-2 and Metal-3)

exist. Via resistance is typically smaller than contact resistance,and is usually less than 8 per Via (Vias connecting the top metal

layer have a lower resistance. For example, for a 0.13m CMOStechnology, the resistance of vias is : V ia15 = 1.5 andV ia6,7 = 0.6.) To reduce via-induced parasitic resistance, multiplevias should be used.

The sheet resistance of metal layers at low frequencies is small, and

is in the range of 0.05. Note that for global interconnects, sincethe length of these interconnects is usually large, the DC voltage

drop across global interconnects must be accounted for in design ofthese interconnects.

The preceding values of the resistances of interconnects are in the

DC steady state. At high frequencies, due to skin effect, currentsflow only in the region close to the surface of the interconnect. The

reduction of the effective conducting area significantly increases theresistance of interconnects, as to be detailed in the following section.



Skin Effect When an AC current flows through a conductor, a magnetic field iscreated. The resultant magnetic field will impact a force, called

Lorezen force, on moving electronics. Lorezen force forces electronsto move to the surface of the conductor higher resistance atcenter and lower resistance near the surface the effectiveconducting area is measured by skin depth

=1f

, (2)

where = ro is permittivity of the conductor, =conductivity of

the conductor, f=frequency of the current.

H

I

vn

Lorezenforce

H

dr

Figure 1: Skin effect of interconnects.

The effective conducting area

A = r2 (r )2 = r2 (r2 2r + 2) 2r. (3)

where we have neglected the 2nd-order term.



Skin Effect (contd)

Skin-effect induced resistance

R(f)

Rdc=

LA Lpir2

=r

2, (4)

we have

R(f) = Rdc

(r

2

)=

L

2r

f. (5)

Skin-induced resistance is proportional to the square-root of

frequency.

Skin depth of typical interconnects

Table 2: Skin depth of interconnects at 100 MHz.

Interconnect Resistivity Skin depth 100MHz Skin depth 5GHz(109m) (m) (m)

Silver 16.3 6.4 0.905Copper 17.3 6.6 0.933Gold 22.7 7.6 1.07Aluminum 27.3 8.3 1.17Silicon 100-300 15.9-27.6 2.25-3.9



Scaling of Interconnects

Uniform Scaling - both the width W and height H of

interconnects are scaled down by the same scaling factor.

SW = SH = S, where SW=scaling factor of width, SH=scalingfactor of height, S=uniform scaling factor.

SL 6=S, the scaling factor of length SL differs from the scaling factorof width and height.

When L LSL , WWS , and HHS , we have

R = pLSL

WSWH

=S2

SLR, (6)

where R and R are the resistance of interconnects before and after

uniform scaling.



For local interconnects, we have SL = S. As a result

R = SR. (7)

The resistance of local interconnects grows linearly with the scaling

factor.

For global interconnects, we have L = SL (L grows in proportion tothe die size),

R = S3R. (8)

The resistance of global interconnects rises cubically with thescaling factor.

Uniform scaling has not be adopted due to the rapid increase in the

resistance of global interconnects.



Selective Scaling - W and L are scaled down by the same

scaling factor but H is kept approximately constant.

0.5u 0.32u

6700A 5700A 5300A

0.23u

Heightreduction15%

Widthreduction36%

Heightreduction7%

Widthreduction28%

Figure 2: Selective scaling of interconnects (metal-1 of 0.35, 0.25, 0.18m technologies).

SW = SL = S, SH1.

R = LS

WSS1

= SR. (9)

For local interconnects : R = SR.

For global interconnects : R = SR.

The resistance of interconnects, both local and global, increases

linearly with the scaling factor.

Selective scaling scheme has been adopted in VLSI scaling.


Capacitance of Interconnects

Area Capacitances

Substrate

CaE

Figure 3: Area capacitance of interconnects.

Area capacitance Ca of an interconnect is the capacitance betweenthe bottom of the interconnect and the substrate.

Area capacitance deceases with technology, mainly due to the

down-scaling of the width of interconnects.


Capacitance of Interconnects (contd)

Fringe Capacitances

Substrate

Cf

E

Cf

Figure 4: Fringe capacitance of interconnects.

Fringe capacitance Cf is the capacitance between the side walls and

the substrate.

Fringe capacitance increases with technology, as compared witharea capacitance, mainly due to the increase of H/W (H is kept

approximately constant whereas W is reduced).

For deep sub-micron CMOS technologies, Ca and Cf arecomparable. Both must be considered when estimating the

capacitance of interconnects.



Other Capacitances

Bond pad capacitances

Bond pads are on-chip metal rectangles large enough to be soldered

to the leads. Typical 70x70 m2 - 100x100 m2.

Each pad is typically formed by the two top-most metal layersconnected to each other by many vias on the perimeter in order to

avoid the lift-off of the top metal layer during bonding.

Most CMOS processes require that all metal layers to be connectedtogether for bond pads. Because the top metal layer has a smaller

capacitance to the substrate as compared with the bottom metallayer, connecting all bond-pad metal layers together increases the

capacitance of the pad to the substrate.

64u

64u

m1

m2

m3

H1

H2

H3

T1

T1

T2

Substrate

Figure 5: Capacitance of multi-layer bond pads.



Capacitance of Stubs

A stub is a transmission line segment that branches from the mainline.

metal-2

metal-1

I

I

Min.enclosurerequirementgivesrisetoanopenlinethatbehavesasacapacitor

Figure 6: Capacitance of stubs.

The stub shown in the figure is a transmission line with open-circuittermination. It behaves as a capacitor with the capacitance

determined by the length of the line. To minimize this capacitance,the minimum enclosure rules should be followed.


Inductance of Interconnects

Self-inductance of a round bond wire

R

H

Figure 7: Self-inductance of a round wire.

L0.2ln[2H

R

]where R=radius and H distance from the conductive

substrate.

Self-Inductance of a Rectangular Trace

H

Figure 8: Self-inductance of a rectangular trace.

L1.6Kf

[H

W

], where Kf0.72(HW )+ 1 (fringe factor), W=width of the

trace and H=distance from the trace to the conductive substrate.


Inductance of Interconnects (contd)

Mutual Inductance of two round wires

H

d

Figure 9: Mutual-inductance of two round wires.

L0.1ln[1 + (

2H

d)2].


Modeling of Interconnects

This section deals with the modeling of interconnects. Dependingupon the frequency of signals traveling through the interconnects

and the physical dimensions, in particular, the length of theinterconnects, the behavior of the interconnects can be

characterized at various levels of abstraction, from the simplestlumped RC model to full transmission-line models.


Modeling of Interconnects (contd)

Lumped RC Model

Distributed RC Model

Elmore Model

Transmission-line Model


Lumped RC Model of Interconnects

When the physical dimension of an interconnect is much smallerthan the wave length of the signal passing through the interconnect,the interconnect can be treated as a lumped element and

represented by a low-pass RC network as shown in Fig.10 withR = R2

LW

and C = Ca(WL) + CfL, where Ca and Cf are the area

capacitance per unit area and fringe capacitance per unit length,respectively.

C

Substrate

Vout

C

R

Vin V outVin

L

WH

Figure 10: Lumped RC model of interconnects.

The output voltage to a step voltage input of amplitude Vm is givenby

vo(t) = Vm[1 et/ ], (10)

where = 1RC .

Propagation delay (tp) - the time delay from vo = 0 to vo(tp) =12Vm.

From

0.5 = 1 etp/ , (11)

we arrive at tp = 0.69 .


Distributed RC Model of Interconnects

When the physical dimension of an interconnect is comparable tothe wave length of the signal passing through the interconnect, the

interconnect can not be treated as a lumper element. Instead, itmust be treated as a distributed element, as shown in Fig.11 where

R is the resistance per unit length and C is the capacitance per unitlength. Note that the number of distributed elements N should be

such that L =L

Nis sufficiently small as compared with the

wavelength of the signal.

C

Substrate

Vout

R

Vin

Vout

Vin

DLDL

L

(DL)

C(DL)

R(DL)

C(DL)

R(DL) R(DL)

C(DL) C(DL)

ii-1 i+1

D L D L D L D L

Figure 11: Distributed RC model of interconnects.

KCL at node i

vi vi1R(L)

+vi vi+1R(L)

+ C(L)dvidt

= 0, (12)

from which we obtain

RCdvidt

=(vi+1 vi) (vi vi1)

(L)2. (13)


Distributed RC Model of Interconnects(contd)

Let vi+1 = vi+1 vi, vi = vi vi1, and take the limit L0,we arrive at the diffusion equation of the distributed RC model ofinterconnects

RCvit

=2vix2

. (14)

Diffusion equation (14) reveals that the voltage of an interconnectat a given time t and location x is a function of both the time t and

the location x. Note that in the lumped RC model, the voltage ofinterconnects is a function of time t only.


Elmore Model of Interconnects [1]

R1

Vin

Vout

C1 C

R R

C C

ii-1 i+1

D L D L D L D L

Ri-1 i N

i-1 i N

tN

VDD

0.5VDD

Vin

VDD

Vout

1 i-1 i N

t

t

0

0

Figure 12: Elmore model of interconnects.

For non-branched RC networks

1 = R1C1,

2 = R1(C1 + C2) +R2C2,3 = R1(C1 + C2 + C3) + R2(C2 + C3) + R3C3,

. . .N = R1(C1 + . . .+ CN

N

) + R2(C2 + . . .+ CN N1

) + . . .+ RNCN .

(15)


Elmore Model of Interconnects (contd)

Interconnects are represented by distributed RC networks, where Rand C are resistance and capacitance per unit length, respectively.

R

Vin

Vout(DL)

C(DL)

R(DL)

C(DL)

R(DL) R(DL)

C(DL) C(DL)

ii-1 i+1

D L D L D L D L

1 Ni i+1

Figure 13: Elmore model for distributed interconnects.

N = R1(C1 + C2 + ...+ CN N

) +R2(C2 + ...+ CN N1

) + . . .+ RNCN

= R(L)[C(L) + C(L) + . . .+ C(L) N

]

+ R(L)[C(L) + C(L) + ...+ C(L) N1

] + . . .+ R(L)C(L)

= RC(L)2(1 + 2 + ...+N)

= RC(L)2N(N + 1)

2. (16)

Because L = LN , we have

N =1

2RCL2(1 +

1

N). (17)

In the limit N,

N =1

2RCL2. (18)



Comparison of lumped RC model and Elmore model

0.35RC

0.69RC

Vm

0.5Vm

0.1Vm

0.9Vm

0.9RC

2.2RC

LumpedRCmodel

Elmoremodel

Figure 14: Comparison of Elmore and lumped RC models.

Consider an interconnect of length L. Let the resistance and

capacitance of the interconnect per unit length be R and C,respectively.

Delay from lumped RC model

= RtotalCtotal = RCL2. (19)

Delay from Elmore model

=1

2RCL2. (20)



Comparison of lumped RC model and Elmore model(contd)

The delay of the lumped RC model is twice that of the delay ofElmore model.

The propagation delay of lumped RC model = 0.69RC.

The propagation delay of Elmore model = 0.35RC.

The rise time from the lumped RC model = 0.9RC.

The rise time from the Elmore model = 2.2RC.



Examples

Ca

Substrate

Vout

Vin

L=1mm

W=1uH

Cf

Figure 15: Example.

Consider the interconnect shown. Let the area capacitance per unit

are and the fringe capacitance per unit length beCa = 0.058fF/m

2 and Cf = 0.043fF/m, respectively. Let the

sheet resistance R2 = 10. Estimate the propagation delay.

Total resistance R = R2LW = 10k.

Total capacitance per unit length C = CaA+ CfL = 0.101 pF.

Propagation delay p = 0.38RC = 0.38 ns.


Transmission Line Model of Interconnects

Transmission line equations

Characteristic line impedance

Reflection coefficient

Input impedance


Transmission Line Equations

An infinitesimal section of a transmission line is represented by alumped network shown in Fig.16, where R=series resistance per

unit length, L=self-inductance per unit length, G=shuntconductance between the interconnect and substrate per unit length

(mainly due to dielectric loss of SiO2), C=shunt capacitancebetween the interconnect and substrate per unit length.

R

C

D

zz z+

D

z

V(z,t)

Substrate

V(z) V(z+z)D

L

G

I(z) I(z+z)D(Dz)(Dz)

(Dz) (Dz)

Figure 16: lumped network model of an infinitesimal section of transmission lines.

In the AC steady-state, write KVL in the phasor domain

V (z +z) V (z) = [R(z) + jL(z)

]I(z). (21)

In the limit z0, we have

dV (z)

dz= (R+ jL)I(z). (22)


Transmission Line Equations (contd)

Similarly, write KCL

I(z +z) I(z) = [G(z) + jC(z)

]V (z +z). (23)

In the limit z0, we have

dI(z)

dz= (G+ jC)V (z). (24)

Differentiate (22) with respect to z and substitute (24) into theresultant equation yield

d2V (z)

dz2 2V (z) = 0. (25)

where =(G+ jC)(R+ jL) = + j is the complex

propagation constant, is the attenuation constant quantifying theattenuation of the amplitude of the voltage (current), and is the

phase constant depicting the variation of the phase of the voltage(current). Note that both and are REAL constants.



In a similar manner, one can show that

d2I(z)

dz2 2I(z) = 0. (26)

Eqs.(25) and (26) are called transmission line equations.

Transmission line equations are 2nd-order O.D.Es. They have the

following general solution

V (z) = V +ez + V ez,I(z) = I+ez + Iez,

(27)

where V +, V , I+, and I are independent of z. Note that theabove equations depict the voltage and current of the transmission

lines in the frequency domain.

Evaluating V (z) and I(z) at z = 0 gives

V (0) = V + + V ,I(0) = I+ + I.

(28)

The voltage and current at z = 0 are the sum of the voltage

(current) of the incident wave and that of the reflected wave atz = 0.



Because

V +ez = V +e(+j)z

= V +ez[cos(z) jsin(z)], (29)

and

V ez = V e(+j)z

= V ez[cos(z) + jsin(z)]= V e(z){cos[(z)] jsin((z)]}. (30)

we conclude that (29) depicts the propagation of the voltage inz-direction (the voltage of the incident wave), whereas (30)

characterizes the propagation of the voltage in z direction (thevoltage of the reflected wave).

If = 0, the amplitude of the voltage of the wave in both z and zdirections remains unchanged along the transmission lines (losslesslines).

For practical transmission lines, > 0, the voltage of both the

incident and reflected waves is attenuated along the transmissionlines (lossy lines).


Characteristic Line Impedance

The current of the transmission lines is obtained from

I(z) = 1R + jL

dV (z)

dz

= 1R + jL

d

dz(V +ez + V ez)

=1

Zo(V +ez V ez). (31)

where

Zo =R+ jL

=

R + jLG+ jC

(32)

is called the characteristic impedance of the line.

The characteristic impedance is independent of either the voltage or

the current of the line. It is a function of the physicalcharacteristics of the line that are quantified by R,L,C,and G only.

For lossless lines, i.e. no ohmic loss, R = 0 and G = 0, we have

Zo =

LC. (33)

The characteristic impedance of lossless lines is a REAL constant.For coaxial cables, typically Zo = 50 and for PCB traces,

Zo = 75.


Characteristic Line Impedance (contd)

Comparing the following two equations

I(z) = 1Zo (V+ez V ez),

I(z) = I+ez + Iez,(34)

we have

V + = ZoI+,

V = ZoI (35)

For lossless lines, since Zo is real, V+ and I+ are in phase while V

and I are out of phase.


Reflection Coefficient

z=0

V

VZL

I L

VL

Figure 17: Terminated lines.

At the load whose location is specified by z = 0, the voltage across

the load is obtained from VL(0) = V+ + V , where V + and V are

the amplitude of the voltage of the incident and reflected waves,

respectively.

At the load (z = 0), we have

ZL =VL(0)

IL(0)=

V + + V 1Zo(V + V ) . (36)

The above equation can be written as

V =[ZL ZoZL + Zo

]V +. (37)


Reflection Coefficient (contd)

Voltage reflection coefficient at the load (z = 0) is defined as

V (0) =V

V +=ZL ZoZL + Zo

. (38)

Note that reflection coefficient is a function of location. The above

definition is valid at z = 0 only because ZL is evaluated at z = 0.

Current reflection coefficient at the load is obtained form

I(0) =I

I+= V

/ZoI+/Zo

= V (0). (39)


Reflection Coefficient (contd)

Reflection coefficient of open lines

Open lines : ZL =.

(0) = 1. As a result, V + = V a maximum reflection occurs atthe load. The reflected wave is in phase with the incident wave VL(0) = V

+ + V , voltage doubles at the far end of an open line !

Because I(0) = V (0) = 1, we have IL(0) = I+ + I = 0. Thecurrent at the far end of an open line vanishes.

Reflection coefficient of shorted lines

Shorted lines : ZL = 0.

V (0) = 1, As a result, V + = V a maximum reflectionoccurs at the load. The reflected wave is out of phase with theincident wave VL(0) = V + + V = 0, voltage vanishes at the farend of an shorted line.

Because I(0) = V (0) = 1, we have IL(0) = I+ + I. The currentat the far end of a shorted line doubles.


Input Impedance

z=0

V

ZL

I L

V(0)

z

Z(z)in

Zo

VV(z)

I(z)

Figure 18: Input impedance of transmission lines.

The input impedance of a terminated transmission line at an

arbitrary location z

Zin(z) =V (z)

I(z)

=V +ez + V ez

I+ez + Iez

= Zo

[ez + V

V +ez

ez V V +ez]

= Zo

[ez + V (0)ez

ez V (0)ez]

= Zo

[1 + V (0)e

2z

1 V (0)e2z]. (40)


Input Impedance (contd)

Eq.(40) reveals that once the voltage reflection coefficient at theload z = 0 is known, the input impedance at any location z of theline can be determined.

For lossless lines we have = 0 and = j. Because

V (0) =ZL ZoZL + Zo

, (41)

we have

Zin(z) = Zo

[ZL + jZotan(z)

Zo + jZLtan(z)

]. (42)

This equation allows us to compute Zin(z) at any location z oflossless lines.



Input impedance of terminated lossless lines

Terminated lossless lines : ZL = Zo.

Zin(z) = Zo and V (z) = 0

1. No reflection at any point of a lossless line once the line

is terminated with its characteristic impedance.

2. The input impedance is the same anywhere along theline and in is the characteristic impedance of the line.



Input impedance of open-circuit terminated losslesslines

Open-circuit terminated lossless line : (ZL =).

Zin(z) =Zo

jtan(z).

A lossless line with an open-circuit termination exhibits a capacitivecharacteristic ! The capacitance depends upon the length of the line

and the frequency of the signal traveling on the line.



The following configurations introduce unwanted capacitive loads,arising from the stubs and the minimum enclosure spacerequirement of design rules.

Stub

(A)-multipledrops

Stub

Figure 19: Unwanted capacitive loads.



VIA12m2

m1Stub

Min.enclosurespacerequiredbydesignrules

Stub

Min.enclosurespacerequiredbydesignrules

(B)-multiplelayersofinterconnects

Figure 20: Unwanted capacitive loads.

The followings should be considered to minimize the unwantedcapacitances

(1) In multiple-drop cases, the length of stubs should be minimized.

(2) In multiple layer interconnect case, the space between the viaand the edge of metal layers should be minimized.



Input impedance of short-circuit terminated losslesslines

Short-circuit terminated lossless lines : ZL = 0.

Zin(z) = jZotan(z).

A lossless line with a short-circuit termination exhibits an inductivecharacteristic !



Quarter-Wave Transformer

z=0

V

ZL

I L

V(0)

z

Z(z)in

ZoV

l/4

Figure 21: Quarter wave transformer.

Zin(4) = Zo

[ZL + jZotan(z)

ZL + jZLtan(z)

]z=

4

=Z2oZL

. (43)

or in the following form

Zo =

ZLZin(4). (44)



Application of Quarter-Wave Transformer

If ZL and Zo are known, this relationship allows us to choose atransmission line segment of length /4 whose impedance is given

by Zin(4), as shown in Fig.22, to eliminate the reflection at the farend of the transmission line.

l/4

Zo

Zo Z

Zo

Z

Longinterconnect

Verysmalldistance

Strongreflection

StrongreflectionZeroreflection

Zo

Impedancematchingnetwork

L

L

Figure 22: Quarter wave transformer as an impedance-matching network.

Note that reflection still exists between the added impedancematching network and the load. However, since the distance

between them is so small, the effect of ringing (multiple reflectionsbetween the matching network and the load) is negligible.

Because the length of the quarter-wave transformer is determined

by the wavelength of the signal, impedance matching using aquarter-wave transformer is only effective at a given frequency quarter-wave transformer can only be used for narrow-band

impedance matching.


Transmission Line Effects

In this section, we investigate the voltage and current ofinterconnects (i)without termination at both the near and far ends

of the interconnects, (ii) with termination at the near end but notermination at the far end, and (iii) with termination at both the

near and far ends. These studies will reveal an importantcharacteristics of long interconnects, called ringing, which gives rise

to inter-symbol interference and limits the rate of data transmission.


Transmission Line Effects (contd)

No Termination

Consider a step voltage of Vs = 5V applied to a lossless transmissionline. Let the source impedance be Zs = 5Zo, where Zo is the

characteristic line impedance. Let the propagation delay of the linebe . We derive the waveform of v1(t) and v2(t).

21Zs=5Zo Zo

5V

Z1

Z=infinityL

Figure 23: No termination.

To simplify analysis, we assume Z1 = Zo. Note that this assumption

is not true in reality because a lossless line terminated with anopen-circuit is a capacitor with impedance

Z1 =Zo

jtan(z). (45)

When the wave arrives at node 1 for the very first time, the voltage

and current at node 1 are computed from

V1 =Zo

Zo+5ZoVs =

565 = 0.83V,

I1 =Vs

Zo+5Zo= 56Zo .

(46)



When the wave arrives at node 2 for the very first time, the voltageof the incident wave is given by V +2,1 = 0.83V, where the firstsubscript identifies the node and the second subscript identifies that

this is the first time the wave arises at the node.

The voltage and current reflection coefficients of node 2 arecomputed from

V 2 =ZLZoZL+Zo

ZL=

= 1,

I2 = V 2 = 1,(47)

from which we obtain the voltage and current of the reflected waveat node 2

V 2,1 = V 2V+2,1 = 0.83V,

I2,1 = I2I+2,1 = 56Zo .

(48)

The total voltage and current at nod 2, after the first reflection, are

obtained from

V2,1 = V+2,1 + V

2,1 = 0.83V + 0.83V = 1.66V,

I2,1 = I+2,1 + I

2,1 =

56Zo 56Zo = 0.

(49)



When the reflected wave arrives at node 1 for the very first time, wehave V +1,1 = 0.83V and I

+1,1 = 56Zo . The voltage and current

reflection coefficients at node 1 are obtained from

V 1 =ZLZoZL+Zo

ZL=5Zo

= 23 .

I1 = V 1 = 23.(50)

The voltage and current of the reflected wave at node 1 arecomputed from

V 1,1 = V 1V+1,1 =

230.83V = 0.5533V,

I1,1 = I1I+1,1 = (23)( 56Zo) = 59Zo .

(51)

The total voltage and current at node 1, after the first reflection,

are given by

V1,1 = V+1,1 + V

1,1 + 0.83V = 0.83V + 0.5533V + 0.83V = 2.2133V,

I1,1 = I+1,1 + I

1,1 +

56Zo

= 56Zo + 59Zo + 56Zo = 59Zo .(52)



When the wave arrives at node 2 for the second time

V +2,2 = 0.5533V,V 2,2 = V 2V

+2,2 = 0.5533V.

I+2,2 =59Zo

I2,2 = I2I+2,2 = 59Zo .

(53)

The resultant voltage and current at node 1 are obtained from

V2,2 = V+2,2 + V

2,2 = 0.5533 + 0.5533 = 1.12V,

I2,2 = I+2,2 + I

2,2 = 59Zo + 59Zo = 0.

(54)

When the reflected wave arrives at node 1 for the second time

V +1,2 = 0.5533V,V 1,2 = V 1V

+1,2 =

230.5533V = 0.3687V,

V1,2 = V+1,2 + V

1,2 = 0.5533 + 0.3687 = 0.93V,

I+1,2 = 59Zo ,I1,2 = I1I

+1,2 = (23)( 59Zo) = 1027Zo .I1,2 = I+1,2 + I1,2 = 59Zo + 1027Zo = 1027Zo .

(55)



The total voltage and current at node 1 after the 2nd reflectionbecome

V1 = 2.22 + 0.93 = 3.15V,

I1 =59Zo 527Zo = 527Zo .

(56)

When the wave arrives at node 2 for the third time

V +2,3 = 0.3687V

V 2,3 = V 2V+2,3 = 0.3687V.

V2,3 = V+2,3 + V

2,3 = 0.7374V,

I+2,3 =1027Zo

,

I2,3 = I2I+2,3 = 1027Zo .

I2,3 = I+2,3 + I

2,3 = 0.

(57)

When the wave arrives at node 1 for the third time

V +1,3 = 0.3687VV 1,3 = V 1V

+1,3 =

230.3687V = 0.2458V.

V1,3 = V+1,3 + V

1,3 = 0.3687 + 0.2458 = 0.6145V,

I+1,3 = 1027Zo ,I1,3 = I1I

+1,3 = 23( 1027Zo) = 1081Zo ,

I1,3 = I+1,3 + I

1,3 = 1027Zo + 1081Zo = 2081Zo .

(58)



The total voltage and current

V1 = 3.15 + 0.6145 = 3.745V,I1 =

527Zo

2081Zo

= 581Zo

.(59)

When the wave arrives at node 2 for the fourth time

V +2,4 = 0.2458VV 2,4 = V 2V

+2,4 = 0.2458V.

(60)

When the wave arrives at node 1 for the fourth time

V +1,4 = 0.2458V

V 1,4 = V 1V+1,4 =

230.2458V = 0.1639V.

(61)



1

2

3

4

5

6

0 t 2t 3t 4t 5t 6t 7t 8t 9t 10t Time

Voltage

V1

0.83V

1.66V

2.78V

2.22V

3.15V

3.52V3.77V

4.02V4.19V

4.36V

V2

5/6Zo

5/9Zo

5/27Zo

5/81Zo

Current

Current

Figure 24: Transmission line effect.

Ringing exists due to the multiple reflection at both the near andfar ends of the transmission line, arising from impedance mismatch

at both the near and far ends of the line.

The duration of the ringing depends upon the delay of the line.The smaller the , the shorter the ringing the fast thevoltage at the far end of the transmission line reaches itssteady-state value (5V).



21Zs=5Zo Zo

5V

Z1

Z=inftyL

0.83V

1.39V

0.93V

0.62V

1.66V

1.12V

0.74V

0.83V

0.83V

0.56V

0.56V

0.37V

0.37V

0.25V

V1

0.83V

2.22V

3.15V

3.77V

V2

1.66V

2.78V

3.52V

4.02V

Figure 25: Multiple reflections.



Zo

Zo Zin

VerysmalldistanceStrongreflection

Zeroreflection

Zo



Zo Zo

VerysmalldistanceStrongreflection

Zout

Longinterconnect

Zo Zo

Figure 26: Impedance matching.

For long interconnects, impedance-matching networks are requiredat both the near and far ends of the interconnects to minimize the

reflection at the near and far ends of the interconnects minimize the ringing of the signals on the interconnects.

Strong reflection, however, does exist at the interface between the

driver and the impedance-matching network at the near end andbetween the load and the impedance-matching network at the far

end. Because the impedance-matching networks are very close tothe driver/load, the amount of time that the voltage needs to climb

up to its steady-state value is much smaller the ringing effectbecomes negligible Impedance-matching networks should beplaced as close as possible to the driver and the load !

Although, ideally, only the impedance-matching network at the farend of the interconnect is needed to eliminate the ringing. Inreality, a perfect impedance matching is difficult to achieved. Some

waveform will be reflected at the far end of the interconnect. Thetermination at the near end will therefore further eliminate the

reflection. Most high-speed interconnects require doubletermination.



Terminated at the Near End

21Zs=Zo Zo

5V

Z1

Z=infinityL

Figure 27: Terminated at the near end.

Consider a step voltage of Vs = 5V applied to a lossless transmission

line. Let the source impedance be Zs = Zo, where Zo is the linecharacteristic impedance. Let the delay of the line be . We derive

the waveform of v1(t) and v2(t).

To simplify analysis, we assume Z1 = Zo. When the wave arrives atnode 1 for the very first time, the voltage at node 1 is computed

from

V1 =Zo

Zo + ZoVs =

1

25 = 2.5V (62)



When the wave arrives at node 2 for the very first time, the voltageof the incident wave is given by V +2,1 = 2.5V.

The reflection coefficient of node 2 is computed from

V 2 =ZL ZoZL + Zo

ZL=

= 1, (63)

from which we obtain the voltage of the reflected wave

V 2,1 = V 2V+2,1 = 2.5V (64)

The voltage at nod 2, after the first reflection, is obtained from

V2,1 = V+2,1 + V

2,1 = 5V (65)



When the reflected wave from node 2 arrives at node 1, we haveV +1,1 = 2.5V. The reflection coefficient at node 1 is obtained from

V 1 =ZL ZoZL + Zo

ZL=Zo

= 0. (66)

The reflected wave at node 1 is computed from

V 1,1 = V 1V+1,1 = 0. (67)

No wave is reflected at node 1.

V1,1 = V+1,1 + V

1,1 = 2.5V. (68)

The total voltage at node 1 is obtained from

V1 = V1,1 + 2.5 = 5V. (69)

Although V2 = 5V after the delay , due to the existence of thereflected wave traveling towards node 1, the second data can not be

sent to the line until the reflected wave from node 2 is fully

absorbed at node 1 the max. data rate = 12

.



Double Termination

Consider a step voltage of Vs = 5V applied to a lossless transmissionline. Let the source impedance be Zs = Zo and the load impedance

be ZL = Zo, where Zo is the line characteristic impedance. Let thedelay of the line be . We derive the waveform of v1(t) and v2(t).

21Zs=Zo Zo

5V

Z1

Zo

Figure 28: Double termination.

The line is terminated with its characteristic impedanceZ1 = Zo.

When the wave arrives at node 1 for the first time, the voltage and

current of node 1 are computed from

V1 =Zo

Zo+ZoVs =

125 = 2.5V,

I1 =52.5Zo

Vs =2.5Zo.

(70)



When the wave arrives at node 2 for the very first time, the voltageand current of the incident wave are given by V +2,1 = 2.5V andI+2,1 =

2.5Zo, respectively.

The voltage and current reflection coefficients of node 2 arecomputed from

V 2 =ZLZoZL+Zo

ZL=

= 0,

I2 = V 2 = 0.(71)

from which we obtain the voltage and current of the reflected wave

V 2,1 = V 2V+2,1 = 0,

I2,1 = I2I+2,1 = 0.

(72)

No reflection at node 2.

The voltage and current at nod 2 are obtained from

V2,1 = V+2,1 + V

2,1 = 2.5V,

I2,1 = I+2,1 + I

2,1 =

2.5Zo.

(73)



The total voltage at node 1 is 2.5V.

The total propagation time of the wave on the transmission line is .

Note that although ideally a perfect impedance matching at the farend will eliminate refection, in reality a perfect impedance matching

is difficult to achieve. Some reflection is enviable. For this reason,double terminations are needed to minimize multiple reflections.

When double termination is employed, V2 =Vs2 50% signal

(voltage) loss at the far end of the line. Also, DC powerconsumption exists. These are the prices paid for the elimination of

reflection.


Termination Schemes

This section deals with termination schemes of interconnects. Thepros and cons of various termination schemes, namely series

termination, parallel termination, AC parallel termination, andThevenin termination, are investigated in detail.


Termination Schemes (contd)

No Termination

Series Termination

Parallel Termination

AC Parallel Termination

Thevenin Termination


No Termination

21 Zo=50Ohms

Z L,2ZL1

Vin

Figure 29: Inverter drivers without termination.

Because ZL,2 is very large, 2 =ZL2 ZoZL2 + Zo

1. Strong reflection atthe far end of the line. Voltage doubles at node 2.

ZL1 is the output impedance of the driving inverter. It varies with

the output voltage of the inverter in the following ways

ZL1 =

Rn, when Vout is low

Rp, when Vout is highRo,n||Ro,p, when Vout is in transition

(74)

where Rn and Rp are the channel resistance of nMOS and pMOS

transistors when in triode, respectively, and Ro,n and Ro,p are theoutput resistance of nMOS and pMOS transistors when in

saturation, respectively. Note that we have neglected the regionswhen one of the transistors of the inverters in triode and the otheris in saturation.

The variation of ZL1 gives rise to reflection at the near end of thetransmission line.


No Termination (contd)

Also note reflection also exists even if the signal is of lowfrequencies. Sharp transitions contain high-frequency components.These high-frequency components are subject to transmission line

effect because their wave length is comparable to the length of theline.

T

T/2 w s2w

s3w

s4w

sw

TimeDomain FrequencyDomain

Figure 30: Signal sharp transitions contain high-frequency components.

Fourier series expansion of the periodic signal shown

x(t) =

n=Cne

jnst, (75)

where s =2

Tand Cn =

1

T

T0x(t)ejnstdt.


Series Termination

21 Zo=50Ohms

ZL2ZL1

Vin

Rs

Figure 31: Inverter driver with series termination.

Because ZL,2 is very large, 2 =ZL2 ZoZL2 + Zo

1. Strong reflection atthe far end of the transmission line The voltage at the far endequals to the applied voltage.

ZL1 is the output impedance of the driving inverter. It varies withthe output voltage of the inverter. An explicit termination resistorRs is inserted to ensure ZL1 = Zo no reflection at the near end.The min. delay is the time for an around trip.

Drawbacks - Although Rs can ensure that ZL1 = Zo for a given

output voltage, the variation of the output impedance of theinverter driver gives rise to ZL1 Zo for other output voltage,resulting in reflection at the near end of the transmission line aperfect impedance matching at the near end is difficult to achieve.


Parallel Termination

21 Zo=50Ohms

ZL2ZL1

Vin

Zo

Figure 32: Inverter driver with parallel termination.

Interconnects are terminated with the characteristic impedance at

the far end.

Drawbacks - the termination resistor consumes significant amountof DC power when the output of the driver is at Logic-1.


AC Parallel Termination

21 Zo=50Ohms

ZL2ZL1

Vin

C T

R T

Figure 33: Inverter driver with parallel termination.

During state transitions, CT behaves as a short circuit ZL2 = RT = 50 perfect impedance matching.

During Logic-0 and Logic-1, CT behaves as an open-circuit zeroDC power consumption of driver due to termination.

Design difficulties : ZT = RT +1

jCTvaries with frequency. The

rising and falling edges of square waves contains a large number offrequency components a perfect impedance matching can onlybe achieved for a specific frequency.

Deficiencies - When the transmitter is in an idle state(high-impedance state), the line is very sensitive to noise because

the far end of the interconnect is floating.


Thevenin Termination

21Zo=50Ohms

ZL2ZL1

Vin

R2

R1

Figure 34: Thevenin termination.

Floating input node of parallel termination in the idle states is

eliminated.

ZT = R1||R2.

Drawbacks - DC power consumption exists regardless of the state of

the driver.


Impedance-Matching Networks

This section investigates the pros and cons of off-chip and on-chippassive impedance-matching networks. In addition, it examines the

design of on-chip active impedance-matching networks. Thedifficulties encountered in realization of off-chip and on-chip

termination resistors are studied. Various on-chip activeimpedance-matching networks are investigated.


Impedance-Matching Networks (contd)

Difficulties encountered in realization of on-chip termination

resistors

50 termination resistors can be realized using poly resistors due totheir low resistance and high accuracy (as compared to n-well

diffusion resistors).

Poly in standard digital CMOS processes is silicided to reduce sheet

resistance. Typical sheet resistance of poly of 0.18m CMOSprocesses : R28 with 30% errors.

A care should be taken for parasitic resistance of metal wires and

contacts (Typical 0.18m CMOS processes : 0.07 for Metal layers.8/contact, and 2.5/Via).

L

W

Poly Contact

Metal-1

Figure 35: Poly resistors as impedance-matching networks.

R =RC2

+RC2

+R2L

W= 8 + 8

L

W. (76)

The resistance of poly resistors can not be tuned to match the

characteristic impedance of interconnects.



Difficulties encountered in off-chip passive termination

The resistance of passive resistors has a large error.

Resistor

Lead

PCBtrace

VIA hole

Figure 36: Passive resistor termination.

The leads of passive resistors, the PCB trances and vias (if not

surface-mounted resistors) introduce unwanted parasiticcapacitances and inductances that drive the impedance of the

resistors away from 50 a perfect impedance matching usingpassive resistors is difficult to achieve.



On-chip Active Termination

Triode Symmetricalload Transmissiongate(TG)

DD 01D 2D N

Digitaltrimming

V

Vc Vc Vc VcV

I

V V

III

I

M0M1M2M N

Figure 37: Termination networks.



Triode - pMOS should be biased in deep triode to achieve betterlinearity small operation voltage range (i.e. Vsd must be small)

Triode

VcV

I

V

I

Vdd-Vc

Pich-off

Betterlinearityinthisregioncalleddeeptriode

Vdd

Theslope(conductance)varieswith Vc

Figure 38: Termination network realized using pMOS biased in deep triode.



Symmetrical load [7] - provide a large voltage range. The resistanceis approximately constant at both low and high operation voltage V .

Symmetricload

VcV

I

V

I

Pich-off

Vdd

VtVsat

M1

M2 M1

M2

Symmetricload

D I

D I

Figure 39: Termination network using symmetric load.



Digital trimming [8]

The width of each transistor = 2NWref , where Wref is the width ofthe least significant bit transistor and N is the location of the bit.

Width range : All transistors are OFF, Wtotal = 0; All transistors

are ON, Wtotal = (1 + 2 + 22 + . . .+ 2N1)Wref .

All transistors , when ON, are biased in deep triode.

Table 3: Impedance matching using digital trimming

D2 D1 D0 Width Resistance

0 0 0 0 0 0 1 1Wref Rref0 1 0 2Wref Rref/20 1 1 3Wref Rref/31 0 0 4Wref Rref/41 0 1 5Wref Rref/51 1 0 6Wref Rref/61 1 1 7Wref Rref/7



Low-Power Active Termination [9]

Zo1 2

Figure 40: Low-power termination.

Both nMOS and pMOS are sized such that they provide 50

resistance when biased in deep triode.

When V2 = VDD, pMOS is ON (triode) and nMOS is OFF. No DCcurrent flows through pMOS.

When V2 = 0, nMOS is ON (triode) and pMOS is OFF. No DC

current flows through nMOS.

Design difficulties : the propagation delay of the inverter must be

sufficiently small, as compared with the propagation delay of thetransmission line.



On-Chip Termination [6]

nMOS and pMOS transistors when biased in triode arevoltage-controlled resistors. The resistance, however, is highly

nonlinear unless biased in deep triode.

When biased in deep triode, the voltage swing of the variableresistor is rather small.

Both nMOS and pMOS are biased in triode and connected inparallel to provide a matching impedance for both HIGH and LOWoutput stages of the driver.

Zo1 2

Vc1

Vc2

Figure 41: Large-swing termination.



Self-Regulated Series Termination [10]

In series termination scheme, the voltage at the far end (node 2)equals to the source voltage Vin due to farend = 1 and the voltage

at the near end (node 1) equals to half of the source voltage when aperfect impedance matching at th near end exists. When Zs Zo,

reflection at the near end exists and V1 Vin2 .

V1 =Vin2 can be used as the criterion of whether a perfect impedance

matching exists at the near end, as shown in Fig.??. The

termination resistance is adjusted by controlling the supply voltageof he pre-driver, which in turn controls Vgs(Vsg) of the driver.

VDD

VCComparator

VRef

Vin

Figure 42: Self-regulated series termination.


References

References

[1] E. Elmore, The transient response of damped linear network with particular

regard to wide-band amplifiers, J. Applied Physics, vol. 19, No. 1, pp. 55-63,Jan. 1948.

[2] R. Poon, Computer circuits electrical design, Prentice-Hall, 1995.

[3] R. Ludwig and P. Bretchko, RF Circuit Design - Theory and Applications,Prentice-Hall, 2000.

[4] J. Rabaey, Digital Integrated Circuits : A Design Perspective, 2nd edition,Prentice-Hall, 2004.

[5] M. Lee, An efficient I/O and clock recovery design for terabit integrated

circuits, Ph.D. Dissertation, Stanford University, August 2001.

[6] G. Ahn, D. Jeong, and G. Kim, A 2-Gbaud 0.7-V swing voltage-mode driver

and on-chip terminator for high-speed NRZ data transmission, IEEE J.Solid-State Circuits, vol. 35, No. 6, pp. 915-918, June 2000.

[7] J. Maneatis, Low-jitter process-independent DLL and PLL based on

self-biased techniques, IEEE J. Solid-State Circuits, Vol.31, No.11, pp.1723-1732, Nov. 1996.

[8] T. Gabara and S. Knauer, Digitally adjustable resistors in CMOS forhigh-performance applications, IEEE J. Solid-State Circuits, vol. 27, No. 8,pp. 1176-1185, August 1992.

[9] M. Dolle, A dynamic line-termination circuit for multi-receiver nets, IEEE J.Solid-State Circuits, vol. 28, No. 12, pp. 1370-1373, Dec. 1993.

[10] T. Knight and A. Krymn, A self-terminating low-voltage swing CMOS outputdriver, IEEE J. Solid-State Circuits, vol. 23, No.2, pp. 457-464, April 1988.


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