CSCE 612: VLSI System Design

Instructor: Jason D. Bakos

VLSI Design

What is VLSI?Very Large Scale IntegrationDefines integration level1980s hold-over from outdated taxonomy for integration levelsObviously influenced from frequency bands, i.e. HF, VHF, UHFSources disagree on what is measured (gates or transistors?)SSI Small-Scale Integration (0-102)MSI Medium-Scale Integration (102-103)LSI Large-Scale Integration (103-105)VLSI Very Large-Scale Integration (105-107)ULSI Ultra Large-Scale Integration (>=107)

Integration Level Trends

Obligatory historical Moores law plot

Integrated Circuits/MEMs

Today, VLSI refers to systems impl. w/integrated circuitsIntegrated circuit refers mostly to general manufacturing techniquemicro/nano-scale devices on a semiconductor (crystalline) substrateFormed using chemical/lithography processingWhat kind of devices / structures?transistors (bipolar, MOSFET)wires (interconnects and passives)diodes (junction, LEDs, VCSELs, MSM, photoconductor, PiN)MEMs (piezoelectric integration, accelerometers, gyroscopes, pressure sensors, micro-mirrors)For CMOS digital design, we only use MOSFET transistors (used as switches) and wires

Chips

Integrated circuits consist of:A small square or rectangular die, < 1mm thickSmall die: 1.5 mm x 1.5 mm => 2.25 mm2Large die: 15 mm x 15 mm => 225 mm2Larger die sizes mean:More logic, memoryLess volumeLess yieldDies are made from silicon (substrate)Substrate provides mechanical support and electrical common point

VLSI Design

Draw polygons that represent layers deposited on the substrateMore of an art than scienceOne 2-input NAND gate with 4 transistorsTypical microprocessor contains 50 200 million transistors (10-50 million gates)

Scale: approximately 10 um x 10 um

VLSI Design

Manual layout design is obviously not practicalDesign complexity:Manually drawing layout for a billion transistors would take too longEven if we couldHow to verify (test) designs for functionality, speed, power, etc.?Complexity scales faster than actual designHow to reuse designs?How to create human-readable designs?How to speed-up design process?These problems form a great deal of workElectronic Design Automation (EDA)a.k.a. CADAdvancing EDA technology, physical fabrication technology, advanced designs, and IP form bulk of work (and money) in VLSI

EDA Tools

Conclusion:This course is about using design tools to manage design complexity of VLSI systemsOnly way to learn tools: practice and work with tools individuallyMust teach IC fundamentals, but prevent course from becoming semiconductor theory, analog electronics, circuits, or digital logic courseTarget large-scale integration and EDAReach good balance between fundamental IC theory and automated large-scale design methodology80-90% of course time will be spent in labTutorials will provide basic knowledgeMust learn the tools on your own (assisted by instructor)

Course Overview

This course is called VLSI System DesignFocus on large-scale system design (CAD tools)CAD tools manage design and verification complexityWhat we haveLatest, most advanced CAD tools in the EDA industryThree primary playersSynopsys, #258 ($1.2 billion revenue)Cadence Design Systems, #259 ($1.1 billion revenue)Mentor Graphics, ?Comparison: Microsoft #95 ($36.8 billion), Intel #102 ($34.2 billion)Fabrication award for 500 nm CMOS fabrication processAMI C5N process with academic design kit (NCSU CDK)1.5 mm x 1.5 mm die size, multiple dies, packaging

EDA Tools

Big companies, lots of money, 40 years of integrated circuit design experience, conferences, journals, powerful PCs whats the problem?IC CAD tools are difficult to useWritten by electrical engineers (not professional programmers)Incredibly buggyNot documentedRely on ancient, outdated file formats for interoperabilityStill mostly rely on command-line interfacesUtilize outdated, primitive, buggy APIs for GUIsInherently required to solve hard problemsPlace components, route wiresMust utilize advanced heuristics that are only as good as fabrication process technology information and user input (garbage-in, garbage-out)

EDA Tools

Cadence toolsIC-Tools => IC5141 package (Linux)Collection of tools managed by Design Framework II (dfII)Virtuoso schematic/layout editorAnalog EnvironmentSpectre simulatorDiva DRC, EXT, LVSOther Cadence toolsSignalStorm => TSI42 package (Linux)Abstract Generator => DSMSE54 (Solaris)First Encounter => SOC42 package (Linux)SynopsysDesign Compiler (Linux)MentorHDL Designer (Linux)

What EDA Tools Can Do

Manual layout vs. EDA is like:Manual transmission vs. automatic transmissionHTML programming vs. FrontpageAssembly code programming vs. compiled high-level languageManual layout for small, optimized designs will always be superiorEDA techniques for larger-scale designs will always be superior (verification, reusability, NRE, etc.)Goal: do careful, manual design of smaller components (cells) and use EDA to combine them for large-scale design

What EDA Tools Can Do

My Design Flow

Digital cell library design

Cadence IC-Tools

Circuit Sim

Cadence IC-Tools

Characterization

Cadence SignalStorm

Abstract Generation

Cadence AbGen

Standard Cell Library

Behavioral VHDL Design

Mentor HDL Designer

Design Specification

char. info

process info, cell abstracts

Synthesis

Synopsys Design Analyzer

VHDL

Behavioral Simulation

Mentor ModelSim

Place-and-Route

Cadence First Encounter

Cell Timing Simulation

Mentor ModelSim

Verilog

Interconnect Timing Simulation

Mentor ModelSim

Course Organization

Course will be divided into unitsIntroduction: IC design and fabrication fundamentalsLecturesAssignments from textbookCMOS circuit design, layout, and simulationTutorial: Cadence IC-ToolsDesign projectsDevelopment of standard cell libraryCell library developmentTutorial: Cadence SignalStorm and Abstract GeneratorReport on cell libraryVHDL DesignLectures on VHDLTutorial: Mentor HDL DesignerDesign projectLogic SynthesisTutorial: Synopsys Design AnalyzerPlace-and-routeTutorial: Cadence First EncounterCourse projectTeams?Design?Fabrication?