A look at Intel Processors from the 4004 to the Pentium Pro

CS-350-2: Computer Organization and ArchitectureSpring 2004

David LenhardtMarcus O'MalleyChristopher Payne

Jonathan Taylor

Table Of Contents

Introduction…………………………………Page 2

Prelude to the 4004 Microprocessor………...Page 2

The 4004 Microprocessor………...………....Page 3

The 8008 Microprocessor………...………....Page 3

The 8080 and 8085 Microprocessors……….Page 4

The 8086 and 8088 Microprocessors……….Page 5

80286 Microprocessor………...………..…...Page 6

80386 Microprocessor………...………..…...Page 7

80486 Microprocessor………...…………….Page 8

Pentium Microprocessor………...………..…Page 9

Pentium Pro Microprocessor………...……... Page 10

Summary………...………..…………………Page 11

Bibliography………...………..……………..Page 12

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Introduction

Since the development of the 4004 microprocessor, Intel's microprocessors have greatly evolved. From the 4004 microprocessor all the way through the Pentium Pro, Intel manufactured new, faster, more efficient processors at an incredible rate. We will begin with the justification of the development of the 4004, and then discuss the architecture of the 4004 and the changes in the 8008. We will briefly touch on the 8080 and 8085 before explaining the significant features and changes in both the 8086 and 8088. After these came the 80286 in 1982, 80386 in 1986, and the 486 processors in 1991. The 486 processor was innovative because it was the first time that motherboards could be reused. Previous to its creation when a new processor was developed the motherboard was deemed obsolete. This new technology could support several versions of the 486 processor. Each significant improving upon each other until finally the Pentium processor and Pentium pro were created putting Intel back on top of the world of high-speed processors.

Prelude to the 4004 Microprocessor

In 1969, Intel agreed to produce a set of 12 calculator chips for Busicom. However, Intel employee Marcian Hoff Jr., concerned with both the design complexity and the package requirements for each of the calculator chips, believed it was easier to have a single purpose computer that could perform all the functions. Masatoshi Shima, who worked for Busicom, and Stanley Mazor, who joined Intel late in 1969, contributed their own ideas, which furthered Hoff's idea. After Busicom accepted Shima and Hoff's idea about the development of a single purpose microprocessor, Intel hired Federico Faggin as the designer for the chip set. Faggin decided to develop a chip set called the 4000 series that consisted of the 4001 ROM chip, the 4002 RAM chip, the 4003 I/O expansion shift register chip, and the 4004 chip used as the central processing unit (CPU). Faggin focused on the circuit design and layout of the chip set while Shima worked on the logic for the 4004 chip. Together, they were able to produce the first functional 4004 chip in January of 1971. The 4004 chip became fully functional in March of 1971 after Faggin fixed two minor bugs. The designs of the 4002 and 4004 chips then received final amendments by Faggin before production of the 4000 chip set began in August of 1971.

Faggin felt that the 4000 chip set had far more potential than just being used for calculators. Unfortunately, Busicom owned the rights to the 4000 chip set architecture. Faggin requested that Intel obtain the rights to the chip set, but was unsuccessful due to the consensus by Intel management that the chip set was only good for calculator-like products. Faggin then proved the opposite to Intel's management when he demonstrated the use of a 4004 chip in a totally different application. He and Hoff then used this proof along with Busicom's financial troubles to convince the owner of Intel, Robert Noyce, and the rest of management to lower the price for development of the chips in exchange for nonexclusive rights to sell the chips (Faggin et Al., 1996).

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The 4004 Microprocessor

The 4000 chip set varies in the number of 4001 ROM chips and 4002 RAM chips it contains. At the 4004 chip set limit, it is able to support 16 256-kilobyte 4001 ROM chips, as well as 16 80-nibble 4002 RAM chips, where every 20 nibbles represent one register. The 4001 and the 4002 chips drive the 4003 chip, and are equipped with a 4-bit output port. The 4004 chip controls both the 4001 and 4002 chips with the use of five control lines. It includes 16 4-bit registers. Five of the registers consist of a 4-bit accumulator and four 12-bit push-down address stacks where one stack is an instruction pointer and the other stacks are used as return addresses for subroutines. Another register is an arithmetic unit that is used for binary and decimal arithmetic. The other ten registers are used for various other purposes such as logic control and bus timing.

The 4004 chip contains 2,300 transistors and has a total of 45 different instructions, with 16 instruction types that are divided into three groups. The main group consists of 16 general instructions, the IO and RAM groups have 15 instructions, and the accumulator group contains 14 binary arithmetic instructions. The 4000 architecture uses these instructions to address RAM data in several steps. First, a DCL instruction, which is the memory control instruction, selects four RAM chips out of 16 possible RAM chips. The send register control instruction then selects a single 4-bit nibble out of the 256 nibbles available from the four RAM chips that are selected. Finally, a single I/O and RAM instruction is executed on the 4-bit nibble (Faggin et Al., 1996).

The 4004 uses 12 bits for addresses, which allows up to four kilobytes of addressable memory. The 4004 uses a 4-bit multiplexed bus to transfer 4-bits of data at a time over the bus in a successive fashion. The 12-bits of the address are split up into two parts, where 8-bits are used for instructions and 4-bits are used for data (Wikipedia, 2004). A single four-bit instruction takes a total of eight cycles per instruction because the multiplexor bus is only able to transfer four bits at a time. Of those eight cycles, the first three cycles of the instruction are used to gather the address, which is followed by the next two cycles that are used to gather the instruction to complete the fetch stage. The final three cycles are used to perform the instruction, which includes the decode, execute and cycle stages, respectively. If the instruction is an eight-bit instruction, it is then processed in 16 cycles. The 4004 is able to compute 60,000 instructions per second on average at the frequency of 740.74 kilohertz, although the exact number of instructions depends on the total number of four-bit and eight-bit instructions done within the second (Bunyan, 1998).

The 8008 Microprocessor

Intel started the development of the 8008 microprocessor before the release of the 4004. While Intel searched for a designer for the 4004 chip set, the company decided to accept a request from Computer Terminal Corporation (CTC) for the design of a single eight-bit microprocessor. Intel then assigned their newly hired employee, Hal Feenay, to work on the specifications of the chip. Feenay worked with Mazor on the chip until CTC had financial troubles, which caused the project to halt temporarily. In January of 1971, Intel began work on the chip once again, and assigned Feenay to the design of the chip,

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under the supervision of Faggin. Faggin and Feenay then finished the detail design of the 8008, having used the proven design of the 4004 by March of 1972 (Faggin et Al., 1996).

The 8008 microprocessor contains several upgrades from the 4004. The first change is that the microprocessor's frequency is increased to a range of 400 to 800 kilohertz (Carpinelli, 2001). A second change is the 8008 contains 3,500 transistors (Intel, 2004). Another change includes the microprocessor processing eight-bits at a time. This change is coupled with an upgrade to the multiplexed bus, which is able to transfer eight bits at a time. Another difference in the 8008 is that the number of bits for memory addresses are increased to 14, which allows up to 16 kilobytes of memory to be addressable. This difference allows Intel to increase the number of bits in both the instruction pointer and the subroutines to 14-bit addresses. Furthermore, the 8008 has a total of seven separate return addresses for subroutines instead of the three that the 4004 has. Intel also increased the size of the accumulator and binary arithmetic registers to eight-bits. In addition, Intel included six eight-bit data registers as well as two eight-bit temporary registers.

Another upgrade that is incorporated into the 8008 microprocessor is that the instruction set is increased to 48 different instructions. The instructions are divided into five main groups, which include index register instructions, accumulator group instructions, program counter and stack instructions, I/O instructions, and machine instructions. The instruction groups are then further divided into sub-groups that corresponds with the instruction type as well as whether the instruction uses memory or registers for the instruction.

The 8008 includes new features as well. The first significant feature that the 8008 contains is the introduction of interrupts while an instruction is being executed. When a device raises the interrupt line that is connected to the CPU, then at the fetch stage of the next instruction that is to be executed, the contents of the 14-bit instruction pointer are copied out into a stack. Then the address of the first instruction in a subroutine used to process the interrupt is copied into the instruction pointer at the next fetch stage. The instructions of the interrupt are executed, and finally the original contents of the instruction register are then copied back into the instruction pointer to continue the original instructions before the occurrence of the interrupt.

The inclusion of the ready line is a second, significant feature that is included in the 8008. The ready line allows the 8008 to work with a combination of various memory types that run at different speeds. If the 8008 microprocessor requests a datum from memory, and the datum is not ready, the 8008 would need to wait until the memory that contains that datum gives a signal on the ready line. The 8008 microprocessor is synchronized with memory by the ready line because the 8008 is only able to access the datum at each memory cycle when the ready line is lifted (Intel, 1972).

The 8080 and 8085 Processors

The 8080 and 8085 microprocessors include several changes from the 8008. One of the most significant changes that both microprocessors have is that their machine code is backwards compatible with the 8008 microprocessor. That meant that 8080 and 8085 both can reuse the machine code written for the 8008 (Carpineli, 2001).

The 8080 was released in 1974. It includes a 16-bit address bus that is able to

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access up to 64 kilobytes of memory. The 8080 also includes a separate eight-bit data bus, which is a contrast from earlier processors that uses a single multiplexed bus (Gwennap, 2003). While the address bus accesses memory and I/O addresses, the data bus accesses data. In addition, the 8080 uses a 16-bit instruction pointer, along with six 8-bit general purpose registers that are combined into 16-bit pairs where each register has a specified partner with which it is paired. The pair of temporary registers that the 8008 has are also able to hold 16 bits together, but are used solely for internal execution of instructions. Intel also uses a 16-bit stack pointer in the 8080 in exchange for the seven levels of address stack that the 8008 microprocessor uses. The stack pointer contains the address of the next available location in memory that can be used for the stack and is able to point to any addressable location in memory (Intel, 1974).

By 1976, Intel had released the 8085 microprocessor. It includes several differences over the 8080. One difference is while the 8080 runs at two megahertz, the 8085 runs at 6.25 megahertz. Another change is that the 8085 uses only +5 volts for power instead of both +12 volts and +5 volts that the 8080 needs (Hamzah, 2001). Another difference is an increase to 74 separate instructions from the 72 instructions that the 8080 can perform although both processors still have the same four address modes. Those four different address modes for instructions include direct, register, register indirect and immediate (Intel, 1974). Finally, the 8085 contains 6,500 transistors, which is an increase from the 4,500 transistors that the 8080 has (Intel, 2004).

The 8086 and 8088 Processors

The next two processors that were released by Intel was the 16-bit 8086 and the 8-bit 8088, which were released in 1978 and 1979, respectively. Intel designed each microprocessor to contain 29,000 transistors, and they designed the 8086 to run at frequencies of five, eight and 10 megahertz, whereas the 8088 ran at 4.77 megahertz and eight megahertz (Intel, 2004). Intel increased the 8086's addressable memory to one megabyte along with a 20-bit address bus used to address memory. They also included an external 16-bit data bus in the 8086 but Intel then decreased the 8088's data bus to 8-bits. Intel designed the address bus and the data bus to be a multiplexed bus, which was able to send both data and address over the same bus. Intel kept the 8086 and 8080 architectures the same despite those changes (Intel, 1990).

The 8086's instruction set contains a total of 133 different instructions. The instructions are divided into several groups where each group represents an instruction type. Those instruction types are data transfer, arithmetic, logic, string manipulation, unconditional jump, control transfer, return from call, interrupts, and microprocessor control (Intel, 1990). Furthermore, there are at least seven address modes used to reference the datum required for an instruction, which include immediate, direct, register, register indirect, register relative, base plus index, and base relative plus index (Nalty, 1997).

The 8086 architecture uses a coprocessor architecture that consists of two different processors- the Bus Interface Unit and the Execution Unit. The Bus Interface Unit controls all external bus functions, which includes the instruction fetch, operand fetch, the storage of the results of operations on operands in main memory, and control of the prefetch instruction queue. The Bus Interface Unit uses the prefetch instruction queue

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to store up to six bytes of instructions at a time. The Execution Unit, which contains an arithmetic logic unit, eight general-purpose registers, two temporary registers, and queue control logic, is used to decode and execute the instructions it receives from the Bus Interface Unit, and then pass the results of those instructions back to the Bus Interface Unit. Both processors are able to work separately yet concurrently in a pipeline approach, where the Execution Unit executes the instructions given to it by the Bus Interface Unit while the Bus Interface Unit fills the prefetch queue with new instructions if there is room available in the queue (Rucinski, 2003).

The 8086 architecture introduces another significant feature that became known as segmented memory. The 8086 contains four 16-bit segment registers that can access up to 256 Kilobytes at a time when all four registers are combined. The first of the segments is the code segment that holds instructions, the second is the data segment that holds data references, the third is the stack segment that stores return subroutine addresses and the final segment is an extra segment that is used by string operations to hold memory addresses. Each of these segments are pointers that holds the base address of each of their respective segments (Intel, 1990). However, there is a problem in that the address bus is 20 bits whereas the segment registers is only 16 bits. Intel remedied this problem with a two-step solution. First, the segment register address is multiplied by 16 to shift the address over to the left by four bits, which allows the address to be transferred over the 20-bit address bus. Then, the segment address is increased by the addition of an address in a 16-bit offset register, whose sum results in the true, physical address in memory. The 16-bit registers that hold the offset are the instruction pointer for the code segment, the stack pointer for the stack segment, and the source and destination index registers that could be used with any of the segments. This combination of the segment registers and the registers that hold the offset would allow the entire megabyte of memory to be addressable. However, several memory addresses are dedicated or reserved for specific purposes such as the Interrupt Vector table and are not suppose to be used as part of a segment (McQuire, 2002).

The 80286 Processor

The Intel 80286 processor, officially named the iAPX 286, was introduced in February of 1982 (Wikipedia, 2004b). The 80286 processor contains 134,000 transistors and the same basic set of registers, address modes, and instructions as its predecessors, the 8086 and 8088. It is also upward compatible with the 8086 and 8088 (Intel, 1990).

Like its predecessor, the 286 is a 16-bit architecture. It is available in clock speeds of 8, 10, and 12 megahertz. It operates in two modes, 8086 real address mode and protected virtual address mode. In 8086 real address mode programs use real addresses with up to one megabyte of address space. In this mode the processor is really just a faster 8086. In protected virtual address mode the processor provides for more addressable memory, multi-user protection, and virtual memory.

In order to expand on the addressable memory of the 8086, the 286 uses a table in which an entry, called a descriptor contains the starting address for its corresponding segment. The descriptor is eight bytes long with the first 24 bits used for the segment start address, which allows for 16 megabytes of addressable memory. In order to achieve multi-user protection each user is given their own descriptor table. This way the user can

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only access segments for which there are descriptors in their table. This gives each user their own address space and the illusion of having a dedicated 286, which is called a task.

One of the major advancements from the 8086 is virtual memory. The 286 can address up to one gigabyte of virtual memory. Keeping some of the some of the addressable segments of a program on disk rather than in main memory accomplishes this. If a program tries to access a segment that is on the disk and not in main memory, then an interrupt handler will move the segment from disk into memory. If memory is full then the handler will move a segment out of memory into the disk to make room for the segment from the disk (Morse, 1987).

The 80286 base architecture has fifteen registers grouped into four categories. It contains eight 16-bit general registers used to contain arithmetic and logical operands, four 16-bit special purpose registers used to select segments of memory immediately addressable for code, stack, and data, and three 16-bit special purpose registers used to record or control certain aspects of the processor state including the Instruction Pointer (Intel, 1990).

The 80286 can reference zero, one, or two operands. The operand can reside in a register, in memory, or in the instruction. Zero operand instructions are one byte long, one operand instructions are two bytes long, and two operand instructions are anywhere from three to six bytes long. One operand instructions can reference a register or memory location. Memory is addressed using a 32-bit pointer consisting of a 16-bit segment selector and a 16-bit offset. The segment selector selects the segment in memory and the offset specifies the byte address within the segment. Memory can be accessed either as bytes or words, with words consisting of any two consecutive bytes addressed with the least significant byte stored in the lowest address (Intel, 1990).

The local bus interface has 24 address lines, 16 data lines, and 8 status and control signals.

The 80386 Processor

The Intel 80386 processor, code named P3, was first delivered to customers in 1986. The 386 is a 32-bit architecture and can address up to four gigabytes of memory (wikipedia, 2004c). It contains 275,000 transistors, and consists of a central processing unit (CPU), a memory management unit (MMU), and a bus interface. It has eight 32-bit general-purpose registers and one 32-bit register used for the Instruction Pointer. The 16-bit registers of the 8086, 80186, and 80286 are retained as sub registers (Morse, 1987). The CPU consists of the execution unit and the instruction unit. The execution unit contains the eight 32-bit registers, which are used for address calculations and data operations. The instruction unit is used to decode instruction opcodes and store them in the decode instruction code for use by the execution unit (Intel, 1990).

The MMU consists of a segmentation unit and a paging unit. The paging unit operates beneath the segmentation unit allowing management of the physical address space. Memory is organized into variable length segments up to four gigabytes in size. Each task can have up to 16,381 segments of four gigabytes each for a maximum of 64 terabytes of virtual memory per task. Like the 286, the 386 operates in two modes: Real Address Mode and Protected Virtual Address Mode. Real Mode operates as a very fast

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8086 and is necessary to set up the processor for Protected Mode, which provides sophisticated memory management and paging.

The memory management technique of paging is used for the virtual memory of the 386. The pages are each 4096 bytes in size. When a program tries to access a page that is not in main memory then a page fault is generated, which passes control to an interrupt handler. The handler copies the page from the disk into memory. If there isn’t enough room in memory then the handler swaps out a page from memory to the disk to make room for the new page. Once this is done the handler passes control back to the program. Pages are mapped using a page directory and page table. The page directory is an array of double words, each 32 bits in length, which splits the memory space into page groups. The top 20 bits, bits 12 to 31, is used for the page table address, which gives the physical location of the page table for the page group needed. The page table, like the page directory, is an array of 32-bit double words. This splits the page group into pages, each 4096 bytes in length. The top 20 bits, bits 12 to 31, is used to address the location of the page frame that holds the page (Morse, 1987).

The bus interface offers address pipelining and dynamic data bus sizing. It has separate parallel buses for data and address. The address pipelining allows a memory interface to operate with one less wait state than normal. Dynamic data bus sizing allows the processor to handle a mix of 32- and 16-bit external buses on a cycle-by-cycle basis.

The 80486 Processor

The 8048DX was released in 1989. It was a 32-bit processor containing 1.2 million transistors. It was able to handle 26.9 Million instructions per second (MIPS) at 33 MHz. IT also contained an 8 KB on-die cache. This allowed the processor to pull from cache rather then access external memory. The Intel 486 was developed in 1991. Its intension was to bring the 386 together with an internal math coprocessor at the same time adding speed. It was also the first processor designed by Intel to be upgradeable. Previous to the 486 when processors became obsolete the entire motherboard had to be replaced. With this new technology the same CPU socket could accommodate several different versions of the 486.

The first version was the 486SX, which was very powerful and efficient for its time. It was twice as fast as the 386. It came in 176 lead Thin Quad Flat Pack (TQFP) package and was about the thickness of a quarter. The SX was followed by the 486DX2 and 486DX4. These utilized speed-multiplier technology that allowed the chip to operate at clock cycles greater then the bus speed. They also introduced Reduce Instruction Set Chips (RISC). The DX2 offered 8 KB of write-through cache and the DX4 offered 16 KB. Using RISC this cache allowed the chip to maintain its one clock cycle per instruction operation. The 8 KB cache combined with a 106 MB per second burst bus at 33.3 MHz was a huge improvement from the 386. It also came with eight 32-bit general-purpose registers. Those registers held data or address quantities. It could support data operands up to 32 bits and bit fields of 1 to 32 bits. Another feature was the flag register which is a 32-bit register named EFLAGS. This was used to control certain operations and indicate the status of the processor.

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The 486 had all the features of the 386, but with several improvements for speed. It was completely compatible with the 386 MMU (memory management unit). The 486 MMU consisted of segmentation unit and a paging unit. Segmentation was for managing logical address space and the paging unit worked along with the segmentation however it was not needed for operation. It could be turned off if it was not desired.

The 486 used segments for improved protection by isolating and protecting applications and the operating system from each other. Memory would be organizes into segments up to four gigabytes in size. Each segment had attributes such as location, size, type and protection characteristics. The 486 microprocessor could have a maximum of 16,381 segments of four gigabytes in size.

There were two distinct physical address spaces on the 486: the memory and the I/O. The I/O space was 64 KB and could be divided into 64 K 8-bit ports, 32K 16-bit ports, or 16K 32-bit ports. These I/O ports were accessed through the IN and OUT I/O instructions.

When the system boots up it has two possible modes: real mode and protected mode. Real mode has the same base architecture as the 8086, but is allowed access to the 32-bit register of the 486. The primary purpose of real mode was to setup the processor for protected mode. In real mode the maximum memory size allowed is 1 MB. Also paging was not allowed in real mode so the linear addresses are the same as the physical ones. The 486 processor wasn’t fully operational until it is operates in protected mode. Once this happened the linear address space was increased to its full potential of 4 GB. Protected mode allowed for operations to be done that are especially optimized for multitasking operating systems. Most of the same capabilities were retained in real mode but the addressing space increase and how the addressing mechanism works are greatly improved in protected mode. Paging was also provided in protected mode where it wasn’t available in real mode. Paging allowed the 486 processor to manage very large segments. The paging mechanism translated the protected linear address into physical address.

Another major feature of the processor was the cache. The on-chip cache was a unified code and data cache. It was used for instructions and data cache and acts on the actual physical address. The cache memory was split into four 2 KB blocks containing 128 lines. With each 2 KB block there are 128 21-bit tags. Also with each line in the cache there was a valid bit.

The 486 processor was a great improvement from the 386. Some of the major changes included: increased bus speed, supported on-chip cache, a new page protection feature, as well as the ability to upgrade without having to replace the entire motherboard. These improvements paved the way for the Pentium processor.

Intel Pentium

The Pentium processor was introduced in 1993, as the 5th generation processor produced by Intel. Intel’s main intention of creating the Pentium processor was to retake the speed crown from many other processor manufacturers. Examples of such companies were Apple Macintosh and IBM/Motorola Power PC. The Pentium processor introduced a faster bus speed going from 30 MHz to 60/66 MHz, which boosted the processor’s performance significantly.

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Even though Intel added some additional functions to the Pentium processor, the chips fundamentals remained the same. The application instruction set used by the Pentium was the same as the earlier 386 and 486 processor, thus making all application software used with the previous chips compatible with the Pentium. Also compatible with the 386 and 486 was the on-chip memory management unit. There were some extensions added to the application instruction set to house the Pentium’s additional functionality. One function the Pentium had over its predecessors was two instruction pipelines.These pipelines allowed the Pentium to issue two integer instructions or one floating-point instruction to the clock at one time. An additional function introduced was the ability to computer floating-point math. Although this was a great improvement in processor technology it did have a glitch. The 60 and 66 MHz Pentium processors had a contained an erratum, which meant that long division calculations would come out incorrect. This problem resulted in the processor having to approximate its output. Even though Intel quickly fixed the problem, it left a bad impression of the company on its consumers.

The Pentium processor was released in two series. The first series, introduced in 1993, were the Socket 4 60 and 66 MHz chips, which had the floating-point problem. These chips ran off of a 5-volt power supply. The second series, released in 1995, were the 75 – 133 MHz chips, which were introduced after the floating-point problem was corrected. These chips ran off of a 3.3-volt power supply.

The Pentium processor introduced new functions that were extremely important to computer science. It also provided a processor to suffice the power hungry Windows 95. Ultimately, the Pentium could not live down the bad reputation for releasing the 60/66 MHz chips with the floating-point bug.

Intel Pentium Pro

In November of 1995 Intel released its generation 5 processor, known as the Pentium Pro. Even though Intel kept the Pentium name, the Pentium Pro’s architecture was quite different from its predecessor. The Pentium Pro completely changed how it executed instruction. It first translated the instruction into a RISC-like microinstruction and then executed them on a highly advanced internal core. Even though the Pentium Pro had the same clock speed as the Pentium, it performed almost twice a fast; the Pentium Pro was produced in speeds from 150 to 200 MHz. One of the major aspects of the Pentium Pro was that it had the L2 cache on the chip instead of on the motherboard. This was the first Intel chip to incorporate L2 cache on the chip. The cache came in sizes of 256KB, 512KB, 1Mb or 2Mb. The L2 cache was also non-blocking, allowing the processor to continue without waiting on a cache miss.

The Pentium Pro had super pipelining that increases the number of execution steps to 14, compared to its predecessor’s 5. The address ability of the Pentium Pro could hold up to 64 GB of memory because its address bus was widened to 36 bits. The Pentium Pro also supported quad processor configuration making it more attractive to the

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server market. It also had out of order completion allowing the pipeline to complete executions out of order.

The Pentium Pro performed better when used in Windows NT systems because it is a 32-bit processor. Considering that Windows95/98 were 16-bit operating systems at the time, the Pentium Pro was not used for personal computers and was ideally used for servers. Because of the fact that the Pentium Pro supports multiple processor configurations and is architecturally sound it is still used in servers today.

Summary

There were many changes from the first chip released by Intel in 1971, the 4004, to the Pentium Pro, which is still used today. The architectures became much more complex but at the same time became much more efficient, with the first processor speed of only 740 Khz and 4KB of addressable memory up to the Pentium Pro’s 200 Mhz clock speed and 64GB of addressable memory. Some of the major technological advances that allowed these increases were virtual memory, paging, bus pipelining, and the different levels of cache. One of the biggest changes was from the 16-bit 286 to the 32-bit 386, which set the stage for the 32-bit architecture of the future Pentium processors.

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McGuire, Tim (2002). "Organization of Intel Microprocessors." URL: http://unx1.shsu.edu/~csc_tjm/spring2003/cs272/8086.html

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Group Work Breakdown

We divided the processors on what we thought was a fair proportion. We each agreed to cover the following processors and come up with our own power point slides for what we wanted to say. The other work such as organizing the paper and slides together, the introduction and the summary was divided evenly after we prepared the paper.

David Lenhardt – 4004, 8008, 8080, 8085, 8086, and 8088

Marcus O'Malley – 486, Paper and PowerPoint Organization

Christopher Payne – 286, 386, and Summary

Jonathon Taylor – Pentium, Pentium Pro, and Introduction

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