introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/cad/introduction.pdf · cs&rsoc...

Introduction

Sungho Kang

Yonsei University

2CS&RSOC YONSEI UNIVERSITY

Outline

VLSIDesign StylesOverview of Optimal Logic SynthesisModelGraph Algorithm and ComplexityAsymptotic ComplexityBrief Summary of MOS Device Behavior


VLSIVLSI

Manufacturing TechnologyMinimum length of MOS channelsThe number of interconnection layers

Design TechnologyCAD tools

Why VLSINew marketsOperation speedProtection investments in design


Design StyleDesign Style - Decomposition

Behavioral SynthesisResource allocation; Pipelining; Control flow parallelization; Communicating Sequential Processes; Partitioning

Sequential SynthesisRegister Movement and Retiming; State Minimization; State Assignment; Synthesis for Testable FSM’s; State Machine Verification

Logic SynthesisExtraction of combinational logic to HDL; Two-level minimization; Algebraic Decomposition; Multilevel Logic Minimization; Synthesis for Multi-fault Testability; Test Generation via Minimization; Technology mapping; Timing optimization

Technology MappingMapping to Library of Logic Gates; Timing Optimization

Physical Design SynthesisCell Placement; Routing; Fabrication; Engineering Changes


Design StyleLogic Design Styles

Full custom designEvery circuit part is especially optimized for the purpose it must serve in the design

Semi-custom designThe circuit is designed by assembling pre-designed and pre-characterized sub-circuitsManufacturing may use a pre-diffused substrate

Programmed designThe design is obtained by programming a standard partSome circuits may be programmed only once while others may be programmed an unlimited number of times


Design StyleDesign Methodology

CELL-BASED ARRAY-BASED

SEMICUSTOM

MACRO CELLS

Generatiors: Memory PLA Sparse logic Gate matrix

PREDIFFUSED

Gate arrays Sea of gates Compacted arrays

STANDARDCELLS

Hierarchical cells

PREWIRED

Anti-fuse based Memory-based


SOC DesignSOC Design Paradigm

Emergence of Very large transistor counts on a single chipMixed technologies on the same chip

Logic, Analog, Memory, ProcessorCreation of Intellectual Property (IP)Reusable core-based design

Cores replacing standard parts, such as DSP, DRAM, MCU, Flash, and FPGA


SOC DesignSOC Evolution

OriginalDesignBlock

OriginalDesignBlock

UserDefinedLogic(UDL)

SRAM

ROM

OriginalDesignBlock

uP(IP Core)

UserDefinedLogic(UDL)

DRAM

Analog

ROM

ATM(IP Core)

MPEG(IP Core)

ASIC

Block-Based SOC

Core-Based SOC


SOC DesignIP Core types

Hard Core(Technology dependent layout)Predictable area and performanceLack flexibility

Soft Core(RTL)leave much of the implementation to the designerFlexible and process-independent

Firm Core(Netlist)

Each type of core has different modeling and test requirements


Logic SynthesisDesign Tradeoffs

Factors to be optimized in chip design:AreaDelayPowerTestability

These competing objectives require Tradeoffs

Synthesis tools automate tradeoffAccording to the commands used by the designer, area or delay (or power, or testability) is reduced


Logic SynthesisArea vs Delay:The Bit-Serial Adder

A typical tradeoff is area versus delayWith just one full adder, this circuit can do 32-bit additionBut, it is 32x slower than a parallel adder (32 full adders, 1 bit output per clock cycle)


Logic SynthesisDesign Tradeoff Curve

Holding other factors constant, the Area vs Delay tradeoff curve is typically parabolicThe first design requirement is meet Constraints on Chip Area and Critical Path Delay (0 to 1)



The next priority is to optimize a feasible designDesign 2 is optimal, in the sense that area and delay cannot both be decreased from this pointTradeoff is now necessary, according to policy



A typical design policy is to optimize area subject to a delay constraint (2 to 3)Often a preferred policy is to optimize delay subject to an area constraint (2 to 4)

4


Logic SynthesisPrioritizing Testability

Sometimes other factors, such as testability or power, take priorityTypically this moves the area-delay tradeoff curve up and to the rightThus designs 1 and 2 are optimal


Logic SynthesisArea Optimization

Typically performed in a technology independent view of the circuitIn this view gates are regarded as logic functionsThese functions are converted to physical gates by Technology Mapping


Logic SynthesisTechnology Independent View

In this view the gates of the full adder circuit are just logic equations

a = xi yib = xi’ yi’e = a’ b’zi = eci-1‘ +e’ci-1c = xi yid = xi + y + i f = dci-1ci = c + f


Logic SynthesisOptimization and Technology Mapping

Common subfunctions sharedFunctions “Technology Mapped” to negative gates


Logic SynthesisTesting

Faults ModelsStuck-at faultsDelay faults

Test vectorsFault simulationAutomatic test pattern generation

DiagnosisTestable Design


Logic SynthesisDelay Optimization

First step is to identify the Critical PathSimplest delay model: “number of logic levels”


Logic SynthesisCritical Path Analyzers

Static Delay Models:Levels of LogicDelay function of size, load Worst, best case models

Dynamic Delay ModelsSimplified device modelsFull Spice analysis


Model GenerationModel

BehavioralRepresents the behavior of the systemBehavior can be specified as a mapping of logic values or of data words, etc.Functional model is a representation of its logic functionBehavioral model consists of a function model with a representation associated with timing relationsAdvantages from the separation between function and timing

Circuits with the same function but different timingFunction and timing can be dealt in design verification

Structural Collection of interconnected elementsPrimitive elementsBlock diagram : CPU, RAM, etcSchematic diagram : AND, OR etc


Model GenerationModel

ExternalModel viewed by the userGraphic or text-basedHDL (Hardware Description Language)RTL (Register Transfer Level)

InternalData structures and programs inside


Model GenerationTruth Tables

Simplest wayn variables requires 2n entry

X1 X2 Y0 0 00 1 01 0 01 1 1


Model GenerationCube

A cube of Z(x1,x2,x3) has the form (v1,v2,v3|vz) where vz=(v1,v2,v3) An implicant of g of Z can be represented by a cube constructed

Set vi=1(0) if xi(xi’) appears in g Set vi=x if neither xi nor xi’ appears in g Set vz=1

If the cube q can be obtained from the cube p by replacing one or more x values in p by 0 or 1 then p covers q Primitive cube

Cube representing a prime implicantPrimitive cubes provide a compact representation of a function


Model GenerationIntersection Operator

Inconsistency : ∅Consistency : Except ∅

Compatible Values whose intersection is consistentIntersection of 2 cubes is compatible iff all corresponding values are compatible

To determine ZForm the cube (v1,v2, … vn|x) Intersect this cube with the primitive cube of Z until a consistent intersection is obtainedThe value of z is obtained in the rightmost position

∩ 0 1 X0 0 ∅ 01 ∅ 1 1X 0 1 X


Model GenerationState Tables

Represents synchronous sequential circuitsRow corresponding to every internal stateColumn corresponding to every possible inputN(qi,Im), Z(qi, Im)

Entry in row qi and column Im represents the next state and the output produced if Im is applied when the machine is in state qi N : next state Z : output function

x0 1

1 2,1 3,0q 2 2,1 4,0

3 1.0 4,04 3,1 3,0


Model GenerationState Tables

Canonical Structure

F/F

combinationalcircuit C

F/F

x

CLOCK

z

y Y


Model GenerationFlow Tables

Represents a behavior of asynchronousState transition may involve a sequence of state changes caused by a single input change to Ij until a stable configuration is reached, denoted by N(qi, Ij)=qi

combinationalcircuit C

x z

y

x1 x2

00 01 11 101 1,0 5,1 2,0 1,02 1,0 2,0 2,0 5,13 3,1 2,0 4,0 3,04 3,1 5,1 4,0 4,05 3,1 5,1 4,0 5,1


Model GenerationIterative Array

C(0) pseudoF/F C(0) pseudo

F/Fpseudo

F/FC( i )Y(1) y(1) Y(2) y(2) y(i) Y(i+1) y(i+1)

Y(0)

x(0)

z(0)

x(1)

z(1)

x( i )

z( i )

time frame 0cell 0

time frame 1cell 1

time frame icell i


Model GenerationPrograms as Functional Models

CE = A & B & CF = ~DZ = E \ F

AssemblyLDA A /* load accumulator with value of A*/AND B /* compute A.B */AND C /* compute A.B.C */STA E /* store partial result */LDA D /* load accumulator with value of D */INV /* compute DOR E /* compute A.B.C + D */STA Z /* store result */

ABC

D F

E

Z


Model GenerationRTL Constructs

8-bit register IR register IR[0→ 7]

256-word memory ABC with 16-bit/word memory ABC[0 → 255; 0 → 15]

When control is 1, C=A+Bif X then C=A+B

Decodertest (IR[0 → 3])case 0 : operation0case 1 : operation1

case 15 : operation15testend


Model GenerationTiming Models in RTL

Procedural LanguagesSimilar to conventional programming language where statements are sequentially executed such that the result of a statement isimmediately availableC = B

A = BC = A

Describes a system at the instruction set level of abstractionNonprocedural Languages

Statements are conceptually executed in parallelExchange A and B

A = BB = A

ExamplesC=A+B, delay = 100 delay C 100


Model GenerationStructural Models

FanoutFanout-freeReconvergent fanputInversion Parity


Logic SynthesisGraph Models and FSM

GraphEdgeVertexUndirected graphDigraph (directed graph)

All edges are directedMixed graph

Directed and undirectedDAG (directed acyclic graph)

If digraph has no cycles


Logic Synthesis

Graph: ordered set of two sets G= (V,E)V : a set of vertices or nodesE : a set of edges or arcs->4 : the successors (fanouts) of node 4 4->=1,3->4 : the predecessors (fanins) of node 4 ->4=1,2

Graph Terminology


Logic SynthesisGraph Models

Transitive closureThe extended edge relation E*(u,v) derived from a given edge relation E(u,v) is called transitive closure of E

fanoutfaninSource

v has no predecessorsSink

v has no successors


Graph AlgorithmsProducts of Sets of Sets

Intersecting 2 sets of setsTakes as inputs the sets G and H and computes the product P=GXH of sets G and H

Procedure SET_CARTESIAN_PRODUCT(G,H) Ops Times/callBest Worst

m =G; n=H; c1 1 1P = NULL c2 1 1for (i = 1, 2, …, m) c3m 1 1

for (j = 1, 2, …, n) c4n m mP = P ∪ (Gi ∩ Hj) c5 mn mnq

return(P) c6 1 1


Graph AlgorithmsComputing Critical Path Length

This problem is modeled as that of finding the longest path in a DAG (Directed Acyclic Graph)

The Key point is that every edge is traversed exactly once

T(m,n,q) = O(m)


Graph AlgorithmsLongest Paths


Graph AlgorithmsBacktracing

The slack of an edge(a,v) is the slack of v plus the difference between the length of the longest path to v and the longest path to v through (a,v)In formula, slacka,v = slackv + (λv - (λ a + La,v ))Here λv is the length of the longest path to v, and (λ a + La,v ) is the length of the longest path to v that passes through the edge (a,v)The slack of a node u is defined as the minimum of its fanout edge slacks, so

slacka = min slackv

An edge (a,v) is critical if it connects two nodes a and v with slack value 0


Asymptotic ComplexityAsymptotic Complexity

A function F(n) is in the set O(g(n)) if and only if there exist positive constants co and no such that

F(n) ≤cog(n) for all n ≥ no

This means that F(n) is asymptotically bounded from above by a linear function of g(n)

A function F(n) is in the set Ω(g(n)) if and only if there exist positive constants cΩ and nΩ such that

F(n) ≥ cΩ g(n) for all n ≥ nΩ

This means that F(n) is asymptotically bounded from below by a linear function of g(n)


ConlcusionConclusion

Design time spent in each design phase

Verification : 39% RTL design and synthesis : 17%IC layout : 13%System design and integration : 11%Test vector creation : 11%Evaluation and Procurement : 6%Other : 3%

introduction - soc.yonsei.ac.krsoc.yonsei.ac.kr/class/material/cad/introduction.pdf · cs&rsoc...

Documents