introduction to cmos vlsi design sram/dram
DESCRIPTION
Introduction to CMOS VLSI Design SRAM/DRAM. Textbook: Chapter 11. Outline. Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports DRAM Serial Access Memories. Memory Arrays. Array Architecture. 2 n words of 2 m bits each - PowerPoint PPT PresentationTRANSCRIPT
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Introduction toCMOS VLSI
Design
SRAM/DRAM
Textbook: Chapter 11
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2CMOS VLSI Design
Outline Memory Arrays SRAM Architecture
– SRAM Cell– Decoders– Column Circuitry– Multiple Ports
DRAM Serial Access Memories
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3CMOS VLSI Design
Memory ArraysMemory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory(CAM)
Read/Write Memory(RAM)
(Volatile)
Read Only Memory(ROM)
(Nonvolatile)
Static RAM(SRAM)
Dynamic RAM(DRAM)
Shift Registers Queues
First InFirst Out(FIFO)
Last InFirst Out(LIFO)
Serial InParallel Out
(SIPO)
Parallel InSerial Out
(PISO)
Mask ROM ProgrammableROM
(PROM)
ErasableProgrammable
ROM(EPROM)
ElectricallyErasable
ProgrammableROM
(EEPROM)
Flash ROM
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4CMOS VLSI Design
Array Architecture 2n words of 2m bits each If n >> m, fold by 2k into fewer rows of more columns
Good regularity – easy to design Very high density if good cells are used
row decoder
columndecoder
n
n-kk
2m bits
columncircuitry
bitline conditioning
memory cells:2n-k rows x2m+k columns
bitlines
wordlines 8-word by 4-bit memory folded into a 4-row by 8-column array with n=3, m=2, k=1
simplest design: one row per word and one column per bit in each word very tall skinny memory hard to fit in the chip floorplan
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5CMOS VLSI Design
12T SRAM Cell Basic building block: SRAM Cell
– Holds one bit of information, like a latch– Must be read and written
12-transistor (12T) SRAM cell– Use a simple latch connected to bitline– 46 x 75 unit cell
bit
write
write_b
read
read_b
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6CMOS VLSI Design
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7CMOS VLSI Design
6T SRAM Cell Cell size accounts for most of array size
– Reduce cell size at expense of complexity 6T SRAM Cell
– Used in most commercial chips– Data stored in cross-coupled inverters
Read:– Precharge bit, bit_b– Raise wordline
Write:– Drive data onto bit, bit_b– Raise wordline
bit bit_b
word
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8CMOS VLSI Design
SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will
– be pulled down by the cell Ex: A = 0, A_b = 1
– bit discharges, bit_b stays high– But A bumps up slightly
Read stability– A must not flip
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600
time (ps)
word bit
A
A_b bit_b
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9CMOS VLSI Design
SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will
– be pulled down by the cell Ex: A = 0, A_b = 1
– bit discharges, bit_b stays high– But A bumps up slightly
Read stability– A must not flip– N1 >> N2
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600
time (ps)
word bit
A
A_b bit_b
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10CMOS VLSI Design
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
SRAM Read, 0 is stored in the cell
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11CMOS VLSI Design
SRAM Write Drive one bitline high,
– the other low Then turn on wordline Bitlines overpower cell
– with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
– Force A_b low, • then A rises high
Writability– Must overpower
• feedback invertertime (ps)
word
A
A_b
bit_b
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600 700
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
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12CMOS VLSI Design
SRAM Write Drive one bitline high,
– the other low Then turn on wordline Bitlines overpower cell
– with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0
– Force A_b low, then A rises high Writability
– Must overpower feedback inverter– P2 << N4 to force A_b low,– N1 turns off, P1 turns on, – raise A high as desired
time (ps)
word
A
A_b
bit_b
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600 700
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
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13CMOS VLSI Design
SRAM Sizing High bitlines must not overpower inverters during
reads But low bitlines must write new value into cell
bit bit_b
med
A
weak
strong
med
A_b
word
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14CMOS VLSI Design
SRAM Column Example
2
MoreCells
SRAM Cell
word_q1bit_v1f
bit_b_v1f
data_s1
write_q1
Bitline Conditioningread write
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15CMOS VLSI Design
Decoders n:2n decoder consists of 2n n-input AND gates
– One needed for each row of memory– Build AND from NAND or NOR gate
word0
word1
word2
word3
A0A1
A1
word
A0 1 1
1/2
2
4
8
16
word
A0
A1
1
1
11
4
8
word0
word1
word2
word3
A0A1
choose minimum size to reduce load on the address lines
staticPseudo-nMOS
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16CMOS VLSI Design
Decoder Layout Decoders must be pitch-matched to SRAM cell
– Requires very skinny gates
GND
VDD
word
buffer inverterNAND gate
A0A0A1A2A3 A2A3 A1
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17CMOS VLSI Design
Decoder Layout
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18CMOS VLSI Design
Large Decoders For n > 4, NAND gates become slow
– Break large gates into multiple smaller gates
word0
word1
word2
word3
word15
A0A1A2A3
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19CMOS VLSI Design
Predecoding Many of these gates are redundant
– Factor out common
gates into predecoder– Saves area– Same path effort
A0
A1
A2
A3
word1
word2
word3
word15
word0
1 of 4 hotpredecoded lines
predecoders
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20CMOS VLSI Design
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21CMOS VLSI Design
Column Circuitry Some circuitry is required for each column
– Bitline conditioning– Sense amplifiers– Column multiplexing
Each column must have write drivers and read sensing circuits
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22CMOS VLSI Design
Bitline Conditioning Precharge bitlines high before reads
Equalize bitlines to minimize voltage difference when using sense amplifiers
bit bit_b
bit bit_b
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23CMOS VLSI Design
Sense Amplifiers Bitlines have many cells attached
– Ex: 32-kbit SRAM has 256 rows x 128 cols– 128 cells on each bitline
tpd (C/I) V
– Even with shared diffusion contacts, 64C of diffusion capacitance (big C)
– Discharged slowly through small transistors (small I)
Sense amplifiers are triggered on small voltage swing (reduce V)
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24CMOS VLSI Design
Differential Pair Amp Differential pair requires no clock But always dissipates static power
bit bit_bsense_b sense
N1 N2
N3
P1 P2
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25CMOS VLSI Design
Clocked Sense Amp Clocked sense amp saves power Requires sense_clk after enough bitline swing Isolation transistors cut off large bitline capacitance
bit_bbit
sense sense_b
sense_clk isolationtransistors
regenerativefeedback
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26CMOS VLSI Design
Twisted Bitlines Sense amplifiers also amplify noise
– Coupling noise is severe in modern processes– Try to couple equally onto bit and bit_b– Done by twisting bitlines
b0 b0_b b1 b1_b b2 b2_b b3 b3_b
equalize voltage to reduce noise.
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27CMOS VLSI Design
Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2k word x 16 folded into 256 rows x 128 columns
– Must select 16 output bits from the 128 columns– Requires 16 8:1 column multiplexers
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28CMOS VLSI Design
Tree Decoder Mux Column mux can use pass transistors
– Use nMOS only, precharge outputs One design is to use k series transistors for 2k:1 mux
– No external decoder logic neededB0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7
A0
A0
A1
A1
A2
A2
Y Yto sense amps and write circuits
bitlines propagate through 3 transistors
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29CMOS VLSI Design
Single Pass-Gate Mux Or eliminate series transistors with separate decoder
A0A1
B0 B1 B2 B3
Y
bitlines propagate through 1 transistor
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30CMOS VLSI Design
Ex: 2-way Muxed SRAM
MoreCells
word_q1
write0_q1
2
MoreCells
A0
A0
2
data_v1
write1_q1 two bits from two cells and selected by A0
2-to-1 mux
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31CMOS VLSI Design
Multiple Ports We have considered single-ported SRAM
– One read or one write on each cycle Multiported SRAM are needed for register files Examples:
– Multicycle MIPS must read two sources or write a result on some cycles
– Pipelined MIPS must read two sources and write a third result each cycle
– Superscalar MIPS must read and write many sources and results each cycle
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32CMOS VLSI Design
Dual-Ported SRAM Simple dual-ported SRAM
– Two independent single-ended reads– Or one differential write
Do two reads and one write by time multiplexing– Read during ph1, write during ph2
bit bit_b
wordBwordA
wordA reads bit_b (complementary)
wordB reads bit (true)
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33CMOS VLSI Design
Multi-Ported SRAM Adding more access transistors hurts read stability Multiported SRAM isolates reads from state node Single-ended design minimizes number of bitlines
bA
wordBwordA
wordDwordC
wordFwordE
wordG
bB bC
writecircuits
readcircuits
bD bE bF bG
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34CMOS VLSI Design
bA
wordBwordA
wordDwordC
wordFwordE
wordG
bB bC
writecircuits
readcircuits
bD bE bF bG
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35CMOS VLSI Design
Logical effort of RAMs
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36CMOS VLSI Design
DRAM: Dynamic RAM
Store their contents as charge on a capacitor rather than in a feedback loop.
1T dynamic RAM cell has a transistor and a capacitor
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37CMOS VLSI Design
DRAM Read
1. bitline precharged to VDD/2
2. wordline rises, cap. shares it charge with bitline, causing a voltage V
3. read disturbs the cell content at x, so the cell must be rewritten after each read
bitcell
cellDD
CC
CVV
2
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38CMOS VLSI Design
DRAM writeOn a write, the bitline is driven high or low and the voltage is forced to the capacitor
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39CMOS VLSI Design
DRAM Array
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40CMOS VLSI Design
DRAM
With large size, the bitline cap is an order of magnitude higher than in the cell, causing very small voltage swing.
A sense amplifier is used. Three different bitline architectures, open, folded,
and twisted, offer different compromises between noises and area.
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41CMOS VLSI Design
Serial Access Memories Serial access memories do not use an address
– Shift Registers– Tapped Delay Lines– Serial In Parallel Out (SIPO)– Parallel In Serial Out (PISO)– Queues (FIFO, LIFO)
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42CMOS VLSI Design
Shift Register Shift registers store and delay data Simple design: cascade of registers
– Watch your hold times!
clk
Din Dout8
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43CMOS VLSI Design
Denser Shift Registers Flip-flops aren’t very area-efficient For large shift registers, keep data in SRAM instead Move read/write pointers to RAM rather than data
– Initialize read address to first entry, write to last– Increment address on each cycle
Din
Dout
clk
counter counter
reset
00...00
11...11
readaddr
writeaddr
dual-portedSRAM
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44CMOS VLSI Design
Tapped Delay Line A tapped delay line is a shift register with a
programmable number of stages Set number of stages with delay controls to mux
– Ex: 0 – 63 stages of delay
SR
32
clk
Din
delay5
SR
16
delay4
SR
8
delay3
SR
4
delay2
SR
2
delay1
SR
1
delay0
Dout
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45CMOS VLSI Design
Serial In Parallel Out 1-bit shift register reads in serial data
– After N steps, presents N-bit parallel output
clk
P0 P1 P2 P3
Sin
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46CMOS VLSI Design
Parallel In Serial Out Load all N bits in parallel when shift = 0
– Then shift one bit out per cycle
clkshift/load
P0 P1 P2 P3
Sout
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47CMOS VLSI Design
Queues Queues allow data to be read and written at different
rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers)
Queue
WriteClk
WriteData
FULL
ReadClk
ReadData
EMPTY
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48CMOS VLSI Design
FIFO, LIFO Queues First In First Out (FIFO) organized as a circular
buffer– Initialize read and write pointers to first element– Queue is EMPTY– On write, increment write pointer– If write almost catches read, Queue is FULL– On read, increment read pointer
Last In First Out (LIFO)– Also called a stack– Use a single stack pointer for read and write