introduction to copper / low-k interconnects
TRANSCRIPT
![Page 1: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/1.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 1
Introduction to Copper / Low-K Interconnects &Electromigration Fundamentals
Alvin L.S. Loke1 & Tin Tin Wee2
1 Agilent Technologies, Fort Collins, CO2 Chartered Semiconductor Manufacturing, Singapore
IEEE Solid-State Circuits SocietySeptember 12, 2003
![Page 2: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/2.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 2
Outline� Conventional Interconnect Technology
� Copper / Low-K Interconnects� Fundamental Motivations� Technology Challenges� Integration� Manufacturing Issues� Summary
� Electromigration Fundamentals
� Summary / Future Trends
![Page 3: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/3.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 3
Evolution of Interconnect Technologies
0.25µm Technology(Motorola, 1996)
Al (0.5%Cu)Al (0.5%Cu)
oxide (SiO2 )oxide (SiO2 )
M5M5
M4M4
M3M3
M22
M1M1
Where is the transistor?
1st Fabricated IC(Texas Instruments, 1958)
wiring
90nm Technology(TSMC, 2002)
M5M5
M4M4M3M3M2M2
M1M1
M9M9
M8M8M7M7
M6M6CuCu
LowLow--KK
Scaling & interconnect density / number of metal layers
![Page 4: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/4.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 4
Aluminum Alloy Technology
1. Oxide deposition 2. Via etch 3. Barrier & W fill 4. W & barrier CMP
5. Metal stack deposition
6. Metal stack etch 7. Oxide gapfill deposition
8. Oxide CMP(chemical-mechanicalpolishing)
Via Fabrication
Metal Fabrication
![Page 5: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/5.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 5
Interconnect Scaling – Performance Limiter
Limitations with Al/SiO2 Technology• wire (RC) delay• reliability
• electromigration• stress migration
• power dissipation• crosstalk noise• cost
Materials Solutions• copper
→ R ↓, reliability ↑• low-K dielectric
→ C ↓, power dissipation ↓, crosstalk ↓
Bohr (1995)
![Page 6: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/6.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 6
Copper Processing Challenges
Issues• copper is difficult to dry-etch• copper diffuses quickly in Si and SiO2
→ junction & dielectric leakage ↑, carrier lifetime ↓
Solutions• pattern using Damascene (inlaid) scheme• encapsulate copper wires/vias with diffusion barriers
![Page 7: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/7.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 7
First Declarations of Manufacturable Copper Process Technology
• Announcements accelerated industry-wide commitment to switch to copper interconnects
• First incorporate copper with oxide, then introduce low-K dielectrics
(Sept. 1997) (Oct. 1997)
![Page 8: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/8.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 8
Dual Damascene Technology
1. Dielectric deposition
2. Trench/via patterning• buried-etchstop• trench-first• full-via-first
3. Metal barrier deposition, Cu seed deposition & Cu electroplate fill
4. Cu & barrier CMP(chemical-mechanicalpolishing)
5. Nitride barrier passivation
copper
copper
barriertrench(metal)
via
![Page 9: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/9.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 9
1)Dielectric stack deposition 2)Via photo3)buried etchstop etch
Buried-Etchstop Approach
trench
via
• Via resist strip• Trench-level oxide deposition
• Trench photo
• One-step trench/via etch (stop on nitride)
• Trench resist strip• Nitride etch
buried etchstop
nitride/oxynitridevia-level oxide
nitride
copper
photoresist
![Page 10: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/10.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 10
1)Dielectric stack deposition 2)Trench photo
trench
via
• Trench etch• Trench resist strip
• Via photo
• Via etch (stop on nitride)• Via resist strip• Nitride etch
trench
trench-level oxidenitride/oxynitride
via-level oxide
nitride
copper
photoresistTrench-First Approach
![Page 11: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/11.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 11
1)Dielectric stack deposition 2)Via photo
Full-Via-First Approach
via
trench
via
• Via etch (stop on etchstop layer)• Via resist strip
• BARC deposition• Trench photo• BARC etch
• Trench etch• Trench resist/BARC strip• Nitride etch
trench-level oxidenitride/oxynitride
via-level oxide
nitride
copper
photoresist
![Page 12: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/12.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 12
Lithography Issues• wafer planarity for maximum depth of focus
• resist thickness variation → poor CD control• limits extendibility of via photo in trench-first
approach
• reflective notching for CD control• need anti-reflective films in dielectric stack or
spin-on organic BARC• less effective if underlying topography is present
• overlay error between trench & via masks• big issue in buried-etchstop & trench-first
• misalignment decreases size of via landing as well as intervia and/or intrametal spacing
• least severe in full-via-first • only intrametal spacing misaffected
• may ultimately limit scalability of dual damascene
![Page 13: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/13.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 13
Dielectric Etch Issues• trench etch selectivity to stop layer
• need to control microloading & trench bottom profile• big issue in buried-etchstop
• resist stripping• need to remove before exposing copper since resist
is difficult to strip without oxidizing copper
• BARC stripping• difficult to remove fence residues in full-via-first
• excessive faceting from unmasked nitride etch• some desired for easier barrier & copper seed fill• over-faceting reduces intrametal spacing → leakage
• copper resputtering onto via sidewall• must avoid copper trapped outside barrier which
could diffuse into dielectric
• unlanded via fangs from unselective nitride etch• poor barrier/seed coverage → poor reliability
faceting
etchstop
fang
resputtering
![Page 14: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/14.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 14
Step 1: Barrier Deposition (Ta, TaN, TiN)• prevent diffusion of copper from trench/via into Si or SiO2• adhesion layer for copper to dielectric• must be thin to preserve conductivity advantage of copper• CVD or directional PVD (e.g., ionized metal plasma (IMP))
Step 2: Copper Seed Layer Deposition• conductive layer for copper e-plate fill → better within wafer uniformity• control of plated copper film grain size & texture → better reliability• CVD or directional PVD (e.g., ionized metal plasma (IMP))
Important to have conformal barrier & seed layer to ensure good fill.
Barrier & Copper Seed Deposition
ideal step coverage typical step coverage
cusping
![Page 15: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/15.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 15
Barrier & Copper Seed Deposition Issues
After Cu seed
After Cu electroplate
poor coverage
rough morphology
excess oxidation
overhang asymmetry
Courtesy of Solid State Technology
![Page 16: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/16.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 16
Basic Principle • immerse wafer into solution of copper ions• cathode clamped to wafer edge• apply potential between cathode & anode to
plate copper on waferCu2+ + 2e- →→→→ Cu0
Copper Plating for IC Application• most popular method for copper fill• cheap• optimized tool, plating bath & current for
good gapfill & deposition uniformitye.g., careful diffuser design to compensate
for intrinsic edge-fast deposition• post-plating anneal required to accelerate
room-temperature self-annealing of plated copper → better grain size control for CMP
Copper Electroplating Fundamentals
wafer(facing down)
Cu anode
continuous chemical circulation
diffuser
Iplating
cathode
Copper electroplating for IC’s pioneered by IBM
![Page 17: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/17.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 17
Want superfilling (bottom-up deposition)
1. Pulsed Plating Current Waveform• simultaneous deposition-etch • improve diffusion of copper ions into via
Techniques for Good Plating Gapfill
time
etch
deposition subconformal void
conformal seam
superconformal defect-free
2. Organic Additives in Plating Bath brightener• enhance deposition rate in via & trench• small organic molecules
leveler• retard deposition rate at open field corners• large organic macromolecules
![Page 18: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/18.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 18
Basic Principles• planarize wafer surface• remove excess copper & metal barrier from wafer field to form inlaid copper• removal rate depends on pad pressure, pad velocity, selectivity of slurry
chemistry & mechanical abrasion
Copper CMP Fundamentals
wafer carrierin situ pad conditioner
(critical)
polishing table
polishingpad
wafer(facing down)
slurry
opticalendpointdetection
CMP technology pioneered by IBM
Basic Process1. bulk copper removal
• stop on barrier 2. barrier removal3. oxide buff
• reduce defects• apply corrosion inhibitor
4. post-CMP scrub• remove slurry residues• clean surface• dark ambient to suppress
galvanic copper deposition
![Page 19: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/19.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 19
Good planarity is very critical for multilevel integration!!!• minimize metal residues at higher metal levels• essential to optimize process conditions, polishing pad & slurry chemistry
while maintaining practical removal rates
Copper CMP Issues
post-CMP topography metal residue!!!
copper dishing in wide metal lines oxide erosion in dense metal lines
![Page 20: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/20.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 20
0 2 4 6 8 10Line Width, W (µm)
Line
Spa
ce, S
(µm
)
0
2
4
6
8
10
CMP Layout/Pattern Density Effects
1.00.8 1.20.9 1.1
Normalized Sheet Resistance
![Page 21: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/21.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 21
Interconnect Dummification• Add dummy patterns to open spaces to minimize layout density variations
→ Minimize RS variation→ Minimize surface topography (depth of focus, metal residues)→ Added design complexity to check layout density & insert dummy patterns
• Also critical to step dummy dies along wafer circumference
![Page 22: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/22.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 22
Dielectric CMP• Original motivation for CMP development at IBM• Dummification also required for active & poly layers
• Planarity important since metal layers build on top of polished dielectrics
• STI (shallow trench isolation)
• ILD0 / contact-level dielectric
oxide fill & CMP
need active dummy
oxide fill & CMP
need poly dummy
ILD0
STI
STISi
Si
![Page 23: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/23.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 23
Electrical Monitoring of CMP PerformanceCompare resistances of lines with various adjacent patterns.
• no adjacent lines, i.e., isolated• worst-case low pattern density• lots of Cu in field area to remove
• minimum-pitch adjacent lines• prone to dielectric erosion
• wide adjacent lines, e.g., bus• wide lines very prone to dishing• erosion of dielectric supporting
tested line
Motorola (1998)
![Page 24: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/24.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 24
Post-CMP Inline Electrical TestingMotivations• measuring metal leakage after each copper CMP step can identify wafers
with copper or barrier residues that need CMP rework• monitoring of dishing & erosion with various test structures
Limitations• contact on copper bondpads not reliable• increased contact overdrive of probetips
creates copper debris• essential to minimize overdrive & maintain
probecard with clean / planar tips• test structure is very dependent on
surrounding pattern density• throughput
Recent Development• sensitive optical detection of metal residues (contactless)
![Page 25: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/25.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 25
Potential Fab Contamination Concern• high tool costs require some tool sharing between copper & non-copper
processes, e.g., lithography, metrology
• wafer handling by copper tools adds Cu to wafer backside
• shared tools can cross-contaminate frontend tools through common wafer handling of copper & non-copper wafers
SMIF Pod & Cassette Change
Red SMIF Pod & Cassette(Copper BEOL)
DedicatedCopper Tool
Shared Tool
Black SMIF Pod & Cassette(FEOL)
Shared Tool
DedicatedNon-Copper
Tool
Backside Clean
SMIF pod
![Page 26: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/26.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 26
Moving to Low-K Dielectrics• Damascene Cu integration with lower K dielectrics for reduced capacitance
• Migration to FSG only an incremental improvement
• Plenty of new integration & reliability issues beyond FSG due to fundamental differences in materials properties
• Plenty of early demonstrations in 1990’s, but not manufacturable until recently
![Page 27: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/27.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 27
What Makes K Low?• K = dielectric constant = relative permittivity = ε / εo
• K measures an insulator’s polarizability when exposed to an electric field
• Low K � weak polarization (difficult to induce dipoles)
+ + + + + + + + + + + +
–
+
–
+
–
+
+ + + + + + + + + + + +
–+ –+ –+High K Low K
– – – – – – – – – – – – – – – – – – – – – – – –
• Materials with low K have:• Weakly polar chemical constituents• High porosity (KAIR = 1)• Minimal / no moisture content (KWATER = 80)• High degree of structural symmetry for dipole cancellation
![Page 28: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/28.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 28
Low-K Materials Choices• FSG / F-TEOS (K=3.2-3.9) – first generation low-K, just incremental
• Fluorine reduces polarity of bridging oxygens in glass – undoped TEOS (K=4.0-4.2)• Moisture uptake if % F is too high, K > 3.5 for stable film• Weaker adhesion to metals & dielectrics, potential corrosion
• Nonporous organic polymers / open-structure glasses – spin-on vs. CVD
• Porous materials (K<2.5)• Porous MSQ (methyl silsesquioxane) most extensively developed so far• e.g., AMAT Black Diamond, Novellus Coral® (contains Si, O, C, H)
• Conservative industry favoring CVD of porous silicate-based material although some companies invested heavily in spin-on pure organics
Dow SiLK™
MSQ
HCOSi
![Page 29: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/29.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 29
Low-K Materials Limitations
• Introduces significant integration complexity
• Mechanically weak (low Young’s modulus)• Softness � CMP compatibility• Thermal stability � limited process options• Thermal conductivity � reliability• Adhesion (intrinsic to low K)� delamination, interface leakage• Porosity � moisture uptake• Wet chemical clean compatibility � surface treatments• Dry etch / ashing compatibility � hard masks, plasma damage
![Page 30: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/30.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 30
Why is Low-K Integration So Tough?• Not just a simple matter of replacing oxide/FSG with low-K dielectric
• Lots of integration issues• Lithography (resist poisoning, multilevel planarity)• Damage-free etch & resist ashing (dielectric hard
masks & etch stops)• Void-free & low-stress Cu plating• Scaling higher-ρ barrier & higher-K dielectric liner
thicknesses (atomic layer deposition)• CMP compatibility (low down-force with minimal
dishing, polish stops)• Impact on Transistors (high-K gate integration,
NBTI)• Packaging (mechanical integrity, delamination,
thermal budget)• …
![Page 31: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/31.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 31
Reliability Even Tougher…
• Electromigration along weak interfaces
• need surface/interface treatments
• Via stress migration voiding• HUGE PROBLEM• backend/package heat cycles• barrier delamination, metal stresses
• TDDB • time-dependent dielectric breakdown• leakage from dielectric wearout
• Interface control is key!!!
![Page 32: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/32.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 32
What is Electromigration?
• Major wearout failure mode for IC interconnects � reliability issue
• Mass transport in electrical conductor due to momentum exchange between large flux of conducting electrons and diffusing metal atoms
• Fundamentally a materials problem
• Phenomenon discovered by Gerardin (1863) in liquid metal alloys
Metal void � open circuit Metal hillock � short circuitNix et al. (1992)
![Page 33: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/33.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 33
Why Does Electromigration Happen?• At high current densities, “electron wind” imparts momentum onto
metal atoms during scattering events or collisions
• Mass transport or self-diffusion of metal atoms → atomic densities (ρ) deviate from equilibrium (ρ0)→ regions of tensile & compressive stress in metal→ atomic bonds experience tensile & compressive strain
• Void forms when tensile stress in metal is so high that it is thermodynamically more favorable to form void instead of sustaining build-up of tension in metal
• Hillock forms when compressive stress in metal is so high that surrounding dielectric/barrier encapsulation can no longer resist further build-up of compression in metal
• Understanding mechanical stresses is key to designing EM-resistant interconnects
![Page 34: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/34.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 34
Some Mass Transport Physics
F = ∇µ = FEM + FTM + Fσ + FS
• FEM = migration due to electron wind (electromigration)
• FTM = migration due to temperature gradient (Soret effect)
• Fσ = migration due to stress gradient (creep or stress migration)
• FS = migration due to entropy (atomic concentration)
• Driving Forces for mass transport
![Page 35: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/35.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 35
Diffusion Paths• Metal self-diffusion is a thermally activated process
D = D0 exp (-EA / kBT)
• Generally, D ↓ as EA ↑
• EA depends on diffusion path
• Lattice / bulk diffusion ~ 20 kBTMELT
• Grain boundary diffusion ~ 10 kBTMELT
• Surface / interface diffusion ~ 7 kBTMELT
• Electromigration slowest when bulk diffusion dominates• High TMELT metals � copper, refractory metals (W, Ta)• Large grains (bamboo structure) � cut off grain boundaries paths• Passivate surfaces/interfaces � cut off rapid diffusion paths
DL
DGB
DS
![Page 36: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/36.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 36
Black’s Equation
t50 = (A / j n) exp (EA / kBT)
• t50 = median TTF (time-to-failure)
• A = constant (depends on microstructure)
• j = current density
• n = current density exponential (n =1-2 typical) � growth / nucleation
• EA = activation energy � diffusion path
• kB = Boltzmann’s constant
• T = absolute temperature
![Page 37: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/37.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 37
Reliability Engineering• Al / oxide
• 0.5% Cu doping in Al typical to plug up grain boundaries• Incubation period in EM failures
• Large grains with (111) orientation• Minimize flux divergence / scattering• Special seed layer requirements
• Encapsulation by compressive dielectric
• Damascene Cu / oxide & Cu / low-K• Stress reduction in plated films• Interface sealing with surface treatments• Conformal Barrier coverage• Large grains with (111) orientation
• Minimize flux divergence / scattering• Special seed layer requirements
• Mechanical rigidity
![Page 38: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/38.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 38
Electromigration Testing
• Accelerated testing of many lines at higher temperatures & current densities
• Record line time-to-failure (TTF), e.g., defined as time for line resistance to increase by some % due to voiding
• Extrapolate some conservative TTF (e.g., 0.1 percentile) to nominal IC operating conditions using Black’s equation
• Very statistical in nature � want high TTF AND small σTTF
• Compare different types of test structures to exercise different weak spots in interconnect structure
• Via EM very significant (current crowding, weak interfaces)
![Page 39: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/39.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 39
EM Test Structure Examples
![Page 40: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/40.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 40
How Do These New Interconnect Technologies Impact Designers?
• More to worry about… like there isn’t enough in design alone
• Design must account for process limitations• Greater process variations (in addition to voltage & temperature)• CMP constraints• Yield considerations• Reliability considerations (electromigration)
• Design rule complexities• Layout density checks / dummification• More conservative rules, e.g, redundant vias• Metal slot / maximum line width rules• Mechanical integrity, e.g., sea of vias to support large bondpads
![Page 41: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/41.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 41
Summary / Future Trends• Limitations with aluminum interconnect scaling has forced industry-wide
migration to on-chip copper metallization.
• Dual-damascene copper interconnect processes with FSG now in mass production.
• Leading IC manufacturers on track to successfully integrate true (non-FSG) low-K dielectrics, some migrating to single damascene copper.
• K scaling has not kept pace with forecasted IC roadmaps due to materials integration challenges.
• Pressure to recover performance from higher performance transistors (e.g., with strained Si, high-K dielectrics, SOI)
• Interconnect reliability much more challenging but performance bar is much higher than before.
• Industry trend is to integrate more porous low-K with copper in 300mm.
![Page 42: Introduction to Copper / Low-K Interconnects](https://reader031.vdocument.in/reader031/viewer/2022020912/6203490124f6b61e9c66396d/html5/thumbnails/42.jpg)
Alvin LokeAgilent Technologies Introduction to Copper/Low-K Interconnects & Electromigration Fundamentals Slide 42
Acknowledgments
• Chintamani Palsule (Agilent)• Module Engineers & Managers (Chartered)• Jeff Wetzel (TEL)• Simon Wong (Stanford)• Jim Pfiester (Agilent)• Jim Lloyd (IBM)• Joe McPherson (Texas Instruments)• Nobuyoshi Kobayashi (SELETE)