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Introduction to Verilog - A by Eng. Radwa Ahmed Abbas Microelectronics Course ELCT 703 Electronics Dept., Faculty of IET The German University in Cairo

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Page 1: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Introduction to Verilog-Aby

Eng. Radwa Ahmed Abbas

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

Page 2: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Contents • Verilog-A History

• Digital vs. DT Analog vs. CT Analog

• Verilog-A Examples

• Ideal Op-Amp

• Non ideal Op-Amp

• Verilog-A in Cadence

• References

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 3: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A History • Verilog Hardware Description Language (VHDL) , is another method to document

hardware instead of schematic .

• It started life as a proprietary language but was donated by Cadence Design Systems tothe design community to serve as the basis of an open standard.

• That standard was formalized in 1995 by the IEEE

• Verilog-A was released in 1996 proposing extensions to VHDL

• Support analog and mixed signal simulation.

• Verilog-A was not intended to work directly with VHDL.

• Rather it was a language with Similar syntax and related semantics that was intended tomodel analog systems and be compatible with SPICE class circuit simulation engines.

• The first implementation of Verilog A soon followed from Cadence on their Spectrecircuit simulator.

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 4: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A History • Verilog AMS was first released in 2000 , latest version in 2014.

• Verilog AMS combines both VHDL and Verilog-A, and adds additional mixed signalconstructs, providing an HDL suitable for analog, digital, and mixed signal systems.

• Cadence released an implementation of Verilog AMS in AMS Designer that combinestheir Verilog and Spectre simulators.

• Currently, almost all circuit simulators support Verilog-A, and each of the major EDAvendors offer mixed signal simulators that support Verilog AMS.

• System Verilog added many more verification capabilities, first released in 2005.

• Remember: Verilog AMS is used for modeling/simulation/verification, NOT for synthesis.

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 5: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Digital vs. DT Analog vs. CT Analog • Verilog-A is designed to allow modeling of systems that process continuous time (CT)

signals.

• While it can also handle systems that process other types of signals, it is not efficient for doing so .

• Verilog AMS efficiently handle all types of signals Ideal for mixed signal design.

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 6: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : resistor model

• Words bolded are key words in Verilog-A .

• Structure of code :

• `include : defines different libraries to be used , for example:

disciplines.vams has physical nature of signals types ( electrical , mechanical)

• Electrical to define voltage and current . Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 7: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

• module name ( n, m, r ): contains the description of a black box and no. of signals coming out or in and it’s characteristics .

• ports direction : input , output , inout

• input can sense the signal that they are connected to , but cannot affect them

• output can affect signal but cannot sense it

• inout ports can affect and sense the signals

Verilog-A Examples : resistor model

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 8: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

• analog introduces an analog process: continuous time behavior., if more than one line command word begin is added after analog and an additional end must be added before end module to define start and end of behavior description .

• V() and I() are access functions defined in disciplines.vams.

• V( p, n ) and I( p, n ) are called branch signals.

• Contribution operator: <+

Verilog-A Examples : resistor model

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 9: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : Contribution operator • Used to give values to continuous signals: Branch voltage or Current.

• Multiple contributions to the same branch in the same analog process accumulate.

• This is equivalent to :

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 10: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : conductance model

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 11: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples: capacitor model

• The ddt operator returns the time derivative of its argument .

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 12: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : inductor model

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 13: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : DC Voltage Source

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 14: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : DC Current Source

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 15: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : VCVS

• How to change to VCCS ?

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Page 16: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : Ideal Relay ( SPST switch )

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 17: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : Ideal Relay (SPST switch )• if (condition )

action // if more than one line began is added after condition and end is added after actions .

@( cross(wave [, dir ][, ttol ][, tol ][, enable]) )

• Generates events at zero crossings.

• Parameters :

• wave (real) look for zero crossings in this waveform.

• dir (real) direction (use + 1 for rising, 1 for falling, 0 for either).

• ttol (real) time tolerance.

• tol (real) waveform tolerance.

• enable (real) enable Return.

• Specifying ttol allows events that are close to be combined for simulation efficiency reasons.

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 18: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : Ideal Relay ( SPST switch )

• model nonlinear- Relay ??

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 19: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A Examples : sample and hold

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 20: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

• @( timer (toff , period) or initial_step ) )

• The timer function produces an event at

-toff + n*period (n = 0 , 1 , ....)

• The second source of events is initial_step , a built in event source that produces a single event at the beginning of the simulation time interval.

• It is generally used for initialization, and this case initializes the sample and hold.

• The events produced by these event sources are combined using the or keyword.

• When an event occurs, the event statement executes its event clause, in this case a statement that assigns the value of the input to a local variable ,save.

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

Verilog-A Examples : sample and hold

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Page 21: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

• transition(operand, delay, trise [, tfall ])

• Parameters :

• operand (real) signal to be smoothed (must be piecewise constant).

• delay (real) delay.

• trise (real) transition time (or the rise time if fall time is also given).

• tfall (real) fall time.

• ttol (real) time tolerance.

• Notes :

• Make delay = zero or as large as possible.

• Make trise & tfall as large as possible Otherwise short time step will be forced.

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

Verilog-A Examples : sample and hold

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Page 22: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

OP-Amp: Ideal model

• Op-Amp is a VCVS with ( A ∞ ) , R_input∞ , R_output 0

• (𝑉𝑜 (𝑆)

𝑉𝑖(𝑆)= A ) is constant with frequency .

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 23: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Non-ideal Op-Amp

• R_input∞ , R_output 0 ,but 𝑉𝑜 (𝑆)

𝑉𝑖(𝑆)=

𝐺𝑚𝑅1

1+𝑠𝑅1𝐶1

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 24: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

• Important terms:• GBW ( Gain Bandwidth product ) : constant

value specify relation between open loop gain (𝐺𝑚𝑅1) and corner frequency ( 𝑓𝑏=

1

2𝜋𝑅1𝐶1)

• fT ( Unity Gain frequency ): frequency at which the gain = 0dB

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

Non-ideal Op-Amp

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Page 25: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in Cadence http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ICDesignVerilogA

1. Open a new cellview by going to File > New > Cellview in the CIW window.

2. In the New File window, choose your working library and name your new cell. Choose VerilogA in the Type menu. Click OK.

3. A blank Verilog-A template should pop up. Transfer your Verilog A code into the window and save.

• When you close the window, the code is checked for syntax errors. If there are any errors, a window will appear that says "Parsing of veriloga file failed: Do you want to view the error file and re edit the veriloga file?" If you choose yes, a list of warnings/errors will appear. Fix them, resave the file, and close the Verilog A file

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ICDesignVerilogA
Page 26: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

4. A new window will ask if you want to create the symbol view for your component. Click yes and use the symbol editor to design the graphical view for the component. Save the symbol view.

5. Now your component can be used in circuit simulations

• Notes:• The default text editor in Virtuoso is Vim.

• If you don't want to use Vim you can change which editor Virtuoso uses by typing <editor= gedit "> (without brackets) in the CIW window and pressing enter.

• You can replace gedit " with whichever editor you want to use (vi, kedit ,etc ).

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

Verilog-A in Cadence

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Page 27: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

• In ADE L, when simulating circuits that contain Verilog A code, make sure to add " veriloga " (without quotes) to the stop view list.

- This can be accessed by going to Setup > Environment

- A better way to manage it is by using config view and hierarchy editor

• Any variable that is defined as a "parameter" in the Verilog A code can be altered from the schematic view of the component.

- Open the properties for the instance you want to change.

- Change the "CDF Parameter of view" option from "Use Tools Filter" to "veriloga”

- This should bring up all of the available parameters for editing.

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

Verilog-A in Cadence

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Page 28: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in Cadence :Model writer

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 29: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in Cadence: Model writer

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 30: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in Cadence : A new Verilog-A cell

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 31: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in Cadence : Symbol Generation

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 32: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in cadence: Test bench

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 33: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in Cadence : add instant with parameters

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 34: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in cadence: Test bench

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 35: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in Cadence : Config view

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 36: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in Cadence : add instant with parameters

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 37: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in Cadence : hierarchy director

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 38: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Verilog-A in cadence : Associated ADE with config view

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

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Page 39: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

References

• ECE 511 Computer Aided Circuit Design – ASU faculty of Engineering .

• ❑ K. Kundert and O. Zinke, The Designer's Guide to Verilog-AMS, 2004

http://www.designers-guide.org/VerilogAMS/

http://www.designers-guide.org/Books/dg-vams/

• Verilog-A Reference Manual (excellent resource)

• http://literature.cdn.keysight.com/litweb/pdf/ads2004a/pdf/verilogaref.pdf

• http://verilogams.com/

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Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo

http://www.designers-guide.org/VerilogAMS/
http://www.designers-guide.org/Books/dg-vams/
http://literature.cdn.keysight.com/litweb/pdf/ads2004a/pdf/verilogaref.pdf
http://verilogams.com/
Page 40: Introduction to Verilog-A...Verilog-A History •Verilog AMS was first released in 2000 , latest version in 2014. •Verilog AMS combines both VHDL and Verilog-A, and adds additional

Thank You

Microelectronics Course ELCT 703Electronics Dept., Faculty of IETThe German University in Cairo


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