introduction to verilog (dr. vu)

2006dce

Introduction to Verilog HDL

Dr. Anh-Vu Dinh-Duchttp://www.cse.hcmut.edu.vn/~anhvu

http://www.cse.hcmut.edu.vn/~anhvu

©2007, Dr. Dinh Duc Anh Vu 2Introduction to Verilog HDL

2007dce Outline

• Design flow• What is a HDL?• Verilog HDL – A tutorial • Language elements• Verilog Expressions

• Gate-level modeling• User-defined primitives• Dataflow modeling• Behavioral modeling• Structural modeling• Lots of examples• Advanced topics


2007dce Remember: to design is to represent

• How do we represent digital designs?– You can read it again later– Someone else can read and understand it– It can be simulated and verified– Even software people may read it!– It can be synthesized into specific gates– It can be built and shipped and make money

• Components– Logic symbol, truth table– Storage symbol, timing diagram

• Connections– Schematics

Human readable or machine readable ???


2007dce Netlist

• A key data structure (or representation) in the design process is the “netlist”:– Network List

• A netlist lists components and connects them with nodes:– Ex:

g1 "and" n1 n2 n5g2 "and" n3 n4 n6g3 "or" n5 n6 n7

• Netlist is needed for simulation and implementation

• Could be at the transistor level, gate level, ...

• Could be hierarchical or flat• How do we generate a netlist?

Alternative format:n1 g1.in1 n2 g1.in2n3 g2.in1n4 g2.in2n5 g1.out g3.in1n6 g2.out g3.in2n7 g3.outg1 "and"g2 "and"g3 "or"

n1n2n3n4

n5

n6

n7g1

g2g3


2007dce Digital Design Flow

• Design Specification• Design Partition• Design Entry: Verilog Behavioral

Modeling• Simulation/Functional Verification• Design Integration and Verification• Presynthesis Sign-Off• Synthesize and Map Gate-Level

Netlist• Postsynthesis Design Validation• Postsynthesis Timing Verification• Test Generation and Fault Simulation• Cell Placement, Scan Chain and

Clock Tree Insertion, Cell Routing• Verify Physical and Electrical Design

Rules• Extract Parasitic• Design Sign-OffLow-level

Analysis

High-level Analysis

DesignEntry

TechnologyMapping


2007dce Digital Design Flow

• Circuit is described and represented:– Graphically (Schematics)– Textually (HDL)

• Result of circuit specification (and compilation) is a netlist of:– generic primitives - logic

gates, flip-flops, or– technology specific primitives -

LUTs/CLBs, transistors, discrete gates, or

– higher level library elements -adders, ALUs, register files, decoders, etc.

LowLowLow---levellevellevelAnalysisAnalysisAnalysis

HighHighHigh---level level level AnalysisAnalysisAnalysis

DesignEntry

TechnologyTechnologyTechnologyMappingMappingMapping


2007dce Design Flow

• High-level Analysis is used to verify– correct function– rough

• timing• power• cost

• Common tools used are:– simulator - check functional

correctness, and– static timing analyzer

• estimates circuit delays based on timing model and delay parameters for library elements (or primitives)

LowLowLow---levellevellevelAnalysisAnalysisAnalysis

High-level Analysis

DesignDesignDesignEntryEntryEntry

TechnologyTechnologyTechnologyMappingMappingMapping


2007dce Design Flow

• Technology Mapping– Converts netlist to

implementation technology dependent details

• Expands library elements,• performs:

– partitioning, – placement, – routing

• Low-level Analysis– Simulation and Analysis Tools

perform low-level checks with:• accurate timing models,• wire delay

– For FPGAs this step could also use the actual device

Low-levelAnalysis

HighHighHigh---level level level AnalysisAnalysisAnalysis

DesignDesignDesignEntryEntryEntry

TechnologyMapping


2007dce

Netlist:used between andinternally for all steps

Design Flow

Low-levelAnalysis

High-level Analysis

DesignEntry

TechnologyMapping


2007dce Design Entry

• Hardware Description Languages (HDLs) are the new standard– except for PC board design,

where schematics are still used.

• Schematic entry/editing used to be the standard method in industry

• Schematics are intuitive. They match our use of gate-level or block diagrams.

• Somewhat physical. They imply a physical implementation.

• Require a special tool (editor).• Unless hierarchy is carefully

designed, schematics can be confusing and difficult to follow.


2007dce Outline




2007dce What is a HDL?

• Textual representation of a digital logic design– Can represent specific gates, like a netlist, or more

abstract logic

• HDLs are not “programming languages”– No, really. Even if they look like it, they are not.– For many people, a difficult conceptual leap

• Similar development chain– Compiler: source code assembly code binary

machine code– Synthesis tool: HDL source gate-level specification

hardware


2007dce What is a HDL?

• “Structural” example:

Decoder (output x0,x1,x2,x3;inputs a,b)

{wire abar, bbar;inv (bbar, b);inv (abar, a);nand (x0, abar, bbar);nand (x1, abar, b);nand (x2, a, bbar);nand (x3, a, b);

}

• “Behavioral” example:

Decoder (output x0,x1,x2,x3;inputs a,b)

{case [a b]00: [x0 x1 x2 x3] = 0x0;01: [x0 x1 x2 x3] = 0x2;10: [x0 x1 x2 x3] = 0x4;11: [x0 x1 x2 x3] = 0x8;endcase;

}

• Basic Idea– Language constructs describe

circuits with two basic forms:• Structural descriptions similar to

hierarchical netlist• Behavioral descriptions use

higher-level constructs (similar to conventional programming)

• Originally designed to help in abstraction and simulation– Now “logic synthesis” tools exist

to automatically convert from behavioral descriptions to gate netlist.

– Greatly improves designer productivity

– However, this may lead you to falsely believe that hardware design can be reduced to writing programs!


2007dce

Why an HDL is not a Programming Language

• In a program, we start at the beginning (e.g. “main”), and we proceed sequentially through the code as directed

• The program represents an algorithm, a step-by-step sequence of actions to solve some problem

for (i=0; i<10; i=i+1) {if (newPattern==oldPattern[i]) match=i;

}

• Hardware is all active at once; there is no starting point


2007dce Pitfalls of trying to “program” in Verilog

• If you program sequentially, the synthesizer may add a lot of hardware to try to do what you say– In last example, need a priority encoder

• If you program in parallel (multiple “always” blocks), you can get non-deterministic execution– Which “always” happens first?

• You create lots of state that you didn’t intendif (x == 1) out = 0;if (y == 1) out = 1; // else out retains previous state? R-S latch!

• You don’t realize how much hardware you’re specifying– x = x + 1 can be a LOT of hardware

• Slight changes may suddenly make your code “blow up”– A chip that previously fit suddenly is too large or slow


2007dce Two Roles of HDL and Related Tools

• #1: Specifying digital logic– Specify the logic that appears in final design– Either

• Translated automatically (called synthesis) or• Optimized manually (automatically checked for

equivalence)

• #2: Simulating and testing a design– High-speed simulation is crucial for large designs– Many HDL interpreters optimized for speed– Testbench: code to test design, but not part of

final design


2007dce

HDLSpecification

Structure and Function(Behavior) of a Design

Simulation

Verification: Design Behave as Required?Functional: I/O BehaviorRegister-Level (Architectural)Logic-Level (Gates)Transistor-Level (Electrical)Timing: Waveform Behavior

Synthesis

Generation: Map Specification to Implementation

HDL Design Methodology


2007dce

Structural vs. Behavioral HDL Constructs• Structural constructs specify actual hardware structures

– Low-level, direct correspondence to hardware• Primitive gates (e.g., and, or, not)• Hierarchical structures via modules

– Analogous to programming software in assembly• Behavioral constructs specify an operation on bits

– High-level, more abstract• Specified via equations, e.g., out = (a & b) | c

• Not all behavioral constructs are synthesizable – We’ve already talked about the pitfalls of trying to “program”– But even some combinational logic won’t synthesize well– out = a % b // modulo operation – what does this synthesize to?– We will not use: + - * / % > >= < <= >> <<


2007dce Synthesis vs. Simulation

• HDLs have features for both synthesis and simulation– E.g., simulation-only operations for error messages, reading files– Obviously, these can be simulated, but not synthesized into circuits– Also has constructs such as for-loops, while-loops, etc.

• These are either un-synthesizable or (worse) synthesize poorly– You need procedural code for testbench and only for testbench

• Trends: a moving target – Good: better synthesis tools for higher-level constructs– Bad: harder than ever to know what is synthesizable or not

• Important distinction: What is a “higher-level” construct and what is “procedural code”?


2007dce HDL Design Methodology

HDL for Specification

HDL for Simulation

HDL for Synthesis


2007dce Why use an HDL?

• Easy to write and edit• Compact• Don’t have to follow a maze of lines• Easy to analyze with various tools

Why not to use an HDL• You still need to visualize the flow of logic• A schematic can be a work of art

– But often isn’t!


2007dce Quick History of HDLs

• ISP (circa 1977) - research project at CMU– Simulation, but no synthesis

• Abel (circa 1983) - developed by Data-I/O– Targeted to programmable logic devices– Not good for much more than state machines

• Verilog (circa 1985) - developed by Gateway (now Cadence)– Specification became open in 1985– Similar to Pascal and C programming language, originally developed for simulation– Fairly efficient and easy to write– 80s Berkeley develops synthesis tools– IEEE standard

• Verilog standardized (Verilog-1995 standard)• Continued evolution (Verilog-2001 standard)

• VHDL (circa 1987) - DoD sponsored standard– Based on VHSIC developed by DARPA– Similar to Ada (emphasis on re-use and maintainability)– Simulation semantics visible– Very general but verbose– IEEE standard

• VHDL standardized (’87 and ’93)– Strict syntax


2007dce And the answer is…

• In general, digital logic is captured in an HDL• For government / aerospace work, it’s VHDL• For all else, it’s Verilog• (This is, of course, a generalization…)

Verilog is not perfect!• But then, neither is the X86 instruction set.• And it’s nowhere near that bad.• In fact, it’s pretty good…

– If you know what to watch out for.


2007dce So, about Verilog HDL …

• Verilog is a (surprisingly) big language– Lots of features for synthesis and simulation of hardware– Can represent low-level features, e.g. individual transistors– Can act like a programming language, with “for” loops etc.

• Simulation tools typically accept full set of Verilog language constructs– Some language constructs and their use in a Verilog description make

simulation efficient and are ignored by synthesis tools• Synthesis tools typically accept only a subset of the full

Verilog language constructs• We’re going to learn a focused subset of Verilog

– We will use it at a level appropriate– Focus on synthesizable constructs – Focus on avoiding subtle synthesis errors– Initially restrict some features just because they aren’t necessary– Rule: if you haven’t seen it approved, you can’t use it


2007dce References


2007dce Outline




2007dce Verilog HDL – A Tutorial

• The module concept– Basic design unit

• Describes the communicating ports for external interfacing with other modules

• Describes the functionality or structure of a design

– Declarations and statements can be interspersed within a module

• A declaration must appear before its use

• For clarity and readability, it is best to put all declarations before any statements

– Modules are:• Declared (defined)• Instantiated

– Modules declarations cannot be nested

module module_name (port_list);Declarations:

reg, wire, parameter,input, output, inout,function, task, …

Statements:Initial statementAlways statementModule instantiationGate instantiationUDP instantiationContinuous assignment

endmodule

Module declaration


2007dce Three Module Components

module full_adder (A, B, CI, S, CO);

input A, B, CI ;output S, CO ;

wire N1, N2, N3;

half_adder HA1 (A, B, N1, N2),

HA2 (N1, CI, S, N3);or P1 (CO, N3, N2);

endmodule

Interface specification

Declaration

Implementation

module full_adder (input A, B, CI; output S, CO);

New style (Verilog 2001)

Internal wires, also known as “nets” or “signals”

primitive and module instantiations


2007dce Module Declaration

• Annotated example

/* module_keyword module_identifier (list of ports) */

module C_2_4_decoder_with_enable (A, E_n, D) ; input [1:0] A ; // input_declarationinput E_n ; // input_declarationoutput [3:0] D ; // output_declaration

assign D = {4{~E_n}} & ((A == 2'b00) ? 4'b0001 :(A == 2'b01) ? 4'b0010 :(A == 2'b10) ? 4'b0100 :(A == 2'b11) ? 4'b1000 :4'bxxxx) ; // continuous_assign

endmodule

Identifiers - must not be keywords!

First example of signals

Scalar: e. g., E_n

Vector: e. g., A[1:0], A[0:1], D[3:0], and D[0:3]• Range is MSB to LSB• Can refer to partial ranges - D[2:1]

Type: defined by keywordsinputoutputinout (bi-directional)


2007dce Module Instantiation

• Examplemodule C_4_16_decoder_with_enable (A, E_n, D) ;

input [3:0] A ; input E_n ; output [15:0] D ;

wire [3:0] S;wire [3:0] S_n;

C_2_4_decoder_with_enable DE (A[3:2], E_n, S);not N0 (S_n, S);C_2_4_decoder_with_enable D0 (A[1:0], S_n[0], D[3:0]);C_2_4_decoder_with_enable D1 (A[1:0], S_n[1], D[7:4]);C_2_4_decoder_with_enable D2 (A[1:0], S_n[2], D[11:8]);C_2_4_decoder_with_enable D3 (A[1:0], S_n[3], D[15:12]);

endmodule



• Hierarchy– Build up more complex modules using simpler modules

• More Examples– Single module instantiation for five module instances

C_2_4_decoder_with_enable DE (A[3:2], E_n, S),D0 (A[1:0], S_n[0], D[3:0]),D1 (A[1:0], S_n[1], D[7:4]),D2 (A[1:0], S_n[2], D[11:8]),D3 (A[1:0], S_n[3], D[15:12]);

– Named_port connection

C_2_4_decoder_with_enable DE (.E_n (E_n), .A (A[3:2]) .D (S));// Note: order in list no longer important (E_n and A interchanged).// (but it is still poor practice to mix them up)


2007dce Module Description

• Four styles to describe a design– Structural style

• Instantiation of primitives and modules• List of components and how they are connected

– Explicit structure of the circuit• Just like schematics, but using text

– A netlist• Tedious to write, hard to decode• Essential without integrated design tools

– Behavioral style• Procedural assignments• Describe what a component does, not how it does it

– Program describes input/output behavior of circuit• Synthesized into a circuit that has this behavior• Result is only as good as the tools

– RTL/Dataflow Verilog • Continuous assignments

– Any mixed of above


2007dce Delay

• All delays are specified in terms of time units

• A time unit is associated with the physical time by `timescale compiler directive– This directive is specified before a module declaration

– If no compiler directive is specified, it depends on the Verilog simulator to default to a certain time unit (not specified by the IEEE standard)

assign #2 sum = A ^ B;

`timescale 1ns / 100ps

2 time units

Time unit Time precision


2007dce Dataflow Style

• Continuous assignmentassign [delay] LHS_net = RHS_expression;

V1N3

N0

N1

N2

V0A

B

EN

Z[0]

Z[1]

Z[2]

Z[3]

Abar

Bbar

`timescale 1ns/1nsmodule Decoder2x4 (A, B, EN, Z);

input A, B, EN;output [0:3] Z;wire Abar, Bbar;

assign #1 Abar = ~A;

assign #1 Bbar = ~B;assign #2 Z[0] = ~(Abar & Bbar & EN);

assign #2 Z[0] = ~(Abar & B & EN);assign #2 Z[0] = ~(A & Bbar & EN);assign #2 Z[0] = ~(A & B & EN);

endmodule


2007dce Decoder2x4 Simulation Result

V1N3

N0

N1

N2

V0A

B

EN

Z[0]

Z[1]

Z[2]

Z[3]

Abar

Bbar

`timescale 1ns/1nsmodule Decoder2x4 (A, B, EN, Z);input A, B, EN;output [0:3] Z;wire Abar, Bbar;

assign #1 Abar = ~A;assign #1 Bbar = ~B;assign #2 Z[0] = ~(Abar & Bbar & EN);assign #2 Z[0] = ~(Abar & B & EN);assign #2 Z[0] = ~(A & Bbar & EN);assign #2 Z[0] = ~(A & B & EN);endmodule


2007dce Dataflow Style – Full Adder

module fa_rtl (A, B, Cin, Sum, Cout) ;input A, B, Cin;output Sum, Cout;

assign Sum = A ^ B ^ Cin; assign Cout = A & B | A & Cin | B & Cin;

endmodule

A

B

Cin

Sum

CoutO1

A1

X1X2

A2

A3


2007dce Behavioral Style

• Procedural construct– initial statement: executes only once– always statement: always executes in a loop (repeatedly)

• Only a register data type can be assigned a value in these statements– Register data type retains its value until a new value is assigned– All initial and always statements begin execution at time 0 concurrently

module fa_bhv (A, B, Cin, Sum, Cout);input A, B, Cin;output Sum, Cout;reg Sum, Cout;

always @(A or B or CI) begin

Sum = A ^ B ^ Cin;Cout = A & B | A & Cin | B & Cin;

end endmodule

Register data type is required to “hold” values between events

Sequential block: consists of procedural assigments


2007dce

Behavioral Style – Procedural Assignment

• A procedural assignment may optionally have a delay– Inter-statement delay: this is the delay by which a

statement’s execution is delayed– Intra-statement delay: this is the delay between computing

the value of the RHS expression and its assignment to the LHS

– If no delays are specified, zero delay is the default• Assignment occurs instantaneously

Sum = #3 A ^ B ^ Cin;#4 Cout = A & B | A & Cin | B & Cin;

Inter-statement delay

Intra-statement delay


2007dce Behavioral Style – initial Statement

`timescale 1ns/1nsmodule Test (Pop, Pid);output Pop, Pid;reg Pop, Pid;

initialbegin

Pop = 0;Pid = 0;Pop = #5 1;Pid = #3 1;Pop = #6 0;Pid = #2 0;

endendmodule


2007dce Structural Style

• Structure can be described using– Built-in gate primitives (gate-level)– Switch-level primitives (transistor-level)– User-defined primitives (gate-level)– Module instances (to create hierarchy)

• Interconnections are specified by using netsmodule fa_str (A, B, Cin, Sum, Cout);input A, B, Cin;output Sum, Cout;wire S1, T1, T2, T3;

xorX1 (S1, A, B);X2 (Sum, S1, Cin);

andA1 (T3, A, B);A2 (T2, B, Cin);A3 (T1, A, Cin);

orO1 (Cout, T1, T2, T3);

endmodule

A

B

Cin

Sum

CoutO1

A1

X1X2

A2

A3T1

T2

T3

S1


2007dce Mixed-Design Style

• A module can contain a mixture of gate instantiations, module instantiations, continuous assignments, always and initial statements

module fa_mix (A, B, Cin, Sum, Cout);input A, B, Cin;output Sum, Cout;reg Cout;wire S1;

xor X1 (S1, A, B);

always @(A or B or Cin)begin

Cout = A & Cin | B & Cin | A & B;end

assign Sum = S1 ^ Cin;

endmodule

gate instantiations

always statement

continuous statement


2007dce

S

OutB

A

module mux2to1 (input S, A, B,output Out);assign Out = (~S & A) | (S & B);

endmodule

Behavioral

module mux2to1 (input S, A, B,

output Out);wire S_, AnS_, BnS;not (S_, S);

and (AnS_, A, S_);and (BnS, B, S);or (Out, AnS_, BnS);

endmodule

Structural

Better

Modeling Style – Another Example

module mux2to1 (input S, A, B,output Out);assign Out = S?B:A;

endmodule


2007dce Simulating a Design

• Verilog is also used to model stimulus, control, storing responses and verification– Stimulus and control can be generated using initial

statements– Responses from the design under test can be

saved as “save on change” or as strobed data– Verification can be performed by automatically

comparing with expected responses by writing appropriate statements in an initial statement



`timescale 1ns/1nsmodule Top;reg PA, PB, PCi;wire PCo, PSum;

fa_rtl F1 (A, B, Cin, Sum, Cout);

initialbegin ONLY_ONCE

reg [3:0] Pal;for (Pal=0; Pal<8; Pal=Pal+1)

begin{Pa, PB, PCi} = Pal;#5 $display (“PA, PB, PCin = %b%b%b ”, PA, PB, PCin,

“=> PCo, PSum = %b%b”, PCo, PSum);end

end

endmodule

PA, PB, PCin = 000 => PCo, PSum = 00PA, PB, PCin = 001 => PCo, PSum = 01PA, PB, PCin = 010 => PCo, PSum = 01PA, PB, PCin = 011 => PCo, PSum = 10PA, PB, PCin = 100 => PCo, PSum = 01PA, PB, PCin = 101 => PCo, PSum = 10PA, PB, PCin = 110 => PCo, PSum = 10PA, PB, PCin = 111 => PCo, PSum = 11



`timescale 10ns/1nsmodule RS_FF (Q, Qb, R, S);output Q, Qb;input R, S;

nand #1 (Q, R, Qb);nand #1 (Qb, S, Q);endmodule

module Test;reg TS, TR;wire TQ, TQb;

RS_FF MUT (.Q(TQ), .S(TS),.R(TR), .Qb(TQb));

At time 0, TR=0, TS=0, TQ=x, TQb=xAt time 10, TR=0, TS=0, TQ=1,TQb=1 At time 50, TR=0, TS=1, TQ=1,TQb=1At time 60, TR=0, TS=1, TQ=1,TQb=0At time 100, TR=1, TS=0, TQ=1,TQb=0 At time 110, TR=1, TS=0, TQ=1,TQb=0At time 120, TR=1, TS=0, TQ=0,TQb=1…

initialbegin

TR = 0;TS = 0;#5 TS = 1;#5 TS = 0;TR = 1;#5 TS = 1;TR = 0;#5 TS = 0;#5 TR = 1;

end

initial$monitor (“At time %t, “, $time,

“TR=%b, TS=%b, TQ=%b, TQb=%b”, TR, TS, TQ, TQb);

endmodule


2007dce Outline




2007dce Verilog Language Elements

• Identifiers• Comments• Format• Systems tasks and functions• Compiler directives• Value set• Data types• Parameter


2007dce

• Different names must be used for different items within the same scope

• Identifier alphabet– Upper and lower case alphabetical– Decimal digits– Underscore (_)– $

• Maximum of 1024 characters in identifier• First character not a digit• Case-sensitivity

– Verilog is case-sensitive– Some simulators are case-insensitive– Advice: Don’t use case-sensitive feature!– Keywords are lower case

Identifiers


2007dce Comments

• Two form of comments:– All characters after // in a line are treated as a

comment

– Multi-line comments begin with /* and end with *//* Second form: can* extend across* many* lines */

// First form: ends at the end of this line


2007dce Format

• Free format within statement except for within quotes– Constructs may be written across multiple lines or on one line– White space (newline, tabulation and space characters) have no

significance– Strings enclosed in double quotes and must be on a single line

initialbegintop = 3’b001;#2 top = 3’b110;

end

initial begin top = 3’b001; #2 top = 3’b110; end


2007dce System Tasks and Functions

• Built-in system tasks or functions begin with $– A task can return zero or more values– A function is like a task except that it can return

only one value– A function executes in zero time (no delays are

allowed) while a task can have delays

$time // this system function returns the current simulation time

$display (“Hi, you have reached LT today”);/* the $display system task displays the specified message* to output with a newline character */


2007dce Compiler Directives

• Compiler directives start with the ` (backquote) character• A compiler directive when compiled remains in effect through

the entire compilation process (which could span multiple files) until a different compiler directive specifies otherwise

• Complete list of standard compiler directives– `define, ùndef– ìfdef, èlse, èndif– `default_nettype– ìnclude– `resetall– `timescale– ùnconnected_drive, `nounconnected_drive– `celldefine, èndcelldefine


2007dce `define and ùndef

• `define is used for text substitution• Like #define and #undef in the C language

`define MAX_BUS_SIZE 32…reg [`MAX_BUS_SIZE-1:0] address_register;

`define WORD 16…wire [`WORD-1:0] bus;…ùndef WORD/* the definition of WORD is no longer available* after this ùndef directive */


2007dce ìfdef, èlse and èndif

• Used for conditional compilation• èlse directive is optional with the ìfdef directive

ìfdef WINDOWSparameter WORD_SIZE = 16;

èlseparameter WORD_SIZE = 32;

èndif


2007dce `default_nettype

• Used to specify the net type for implicit net declarations (i.e. for nets that are not declared)

`default_nettype wand


2007dce `include

• Like #include in the C language• Used to include the contents of any file in-line

– The file can be specified either with a relative path name or with a full path name

`include “../../primitives.v”


2007dce `resetall

• Resets all compiler directives to their default value– E.g. causes the default net type to be wire

`resetall


2007dce `timescale

• Used to specify the time unit and time precision

– time_unit and time_precision is made up of values from 1, 10and 100 and units from s, ms, us, ns, ps and fs

• The `timescale directive affects all delays in modules that follow this directive in a compilation until another `timescale or `resetalldirective is found

• The directive appears outside of a module declaration

• What happens?

`timescale time_unit/time_precision

`timescale 1ns/100ps

`timescale 1ns/100psmodule andfunc (Z, A, B);output Z;input A, B;and #(5.22, 6.17) A1 (Z, A, B);endmodule

`timescale 10ns/1nsmodule testbench;reg PutA, PutB;wire GetO;andfunc AF1 (GetO, PutA, PutB);initialbeginPutA = 0;PutB = 0;#5.21 PutB = 1;#10.4 PutA = 1;

endendmodule


2007dce

ùnconnected_drive and `nounconnected_drive

• Any unconnected input ports in module instantiations that appear between these two directives are either pulled up or pulled down

ùnconnected_drive pull1…/* all unconnected input ports between these two directives* are pulled up (connected to 1) */`nounconnected_drive

ùnconnected_drive pull0…/* all unconnected input ports between these two directives* are pulled down (connected to 0) */`nounconnected_drive


2007dce `celldefine and `endcelldefine

• Used to mark a module as a cell module– Typically encompass a module definition

• Cell modules are used by some PLI routines

`celldefinemodule andfunc (Z, A, B);output Z;input A, B;

and #(5.22, 6.17) A1 (Z, A, B);

endmodule`endcelldefine


2007dce Value Set

• Four basic values– 0 – Logical 0 or FALSE– 1 – Logical 1 or TRUE– x, X – Unknown logic value– z, Z – High impedance condition (? can be used as an

alternative)• Three types of constants

– Integer– Real– String

• Underscore character (_) can be used for reading clarity– It can not be the first character


2007dce Integer

• Simple decimal– A sequence of digits with an optional + (unary) or – (unary) operator– An integer value represents a signed number: negative number is

represented in 2’s complement form– 32 (10000 in a 5-bit binary and 010000 in 6-bit binary)– –15 (10001 in 5-bit binary and 110001 in a 6-bit binary)

• Base format <size><base_format><number>– <size> - decimal specification of number of bits

• default is unsized and machine-dependent, but at least 32 bits– <base format> - ' followed by arithmetic base of number

• <d> <D> - decimal - default base if no <base_format> given• <h> <H> - hexadecimal• <o> <O> - octal• <b> <B> - binary

– <number> - value given in base of <base_format>• If first character of sized, binary number is 0, 1, the value is 0-filled up to

size. If x or z, value is extended using x or z, respectively• An x or z in a hexadecimal value represents 4 bit of x or z

Always represents an unsigned number


2007dce Integers – Example

• 6’b010_111• 8'b0110 • 3’b1110• 4'bx01• 16'H3AB• 24• 5'O36• 16'Hx• 8'hz• 4'd-4 • 8 'h 2A• (2+3)'d10

gives 010111gives 00000110gives 110gives xx01gives 0000001110101011gives 0…0011000gives 11100gives xxxxxxxxxxxxxxxxgives zzzzzzzznot legal: value cannot be negativespaces are not allowednot legal: size cannot be an expression


2007dce Reals

• Decimal notation– 2.0– 5.678– 0.1– 2. // not legal: must have a digit on either side of decimal

• Scientific notation– 25_3.1e2 = 25310.0– 5E-4 = 0.0005

• Implicit conversion to integer is define by the language– Real numbers are converted to integers by rounding to the nearest

integer– 42.446 → 42– -16.62 → -17– -25.5 → -26


2007dce Strings

• A sequence of characters within double quotes– May not split across lines– “Internal Error”

• No explicit data type• Must be stored in reg whose size is 8*(number of

characters)– reg [255:0] buffer; //stores 32 characters

• The \ (backslash) character can be used to escape certain special characters– \n newline– \t tab– \\ the \ character itself– \” the “ character– \206 character with octal value 206


2007dce Data Types

• Two groups of data types– Net type

• A net type represents a physical connection between structural elements.

• Its value is determined from the value of its drivers such as a continuous assignment or a gate output.

• If no driver is connected to a net, the net defaults to a value of z.– Register type

• A register type represents an abstract data storage element.• Is NOT necessarily a register in the circuit• It is assigned values only within an always statement or an initial

statement, and its value is saved from one assignment to the next.• A register type has a default value of x.

– Properties of Both• Informally called signals• May be either scalar (one bit) or vector (multiple bits)


2007dce Data Types – Nets

• wire – connectivity only; no logical • tri – same as wire, but indicates will be 3-stated in

hardware• wand – multiple drivers - wired and• wor – multiple drivers - wired or• triand – same as wand, but 3-state• trior – same as wor but 3-state• supply0 – Global net GND• supply1 – Global Net VCC (VDD)• tri0, tri1, trireg

net_kind [msb:lsb] net1, net2, …, netN;


2007dce Net Examples

• wire x;• wire x, y;• wire [15:0] data, address;• wire vectored [1:7] control;• wire address = offset + index;• wor interrupt_1, interrupt_2;• tri [31:0] data_bus, operand_bus;

• Value implicitly assigned by connection to primitive or module output


2007dce wire and tri Nets

• If multiple drivers drive a wire (or a tri) net, the effective value of the net is determined by using the following table

wire / tri 0 1 x z0 0 x x 01 x 1 x 1x x x x xz 0 1 x z

wire [3:2] cla, pla, sla;…assign cla = pla & sla;…assign cla = pla ^ sla;

01x

11zx1x


2007dce wor and trior Nets

• If multiple drivers drive this net, the effective value of the net is determined by using the following table

wor / trior 0 1 x z0 0 1 x 01 1 1 1 1x x 1 x xz 0 1 x z


2007dce wand and triand Nets

• If multiple drivers drive this net, the effective value of the net is determined by using the following table

wand / triand 0 1 x z0 0 0 0 01 0 1 x 1x 0 x x xz 0 1 x z


2007dce tri0 and tri1 Nets

• These nets also model wired-logic nets (a net with more than one driver)

• If no driver is driving tri0/tri1 net, its value is 0/1• If multiple drivers drive this net, the effective value of

the net is determined by using the following table

tri0 / tri1 0 1 x z0 0 x x 01 x 1 x 1x x x x xz 0 1 x 0/1


2007dce Initial Value & Undeclared Nets

• Initial value of a net– At tsim = 0, initial value is x

• Undeclared Nets – Default type– Not explicitly declared default to wire– `default_nettype compiler directive can

specify others except for supply0 and supply1


2007dce vectored and scalared Nets

• These keyword are optional• If a net is declared with vectored, then bit-selects

and part-selects of this vector net are not allowed– The entire net has to be assigned

• The default is scalared

wire vectored [3:1] GRB;// bit-select GRB[2] and part-select GRB[3:2]// are not allowed

wor scalared [4:0] best;// same as// wor [4:0] best;// bit-select best[0] and part-select best[3:1]// are allowed


2007dce Data Types – Registers

• reg – stores a logic value• integer – stores values which are not to be

stored in hardware– Defaults to simulation computer register length or

32 bits whichever is larger– No ranges or arrays supported– May yield excess hardware if value needs to be

stored in hardware; in such a case, use sized reg.• time – stores time 64-bit unsigned• real – stores values as real number• realtime – stores time values as real numbers


2007dce reg Register

• Value in a register is always interpreted as an unsigned number

• A memory is an array of registers

• Arrays with more than two dimensions are not allowed• A single reg declaration can be used to declare both registers and

memories

reg [1:4] comb;…comb = -2; // comb has 14 (2’s complement of 2)comb = 5; // comb has 5

reg [msb:lsb] memory1[upper1:lower1],memory2[upper2:lower2];

reg [msb:lsb] reg1, reg2, …, regN;

reg [1:WORDSIZE] Ram[ADDSIZE-1:0], // Ram is a memoryDataReg; // DataReg is a WORDSIZE-bit register


2007dce Register Assignment

• A register may be assigned value only within:– a procedural statement– a user-defined sequential primitive– a task, or – a function.

• A reg object may never by assigned value by:– a primitive gate output or – a continuous assignment

• A memory cannot be assigned a value in one assignment, but a register can.– To assign to a memory: assign a value to each word of a memory individually

reg [1:4] dig; // dig is a 4-bit register…dig = 4’b1101; // OK

reg bog[1:4]; // bog is a memory of four 1-bit registers…dig = 4’b1101; // no OK


2007dce Register Assignment (cont’d)

• Assign values to a memory by using the system tasks– $readmemb – load binary values– $readmemh – load hexadecimal values

1101110010000111000010011010

ram.patt

RomB[7] = 1101RomB[6] = 1100RomB[5] = 1000RomB[4] = 0111RomB[3] = 0000RomB[2] = 1001RomB[1] = 1010

reg [1:4] RomB[7:1]; $readmemb(“ram.patt”, RomB);


2007dce Register Assignment (cont’d)

$readmemb(“ram.patt”, RomB, 5, 3);// only part of the memory is loaded// RomB[5] = 1101// RomB[4] = 1100// RomB[3] = 1000

$readmemb(“ram.patt”, RomB, 3);// start reading from address 3 and continues until 1// RomB[3] = 1101// RomB[2] = 1100// RomB[1] = 1000

@5 1101@3 1100@6 1000@1 0111@2 0000@7 1001@4 1010

ram.pattRomB[5] = 1101RomB[3] = 1100RomB[6] = 1000RomB[1] = 0111RomB[2] = 0000RomB[7] = 1001RomB[4] = 1010

$readmemb(“ram.patt”, RomB);


2007dce integer Register

• Example of integer declarations

• An integer register holds signed quantities

integer integer1, integer2, …, integerN[msb:lsb];

integer A, B, C; // 3 integer registersinteger Hist[3:6]; // an array of four integers


2007dce integer Register (cont’d)

• An integer cannot be accessed as a bit-vector

• Type conversion is automatic– No special functions are necessary

reg [31:0] Breg;integer Bint;... // Bint[5] and Bint[15:0] are not allowedBreg = Bint;/* at this point, Breg[5] abd Breg[15:0] are allowed and* give the corresponding bit-values from the integer Bint */

reg [3:0] Bcq;integer J;J = 6; // J has the value 32’b000...00110Bcq = J; // Bcq has the value 4’b0110Bcq = 4’b0101;J = Bcq; // J has the value 32’b000...00101J = -6; // J has the value 32’b111...11010Bcq = J; // Bcq has the value 4’b1010


2007dce time, real and realtime Register

• The default value of real registers is 0• No range (bit range or word range) is allowed for

declaring a real register.• When assigning values x and z to a real register,

these values are treated as a 0

time CurrentTime; // holds one time value (at least 64 bits)time events[0:31]; // array of time values

real Temperature; realtime CurrTime;

time integer1, integer2, …, integerN[msb:lsb];real real_reg1, real_reg2, …, real_regN;realtime realtime_reg1, realtime_reg2, …, realtime_regN;


2007dce Parameter

• Constant• Used to specify delays and widths of variables• Assigned a value only once

• Note: a parameter value can also be changed at compile time by using a defparamstatement (more details later)

parameter param1 = const_exp1, param2 = const_exp2,paramN = const_expN;

parameter LINELENGTH = 132, ALL_X_S = 16’bx; parameter BIT = 1, BYTE = 8, PI = 3.14;


2007dce Outline




2007dce Verilog Expression – Operands

• An operand can be one of the following– Constant– Parameter– Net– Register– Bit-select– Part-select– Memory element– Function call


2007dce Operand – Constant

• Some examples

• An integer value in an expression is interpreted as either a signed or an unsigned number– Decimal integer: as signed number– Based integer: as unsigned number

– A negative value of an integer is treated differently for an integer with or without a base

256 // unsigned decimal numbers 4’b1011 // sized integer constant’hFBA // unsized integer constant90.006 // real constant“JAMES” // string constant

12 // is 01100 in 5-bit vector form (signed) -12 // is 10100 in 5-bit vector form (signed) 5’b01100 // is decimal 12 (unsigned)5’b10100 // is decimal 20 (unsigned)4’d12 // is decimal 12 (unsigned)

integer cone;cone = -44/4; // result is -11cone = -6’o54/4; // result is 1073741813


2007dce Operands (cont’d)

• Net– Both scalar nets (1-bit) and vector nets (multi-bit)– A value in a net is interpreted as an unsigned value

• Register– Scalar and vector registers– A value in an integer register is interpreted as a signed two’s complement number– A value in a reg register or a time register is interpreted as an unsigned number– Value in real and realtime registers are interpreted as signed floating point values

wire [0:3] Prt; // Prt is a 4-bit vector netwire Bbq; // Bbq is a scalar net

assign Prt = -3; // Prt has the bit-vector 1101 assigned

integer TemA, TemB; reg [1:5] State;time Que[1:5];

TemA = -10; // TemA = 10110 (2’s complement of 10)TemA = ‘b1011; // TemA has the decimal value 11State = -10; // State has the bit-vector 10110 (decimal 22)State = ‘b1011; // State has the bit-vector 01011 (decimal 11)



• Bit-select– If the select expression evaluates to an x or z or if it is out

of bounds, the value of the bit-select is an x

• Part-select– If either of the range index is out of bounds or evaluates to

an x or an z, the part-select value is an x

State[1] && State[4] // register bit-selectPrt[0] | Bbq // net bit-selectState[x] // returns an x

State[1:4] // register part-selectPrt[1:3] // net part-selectState[1:8] // returns an x



• Memory element– A memory selects one word of a memory– No part-select or bit-select of a memory is allowed

• Function call– System function call (start with the $ character) or a user-

defined function call

reg [1:8] Ack, DRAM[0:63];

DRAM[60][2] // not allowedDRAM[60][1:3] // not allowed

Ack = DRAM[60]; // 60th element of memoryAck[2] // OKAck[1:3] // OK

$time + SumOfEvents(A, B)// $time is a system function// SumOfEvents is a user-defined function


2007dce Verilog Expression – Operators

Operators Name Functional Group

[] Bit-select or part-select

() parenthesis

!~

logical negationnegation

LogicalBit-wise

&|~&~|^~^ or ^~

reduction ANDreduction ORreduction NANDreduction NORreduction XORreduction XNOR

ReductionReductionReductionReductionReductionReduction

+–

unary (sign) plusunary (sign) minus

ArithmeticArithmetic

{} concatenation Concatenation

{{}} replication Replication

*/%+–

multiplydividemodulus binary plusbinary minus

arithmeticarithmeticarithmeticarithmeticarithmetic

Operators Name Functional Group

<<>>

shift leftshift right

shiftshift

>>=<<=

greater thangreater than or equal toless thanless than or equal to

relationalrelationalrelationalrelational

==!=

logical equalitylogical inequality

equalityequality

===!==

case equalitycase inequality

equalityequality

& bit-wise AND bit-wise

^^~ or ~^

bit-wise XORbit-wise XNOR

bit-wisebit-wise

| bit-wise OR bit-wise

&& logical AND logical

|| logical OR logical

?: conditional conditional

All operators associate left to rightexcept for the conditional operator (right to left)

PRECEDENCE


2007dce Arithmetic Operators

• If any bit of an operand in an arithmetic operation is an x or a z, the entire result is an x.

• Result size– Size of the largest operand or size of the LHS target (in case of an

assignment)• Unsigned and signed

– Unsigned value: a net, a reg register and an integer in base format notation– Signed value: an integer register and an integer in decimal form

’b10x1 + ’b01111 = ’bxxxxx

reg [0:5] Bar, Arc;reg [1:5] Cfg, Crt;reg [1:8] Adt;integer Tab;

assign Adt = (Bar + Arc) + (Crt + Cfg);

Bar = -4’bd12; // Bar has the decimal value 52 (110100)Tab = -4’d12; // Tab has the value -12 (110100)-4’d12 / 4 // result is 1073741821-12 /4 // result is -3


2007dce Relational Operators

• Result of a relational operator is true (value 1) or false (value 0)

• If any bit in either of the operands is an x or a z, result is an x

• If operands is not of the same size, the smaller operand is zero-filled on the most significant bit side.

23 > 45 // result if false (value 0)52 < 8’hxFF // result is x’b1000 >= ’b01110 // equivalent to ’b01000 >= 4’b01110


2007dce Equality Operators

• Logical equality (== and !=)– Values x and z have their usual meaning– Result may be unknown

• Case equality (=== and !==)– Values x and z are compared strictly as values– Result can never be an unknown

• If operands is not of the same size, the smaller operand is zero-filled on the most significant bit side.

Data = 4’b11x0;Addr = 4’b11x0;

Data == Addr // result is unknown (value x)Data === Addr // result is true (value 1)


2007dce Logical Operators

• For vector operands, a non-zero vector is treated as a 1.• If a bit in any of the operands is an x, the result is also an x.

ABus = 4’b0110;BBus = 4’b0100;

ABus || BBus // result is 1ABus && BBus // result is also 1!ABus // is same as !BBus

// and result is 0


2007dce Bit-wise Operators

^~ (xnor) 0 1 x z0 1 0 x x1 0 1 x xx x x x xz x x x x

^ (xor) 0 1 x z0 0 1 x x1 1 0 x xx x x x xz x x x x

| (or) 0 1 x z0 0 1 x x1 1 1 1 1x x 1 x xz x 1 x x

& (and) 0 1 x z0 0 0 0 01 0 1 x xx 0 x x xz 0 x x x

~ (not) 0 1 x z1 0 x x


2007dce Reduction Operators

• The reduction operators operate on all bits of a single operand and produce a 1-bit result– & (reduction and): if any bit is 0, the result is 0, else if any

bit is an x or a z, the result is an x, else the result is a 1.– ~& (reduction nand): invert of & reduction operator.– | (reduction or): if any bit is 1, the result is 1, else if any bit

is an x or a z, the result is an x, else the result is a 0.– ~| (reduction nand): invert of | reduction operator.– ^ (reduction xor): if any bit is an x or a z, the result is an x,

else if there are even number of 1’s in the operand, the result is 0, else the result is a 1.

– ~^ (reduction xnor): invert of ^ reduction operator.if (^MyReg === 1’bx)

$display (“There is an unknown in the vector MyReg!”);


2007dce Shift Operators

• Shifts the left operand by the right operand number of times• The vacated bits are filled with 0.• If the right operand evaluates to an x or a z, the result of the

shift operation is an z.

• A 2-to-4 decoder can be modeled using a shift operator

reg [0:7] Qreg;

Qreg = 4’b0111;Qreg >> 2 // is 8’b0000_0001

wire [0:3] DecoderOut = 4’d1 << Address[0:1];


2007dce Conditional Operators

• If Cond_expr is an x or a z, the result is a bit-wise operation on Expr1 and Expr2 with the following logic– 0 with 0 gives 0– 1 with 1 give 1– Rest are x

Cond_expr ? Expr1 : Expr2

always#5 Ctr = (Ctr != 25) ? (Ctr+1) : 5;


2007dce Concatenation/Replication Operators

• Concatenation– Concatenation of unsized constant numbers is not allowed.

• Replication

{expr1, expr2, …, exprN}

wire [7:0] Dbus;wire [11:0] Abus;

assign Dbus[7:4] = {Dbus[0], Dbus[1], Dbus[2], Dbus[3]};// assign lower four bits in reverse order to upper four bitsassign Dbus = {Dbus[3:0], Dbus[7:4]};// swap lower and upper four bits{Dbus, 5} // not allowed

{repetition_number {expr1, expr2, …, exprN}}

Abus = {3{4’b1011}}; // 12’b1011_1011_1011Abus = {{4{Dbus[7]}}, Dbus}; // signed extension

{3{1’b1}} // is 111{3{Ack}} // is same as {Ack, Ack, Ack}


2007dce Outline




2007dce Gate-level Modeling

• The built-in Primitive Gates• Multiple-input Gates• Multiple-output Gates• Tristate Gates• Pull Gates• MOS Switches• Bidirectional Switches• Gate Delays• Array of Instances• Implicit Nets• Some examples


2007dce Built-in Primitive Gates

• Gate Level– Multiple-input gates: and, nand, or, nor, xor, xnor– Multiple-output gates: buf , not– Tristate gates: bufif0, bufif1, notif0, notif1– Pull gates: pullup, pulldown

• Switch Level– *mos

• where * is n, p, c, rn, rp, rc;

– *tran+

• where * is (null), r • where + (null), if0, if1 • both * and + not (null)


2007dce Built-in Primitive Gates

• No declaration; can only be instantiated• All output ports appear in list before any input ports

– Restriction does not apply to modules• Optional drive strength, delay, name of instance

and N25 (Z, A, B, C); // instance nameand #10 (Z, A, B, X); // delay

(X, C, D, E); // delay/*Usually better to provide instance name for debugging*/

or N30 (SET, Q1, AB, N5),N41 (N25, ABC, R1);

and #10 N33(Z, A, B, X); // name + delay


2007dce Multiple-input Gates

xor 0 1 x z0 0 1 x x1 1 0 x xx x x x xz x x x x

or 0 1 x z0 0 1 x x1 1 1 1 1x x 1 x xz x 1 x x

and 0 1 x z0 0 0 0 01 0 1 x xx 0 x x xz 0 x x x

• A value z at an input is handled like an x• The output of a multiple-input gate can never be a z


2007dce Multiple-output Gates

buf 0 1 x zoutput 0 1 x x

not 0 1 x zoutput 1 0 x x

InputAOutput1Output2

OutputNnot

InputAOutput1Output2

OutputNbuf


2007dce Tristate Gates

• Tristate gates model three-state drivers– One output, one input and one control

tristate_gate [instance_name] (OutputA, InputB, ControlC);

InputB

notif1

OutputA

ControlC

InputB

notif0

OutputA

ControlC

Controlnotif1

0 1 x z0 z 1 1/z 1/z1 z 0 0/z 0/zx z x x x

Data

z z x x x

Data

Control

xxzxzxxzxx

0/z0/zz011/z1/zz10zx10

notif0 Output is at z if control is at 1Else output is the invert of the input data

Output is at z if control is at 0Else output is the invert of the input data


2007dce Tristate Gates

InputB

bufif1

OutputA

ControlC

InputB

bufif0

OutputA

ControlC

Controlnotif1

0 1 x z0 z 0 0/z 0/z1 z 1 1/z 1/zx z x x x

Data

z z x x x

Data

Control

xxzxzxxzxx

1/z1/zz110/z0/zz00zx10

notif0 Output is at z if control is at 1Else data is transferred to output

Output is at z if control is at 0Else data is transferred to output


2007dce Pull Gates

• Have only one output with no input• A pullup gate places a 1 on its output• A pulldown gate places a 0 on its output

pull_gate [instance_name] (OutputA);


2007dce MOS Switches

• Unidirectional switches• One output, one input and one control input• Data flow can be turned off by appropriately setting the control inputs

gate_type [instance_name] (OutputA, InputB, ControlC);(r)cmos [instance_name] (OutputA, InputB, NControl, PControl);

Controlnmosrnmos 0 1 x z

0 z 0 0/z 0/z1 z 1 1/z 1/zx z x x x

Data

z z z z z

Data

Control

zzzzzxxzxx

1/z1/zz110/z0/zz00zx10

pmosrpmos

InputB OutputA

NControl

cmos switch

InputB OutputA

ControlC

pmos switch

InputB OutputA

ControlC

nmos switch

PControl


2007dce Bidirectional Switches

• tran rtran tranif0 rtranif0 tranif1 rtranif1• Data flows both ways• No propagation delay • tranif0 rtranif0 tranif1 rtranif1 switches can be turned off by

setting a control signal appropriately

– For tranif0 and rtranif0, if ControlC is 1, the bidirectional data flow is disabled

– For tranif1 and rtranif1, if ControlC is 0, the bidirectional data flow is disabled

• tran and rtran switches cannot be turned off

• The strength of the signal reduces when it passes through resistive switches

(r)tran [instance_name] (SignalA, SignalB);

gate_type [instance_name] (SignalA, SignalB, SignalC);


2007dce Gate Delays

• Gate delay is the propagation delay from any gate input to the output– No gate delay, the default delay is zero

• Gate delay comprised of up to three values– Rise delay– Fall delay– Turn-off delay– The transition to x delay (To_x) cannot be explicitly specified, but is determined

from the other values• Multiple-input gates (and, or) and multiple-output gates (not, buf) can have

only up to 2 delays specified (since output never goes to z)gate_type [delay] [instance_name] (terminal_list);

Delay No delay

1 value (d)

2 values (d1, d2)

3 values (d1, d2, d3)

Rise 0 d d1 d1Fall 0 d d2 d2

To_x 0 d min(d1, d2) min(d1, d2, d3)Turn-off 0 d min(d1, d2) d3

not N1 (Qb, Q);nor #2 N2 (o, i1, i2);and #(3, 5) (o, i1, i2, i3);notif1 #(2, 8, 6) (o, i1, i2);


2007dce min:typ:max Delay Form

• A delay for a gate can also be specified in a min:typ:max form

– The minimum, typical and maximum values must be constant expressions

• The selection of which delay to use is usually made as an option during s simulation run

minimum:typical:maximum

nand #(2:3:4, 5:6:7) (out, in1, in2, in3);


2007dce Array of Instances

• A range specification can optionally be specified in a gate instantiation when repetitive instances are required– Can also be applied in a module instantiation

• Note that the instance name is not optional when specifying an array of instances

gate_type [delay] [instance_name] [leftbound:rightbound] (terminal_list);

wire [3:0] Out, InA, InB;

nand NInst [3:0] (Out, InA, InB);

nandNInst3 (Out[3], InA[3], InB[3]);NInst2 (Out[2], InA[2], InB[2]);NInst1 (Out[1], InA[1], InB[1]);NInst0 (Out[0], InA[0], InB[0]);


2007dce Implicit Nets

• An undeclared net by default is implicitly declared as a 1-bit wire

• `default_nettype compiler directive can be used to override the default net type

module add_array (A, B, CIN, S, COUT);input [7:0] A, B;input CIN;output [7:0] S;output COUT;wire [7:1] carry;

full_add FA[7:0] (A, B, {carry, CIN}, S, {COUT, carry});// instantiates eight full_add modules endmodule

Array of Instances – Example


2007dce Gate-level Modeling – An Example

module Mux41 (Z, D0, D1, D2, D3, S0, S1);output Z;input D0, D1, D2, D3, S0, S1;

not (S0bar, S0),(S1bar, S1);

and (T0, D0, S0bar, S1bar),(T1, D1, S0, S1bar),(T2, D2, S0bar, S1),(T3, D3, S0, S1);

or (Z, T0, T1, T2, T3);

endmodule

An instance name cannot be the same as a net name within one module


2007dce 2-to-4 Decoder

module Decoder24 (I, Enable, Z);output [3:0] Z;input [1:0] I;input Enable;

not #(1, 2)V0 (I0bar, I[0]),V1 (I1bar, I[1]);

nand #(4, 3)N0 (Z[0], Enable, I0bar, I1bar),N1 (Z[1], Enable, I[0], I1bar),N2 (Z[2], Enable, I0bar, I[1]),N3 (Z[3], Enable, I[0], I[1]);

endmodule


2007dce Master-Slave Flip-flop

module MS_DFF (D, C, Q, Qbar);output Q, Qbar;input D, C;

notNT1 (NotD, D),NT2 (NotC, C),NT3 (NotY, Y);

nandND1 (D1, D, C),ND2 (D2, C, NotD),ND3 (Y, D1, Ybar),ND4 (Ybar, Y, D2),ND5 (Y1, Y, NotC),ND6 (Y2, NotY, NotC),ND7 (Q, Qbar, Y1),ND8 (Qbar, Y2, Q);

endmodule


2007dce Outline




2007dce User-Defined Primitives (UDP)

• Defining a UDP• Combinational UDP• Sequential UDP


2007dce Defining a UDP

• An UDP definition does not depend on a module definition– Appear outside of a module definition

• An UDP can have only one output and may have one or more inputs– The first port must be the output port– The output can have the value 0, 1 or x (z is not allowed)– Value z on inputs is treated as an x

primitive UDP_name (OutputName, ListOfInputs);

output_declarationlist_of_input_declarations[reg_declaration]

[initial_statement]tablelist_of_table_entries

endtableendptimitive


2007dce Combinational UDP

• The table specifies the various input combination and their corresponding output values– The order of the input ports must match the order of entries in the table– The ? character represents a don’t-care value (0, 1 or x)– Any combination that is not specified is an x for the output

primitive Mux21 (Z, In1, In0, Sel);output Z;input In0, In1, Sel;

table// In1 In0 Sel : Z Note: this line is only a comment

0 ? 1 : 0 ; 1 ? 1 : 1 ;? 0 0 : 0 ;? 1 0 : 1 ;0 0 x : 0 ;1 1 x : 1 ;



2007dce Sequential UDP

• The internal state is described using a 1-bit register– The value of this register is the output of the sequential

UDP• 2 kinds of sequential UDP

– Level-sensitive behavior– Edge-sensitive behavior

• A sequential UDP uses the current value of the register and the input values to determine the next value of the register

• Initializing the state register

initial reg_name = 0, 1 or x;


2007dce Level-sensitive Sequential UDP

primitive D_Latch (Q, Clk, D);output Q;reg Q;input Clk, D;

table// Clk D Q(state) Q(next)

0 1 : ? : 1; 0 0 : ? : 0;1 ? : ? : -;


The – character implies a “no change”

D-type latch: as long as the clock is 0, data passes from the input to the output, else the value remains latched


2007dce Edge-triggered Sequential UDP

primitive D_Edge_FF (Q, Clk, D);output Q;reg Q;input Clk, D;

initial Q = 0;table// Clk D Q(state) Q(next)

(01) 0 : ? : 0; (01) 1 : ? : 1;(0x) 1 : 1 : 1;(0x) 0 : 0 : 0;

// ignore negative edge of clock(?0) ? : ? : -;

// ignore data changes on steady clock? (??) : ? : -;

endtableendptimitive (01) indicates a transition from 0 to 1

(??) indicates any transition


2007dce Mixed Sequential UDP

primitive D_Async_FF (Q, Clk, Clr, D);output Q;reg Q;input Clk, Clr, D;

table// Clk Clr D Q(state) Q(next)

(01) 0 0 : ? : 0; (01) 0 1 : ? : 1;(0x) 0 1 : 1 : 1;(0x) 0 0 : 0 : 0;

// ignore negative edge of clock(?0) 0 ? : ? : -;(??) 1 ? : ? : 0;? 1 ? : ? : 0;



2007dce 3-bit Majority Circuit

primitive Majority3 (Z, A, B, C);output Z;input A, B, C;

table// A B C : Z

0 0 ? : 0;0 ? 0 : 0;? 0 0 : 0;1 1 ? : 1;1 ? 1 : 1;? 1 1 : 1;


Symbol Meaning 0 Logic 01 Logic 1x Unknown ? Any of 0, 1 or xb Any of 0 or 1– No change

(AB) Value change from A to B* Same as (??)r Same as (01)f Same as (10)p Any of (01), (0x) or (x1)n Any of (10), (1x) or (x0)


2007dce Outline




2007dce Dataflow Modeling

• Continuous Assignment• Net Declaration Assignment• Delays• Net Delays


2007dce Continuous Assignment

• A continuous assignment assigns a value to a net– Not to a register

• Whenever an event occurs on an operand used in the RHS_expression, the expression is evaluated and if the result value is different, it is assigned to the LHS target

• The target in a continuous assignment can be one of– Scalar net – Vector net– Constant bit-select of a vector– Constant part-select of a vector– Concatenation of any of above

assign [delay] LHS_net = RHS_expression;

wire [3:0] Sum, A, B;wire Cout, Cin;

assign Cin = Preset & Clear;assign {Cout, Sum} = A + B + Cin;

assign Mux = (S==0) ? A: ’bz;assign Mux = (S==1) ? B: ’bz;assign Mux = (S==2) ? C: ’bz;assign Mux = (S==3) ? D: ’bz;

assign Mux = (S==0) ? A: ’bz;Mux = (S==1) ? B: ’bz;Mux = (S==2) ? C: ’bz;Mux = (S==3) ? D: ’bz;


2007dce Net Declaration Assignment

• A continuous assignment can appear as part of a net declaration– Net declaration assignment

– It is a convenient form of declaring a net and then writing a continuous assignment

• Multiple net declaration assignments on the same net are not allowed

wire [3:0] Sum = 4’b0;wire Cout = 1’b0, Cin = ’b1;wire A_GT_A = A > B, B_GT_A = B > A;

wire Clear = ’b1;wire Clear;assign Clear = ’b1;

wire Clear = ’b1;wire Clear = Signal_From_Button;


2007dce

Quiet

Late

Ask

5 15

11

10 20

26

66

Delays

• For a vector net target, – if the RHS value goes from a non-zero value to a zero vector, fall delay

is used– if RHS value goes to z, turn-off delay is used– else rise delay is used

assign #4 Ask = Late;

assign #(rise, fall, turn-off) LHS_target = RHS_expression;

Late

Ask

5 20

17 26

44

138 2618

assign #6 Ask = Quiet || Late;

The latest value change is applied


2007dce Net Delays

• A delay can also be specified in a net declaration– Net delay

Assign delay

Assign delay

Driver 1

Driver 2

RHS expressionNet target Net delay

wire #5 Ask;

wire #5 Ask = Quiet || Late;

Assignment delay

Quiet

Late

Ask

10 30

17

20 40

47

assign #2 Ask = Quiet || Late;

77


2007dce Dataflow Modeling – Examples module MagnitudeComparator (A, B, AgtB, AeqB, AltB);parameter BUS = 8;parameter EQ_DELAY = 5; parameter LT_DELAY = 8;parameter GT_DELAY = 8;output AgtB, AeqB, AltB;input [1:BUS] A, B;

assign #GT_DELAY AgtB = A > B;assign #EQ_DELAY AeqB = A == B;assign #LT_DELAY AltB = A < B;

endmodule

module MS_DFF_RTL (D, C, Q, Qbar);output Q, Qbar;input D, C;

assign NotD = ~D;assign NotC = ~C;assign NotY = ~Y;

assign D1 = ~(D & C);assign D2 = ~(C & NotD);assign Y = ~(D1 & Ybar);assign Ybar = ~(Y & D2);assign Y1 = ~(Y & NotC);assign Y2 = ~(NotY & NotC);assign Q = ~(Qbar & Y1);assign Qbar = ~(Y2, Q);

endmodule


2007dce Outline




2007dce Behavioral Modeling

• Procedural Constructs• Timing Controls• Block Statement• Procedural Assignments• Conditional Statement• Case Statement• Loop Statement• Procedural Continuous Assignment


2007dce Procedural Constructs

• Two statements:– initial statement

• mainly used for initialization and waveform generation• executes only once• starts execution at time 0

– always statement• executes repeatedly• start execution at time 0

• Concurrent execution– Order of statements in a module is not important


2007dce initial Statement

• procedural_statement– procedural_assignment (blocking or non-blocking)– procedural_continuous_assignment– conditional_statement– case_statement– loop_statement– wait_statement– disable_statement– event_trigger– sequential_block– parallel_block– task_enable (user or system)

initial [timing_control] procedural_statement


2007dce initial Statement – Example

reg A;reg B;

initial A = ’b0;initial #2 B = ’b1;

parameter SIZE=1024;reg [7:0] RAM[0:SIZE-1];reg RibReg;

initialbegin: Seq_Blk_Ainteger index;

RibReg = 0;for (index=0; index<SIZE; index=index+1)RAM[index] = 0;

end

// waveform generationparameter DELAY=5;reg [7:0] Port_A;

initialbeginPort_A = ’hF2;#DELAY Port_A = ’hF2;#DELAY Port_A = ’h41;#DELAY Port_A = ’h0A;

end

’h20 ’hF2 ’h41 ’h0A0 5 10 15

Port_A


2007dce always Statement

always [timing_control] procedural_statement

always #5 Clk = ~Clk;// waveform on Clk of period 10

reg [3:0] Accum;reg [0:5] InstrReg;wire ExecuteCycle;

always @(ExecuteCycle) begincase (InstrReg[0:1])2’b00: Store(Accum, InstrReg[2:5]);2’b01: Load(Accum, InstrReg[2:5]);2’b10: Jump(InstrReg[2:5]);2’b11: ;

endcaseend

// Store, Load and Jump are user-defined tasks


2007dce always Statement – Example

module DFF (Clk, D, Set, Q, Qbar);input Clk, D, Set;output Q, Qbar;reg Q, Qbar;

always wait (Set==1) begin#3 Q = 1;#2 Qbar = 0;wait (Set==0);

end

always @(negedge Clk) beginif (Set != 1)begin#5 Q = D;#2 Qbar = ~Q;

endend

endmodule


2007dce Procedural Constructs – Example

module TestXorBehavior;reg Sa, Sb, Zeus;

initialbeginSa = 0;Sb = 0;#5 Sb = 1;#5 Sa = 1;#5 Sb = 0;

end

always @(Sa or Sb)Zeus = Sa ^ Sb;

always @(Zeus)$display (“At time %t, Sa = %d, Sb = %d, Zeus = %b”,

$time, Sa, Sb, Zeus); endmodule

Sa

Sb

Zeus5 10 150

At time 5, Sa = 0, Sb = 1, Zeus = 1At time 10, Sa = 1, Sb = 1, Zeus = 0At time 15, Sa = 1, Sb = 0, Zeus = 1


2007dce Timing Controls

• Timing control is of two forms– Delay control

• specifies the time duration from the time the statement is initially encountered to the time the statement executes (wait for delay before executing the statement)

– Event control• Statement executes based on events• two kinds of event control

– Edge-triggered event control– Level-sensitive event control


2007dce Delay Control

• The delay in the delay control can be an arbitrary expression– Explicit zero delay: the value of

the delay expression is 0

initialbegin#3 wave = ’b0111;#6 wave = ’b1100;#7 wave = ’b0000;

end

parameter ON_DELAY=3, OFF_DELAY=5;alwaysbegin#ON_DELAY; // wait for ON_DELAYRefClk = 0;#OFF_DELAY; // wait for OFF_DELAYRefClk = 1;

end

#Strobe compare = Tx ^ Mask;

#(PERIOD / 2)Clock = ~Clock;

#delay procedural_statement #delay;


2007dce Edge-triggered Event Control

@event ;

@(posedge Clock)Curr_State = Next_State;

@(posedge Clear or negedge Reset)Count = 0;

@Cla Zoo = Foo;

@event procedural_statement

time RiseEdge, OnDelay;

initialbegin// wait until positive edge on clock occurs@(posedge ClockA);RiseEdge = $time;// wait until negative edge on clock occurs@(negedge ClockA);OnDelay = $time - RiseEdge;$display(“The on-period of clock is %t”, OnDelay);

end

posedge negedge0→x 1→x0→z 1→z0→1 1→0x→1 x→0z→1 z→0


2007dce Level-sensitive Event Control

wait (condition) procedural_statement

wait (Sum > 22)Sum = 0;

wait (DataReady)Data = Bus;

wait (Preset);


2007dce Block Statement

• Mechanism to group two or more statements to act syntactically like a single statement– Sequential block (begin … end): statements are executed

sequentially in the given order– Parallel block (fork … join): statements execute

concurrently• A block can be labeled optionally

– If so labeled, registers can be declared locally within the block

– Block label provides a way to uniquely identify registers• A block can also be referenced

– It can be disabled using disable statement


2007dce Sequential Block

• A delay value in each statement is relative to the simulation time of the execution of the previous statement

// waveform generationbegin#2 Stream = 1;#5 Stream = 0;#3 Stream = 1;#4 Stream = 0;

end

begin[:block_id {declaration}]procedural_statement(s)

end

Stream

10 12 17 20 24

assume the sequential block get executed at time 10

beginPat = Mask | Mat;@ (negedge Clk)FF = & Pat;

end

begin: SEQ_BLKreg [0:3] Sat;

Sat = Mask & Data;FF = ^ Pat;

end


2007dce Parallel Block

• All statements within the parallel block must complete execution before control passes out of the block

fork[:block_id {declaration}]procedural_statement(s)

join// waveform generationbegin#2 Stream = 1;#5 Stream = 0;#3 Stream = 1;#4 Stream = 0;

end

Stream

10 12 14

assume the sequential block get executed at time 10

alwaysbegin: SEQ_A#4 Dry = 5;fork: PAR_A#6 Cun = 7;begin: SEQ_BExe = Box;#5 Jap = Exe;

end#2 Dop = 3;#4 Gos = 2;#8 Pas = 4;

join#8 Bax = 1;#6 $stop

end


2007dce Procedural Assignments

• Procedural assignment is an assignment within an initial statement or an always statement– used to assign to only a register data type– executes sequentially with respect to other statements that

appear around it

• 2 kinds of procedural assignment– blocking– non-blocking

always @(A or B or C or D)begin: AOIreg Temp1, Temp2;Temp1 = A & B;Temp2 = C & D;Temp1 = Temp1 | Temp2;Z = ~ Temp1;

end


2007dce Intra-statement Delay

• The RHS expression is evaluated before the delay, then the wait occurs and then the value is assigned to the LHS target

RHS_target = #delay RHS_expression;

Done = #5 ’b1; // intra-statement delay control

beginTemp = ’b1;#5 Done = Temp; // inter-statement delay control

end

Q = @(posedge Clk) D; // intra-statement event control

beginTemp = D;@(posedge Clk) // inter-statement event controlQ = Temp;

end


2007dce Blocking Procedural Assignment


2007dce Non-Blocking Procedural Assignment


2007dce Continuous Assignment vs.

Procedural AssignmentProcedural Assignment Continuous Assignment

Occurs inside an always statement or an initialstatement

Occurs within a module

Execution is with respect to other statements surrounding it

Executes concurrently with other statementsExecutes whenever there is a change of value in an operand on its RHS

Drives registers Drives netsUses “=“ or “<=“ assignment symbol Uses “=“ assignment symbolNo assign keyword (except in a procedural continuous assignment)

Uses assign keyword

module Procedural;reg A, B, Z;always @(B)beginZ = A;A = B;

endendmodule

module Continuous;wire A, B, Z;assign Z = A;assign A = B;

endmodule


2007dce Conditional Statement – if

if (condition_1)procedural_statement_1

{else if (condition_2)procedural_statement_2 }

[elseprocedural_statement_3 ]

Note that the condition expression must always be within parenthesis

module mux41 (sel, A, B, C, D, Y);input [1:0] sel; // 2-bit control signalinput A, B, C, D;output Y;reg Y; // target of assignment

always @(sel or A or B or C or D)if (sel == 2’b00) Y = A;else if (sel == 2’b01) Y = B;else if (sel == 2’b10) Y = C;else if (sel == 2’b11) Y = D;

endmodule

Simple 4-1 multiplexer


2007dce

module mux41 (sel, A, B, C, D, Y);input [1:0] sel; // 2-bit control signalinput A, B, C, D;output Y;reg Y; // target of assignment

always @(sel or A or B or C or D)if (sel[0] == 0)if (sel[1] == 0) Y = A;else Y = B;

elseif (sel[1] == 0) Y = C;else Y = D;

endmodule

if Statement – Example

Simple 4-1 multiplexer


2007dce case Statement

• The case expression is evaluated first• The case item expressions are evaluated and

compared in the order given (sequential execution)• Only first case that matches is executed (no break)• Multiple case item expressions need not be mutually-

exclusive• The x and z values are compared as their literal

values

case (case_expr)case_item_expr {, case_item_expr}: procedural_statement...[default: procedural_statement ]

endcase


2007dce case Statement – Examplesmodule mux41 (sel, A, B, C, D, Y);input [1:0] sel;input A, B, C, D;output Y;reg Y;

always @(sel or A or B or C or D)case (sel)2’b00: Y = A;2’b01: Y = B;2’b10: Y = C;2’b11: Y = D;

endcaseendmodule

Conditions tested intop to bottom order

module ALU (A, B, OpCode, Z);input [3:0] A, B;input [1:2] OpCode;output [7:0] Z;reg [7:0] Z;parameterADD_INSTR = 2’b10,SUB_INSTR = 2’b00,MUL_INSTR = 2’b01,DIV_INSTR = 2’b11;

always @(A or B or OpCode)case (OpCode)ADD_INSTR: Z = A + B;SUB_INSTR: Z = A - B;MUL_INSTR: Z = A * B;DIV_INSTR: Z = A / B;

endcaseendmodule

case (3’b101 << 2)3’b100: $display(“First branch taken”);4’b0100: $display(“Second branch taken”);5’b10100: $display(“Third branch taken”);default: $display(“Default branch taken”);

endcase


2007dce case Statement – Examples

// Simple binary encoder (input is 1-hot)module encode (A, Y);input [7:0] A; // 8-bit input vectoroutput [2:0] Y; // 3-bit encoded outputreg [2:0] Y; // target of assignment

always @(A)case (A)8’b00000001: Y = 0;8’b00000010: Y = 1;8’b00000100: Y = 2;8’b00001000: Y = 3;8’b00010000: Y = 4;8’b00100000: Y = 5;8’b01000000: Y = 6;8’b10000000: Y = 7;default: Y = 3’bX;// Don’t care when input is not 1-hot

endcaseendmodule

• Without the default case, this example would create a latch for Y

• Assigning X to a variable means synthesis is free to assign any value


2007dce case Statement – Examples

// Simple encoder (input is 1-hot)module encode (A, Y);input [7:0] A; // 8-bit input vectoroutput [2:0] Y; // 3-bit encoded outputreg [2:0] Y; // target of assignment

always @(A)case (1’b1) // synthesis parallel-caseA[0]: Y = 0;A[1]: Y = 1;A[2]: Y = 2;A[3]: Y = 3;A[4]: Y = 4;A[5]: Y = 5;A[6]: Y = 6;A[7]: Y = 7;default: Y = 3’bX;// Don’t care when input is not 1-hot

endcaseendmodule

• A priority encoder is more expensive than a simple encoder


2007dce Don’t-cares in case

• Different interpretation for x and z values– casez statement

• Like case, but the value z in the case expression and in any case item expression is considered as a don’t-case

– i.e. that bit is ignored

– casex statement• both the values x and z are considered as don’t-cares


2007dce

// Priority encodermodule encoder (A, valid, Y);input [7:0] A; // 8-bit input vectoroutput [2:0] Y; // 3-bit encoded outputoutput valid; // Asserted when an input is not all 0’sreg [2:0] Y; // target of assignmentreg valid;

always @(A) beginvalid = 1;casex (A)

8’bXXXXXXX1: Y = 0;8’bXXXXXX10: Y = 1;8’bXXXXX100: Y = 2;8’bXXXX1000: Y = 3;8’bXXX10000: Y = 4;8’bXX100000: Y = 5;8’bX1000000: Y = 6;8’b10000000: Y = 7;default: begin

valid = 0;Y = 3’bX; // Don’t care when input is all 0’s

endendcase

end // alwaysendmodule


2007dce Loop Statement

• 4 kinds of loop statements– Forever loop– Repeat loop– While loop– For loop


2007dce Forever-loop Statement

• This statement continuously executes the procedural statement

• To get out of such a loop, a disable statement may be used with the procedural statement

• Some form of timing controls must be used in the procedural statement

forever procedural_statement

initial begin

clock = 0;#5 forever

#10 clock = ~clock;end


2007dce Repeat-loop Statement

• The procedural statement is executed the specified number of times• If the loop count expression is an x or a z, the loop count is treated as a 0

repeat (loop_count)procedural_statement

repeat (count)sum = sum + 10;

repeat (ShiftBy)P_Reg = P_Reg << 1;

repeat (count) // repeat-loop statement@(posedge Clk) sum sum + 1;

sum = repeat (count) @(posedge Clk) sum + 1;// repeat event control

compute sum+1 first, then wait for count

positive edges on Clkthen assign to LHS

for count times, wait for positive edge of Clk and

when this occurs, increment sum

repeat (num_of_times) @(negedge clk);


2007dce While-loop Statement

• This loop executes the procedural statement until the specified condition becomes false.

• If the condition is an x or a z, it is treated as a 0 (false)

while (condition)procedural_statement

while (By > 0)beginAcc = Acc << 1;By = By -1;

end


2007dce For-loop Statement

• This loop repeats the execution of the procedural statement a certain number of times.

for (initial_assignment; condition; step_assignment)procedural_statement

integer K;for (K=0; K < MAX_RANGE; K = K + 1)beginif (ABus[K] == 0)ABus[K] = 1;

else if (ABus[K] == 1)ABus[K] = 0;

else$display(“Abus[%d] is an x or a z”, K);

end


2007dce Procedural Continuous Assignment

• Procedural continuous assignment is a procedural assignment– i.e. it can appear within an always statement or an initial statement– But, it is not a continuous assignment

• This assignment can override all other assignments to a net or a register– allows the expression in the assignment to be driven continuously into

a register or a net• 2 kinds of procedural continuous assignment

– assign and deassign procedural statement: these assign to registers– force and release procedural statement: these assign primarily to nets

(though they can also be used for registers)• The assign and force statements are “continuous” in the

sense that any change of operand in the RHS expression causes the assignment to be re-done while the assign or force is in effect

• Target cannot be a part-select or a bit-select of a register


2007dce assign – deassign

• An assign procedural statement overrides all procedural assignments to a register.• The deassign procedural statement ends the continuous assignment to a register• The value in the register is retained until assigned again.

module DFF (D, Clr, Clk, Q);input D, Clr, Clk; output Q; reg Q;

always @(Clr) begin

if (!Clr)assign Q = 0; // D has no effect on Q

elsedeassign Q;

end // always

always @(negedge Clk)Q = D;

endmodule

reg [3:0] Pest;...Pest = 0;...assign Pest = Hty ^ Mtu;...assign Pest = 2;// will deassign Pest and then assign...deassign Pest;// Pest continues to have value 2...assign Pest[2] = 1;// Error: ???

If an assign is applied to an already assigned register, it is deassigned first before making the new procedural continuous assignment.


2007dce force – release

• The force procedural statement on a net overrides all the drivers for the net until a release procedural statement is executed on that net.

• When applied to a register, the force statement causes the current value of the register to be overridden by the value of the force expression– When a release on a register is executed, the current value

is held in the register unless a procedural continuous assignment was already in effect (at the time the forcestatement was executed) in which case, the continuous assignment establishes the new value of the register.


2007dce force – release

wire Prt;...or #1 (Prt, Std, Dzx);

initialbeginforce Prt = Dzx & Std;#5;release Prt;

end

reg [2:0] Colt;...Colt = 2;force Colt = 1;...release Colt; // Colt retains 1...assign Colt = 5;...force Colt = 2;...release Colt;// Colt gets the value 5...force Colt[1:0] = 3;// Error: ???


2007dce A Handshake Example

• Registers can be used in interacting processes– It is not recommended to use registers declared within an always

statement to pass information between always statement • Example: interacting of a Receiver and a µProcessor

ReceiverAck

Data µProcessorClk

Serial_In

Ready

Parallel_Out


2007dce `timescale 1ns/100ps

module Interacting (Serial_In, Clk, Parallel_Out);input Serial_In, Clk; output [0:7] Parallel_Out; reg [0:7 Parallel_Out;reg Ready, Ack;wire [0:7] Data;

`include “Read_Word.v” // task Read_Word is defined in this filealwaysbegin: RXRead_Word(Serial_In, Clk, Data);// the task Read_Word reads the serial data on every clock cycle// and converts to a parallel data in signal Data.// It takes 10ns to do thisReady = 1;wait (Ack);Ready = 0;#40;

end

alwaysbegin: MP#25;Parallel_Out = Data;Ack = 1;#25 Ack = 0;wait (Ready);

end

endmodule


2007dce A Handshake Example

0 25 50 100 125 175

10 65 75 140 150

200

Receiver reading new serial data

Data output by µProcessor

Ready

Ack

alwaysbegin: RXRead_Word(Serial_In, Clk, Data);// It takes 10ns to do thisReady = 1;wait (Ack);Ready = 0;#40;

end

alwaysbegin: MP#25;Parallel_Out = Data;Ack = 1;#25 Ack = 0;wait (Ready);

end


2007dce Outline




2007dce Structural Modeling

• Module• Ports• Module Instantiation• External Ports


2007dce Module


2007dce Ports


2007dce External Ports


2007dce Outline




2007dce Advanced Topics

• Tasks• Functions• Systems Tasks and Functions• Disable Statement• Named Events• Mixed Structure with Behavior• Hierarchical Path Name• Sharing Tasks and Functions• Value Change Dump (VCD) File• Specify Block• Strengths• Race Conditions


2007dce Verification

• Writing a testbench• Waveform Generation• Reading Vectors from a Text File• Writing Vectors to a Text File

2006dce

End slide

introduction to verilog (dr. vu)

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