introduction to vhdl - sm.luth.se · pdf file• only a subset of the language is supported...

SMD098 Computation Structures Lecture 2 1

Introduction to VHDLIntroduction to VHDL

• VHSIC (Very High Speed Integrated Circuit) Hardware Description Language• Current standard is IEEE 1076-1993 (VHDL-93). Some tools still only support

VHDL-87. Tools used in the lab support VHDL-93

• ADA like syntax, strictly typed language, concurrent• Feature rich language for modeling digital systems at system level down to

gate level.• Only a subset of the language is supported for synthesis. Only RTL VHDL

code is synthesizable with most tools

• The goal with this course is not that you should learn the complete language. You should learn how to write RTL VHDL code, but also some behavioral “stuff” for test benches


Main language conceptsMain language concepts

• Concurrency– VHDL can describe activities that are happening in parallel

• Structure, hierarchy

– VHDL allows to structure a design in a hierarchical manner

• Sequential statements

– VHDL also allows sequential execution of statements. Just like any other programming language

• Time

– VHDL allows modeling of time


VHDL design unitsVHDL design units

• Entity declarationSpecifies the interface of an entity

• Architecture bodyDescribes the function of an entity. An entity can have more than one architectures.

• Configuration declarationUsed to bind entity statements to particular architecture bodies.

• Package declarationUsed to store a set of common declarations such as components, types, procedures and functions

• Package bodyUsed to store the definition of functions and procedures declared in the package declaration

entity Ent1 is

begin

end Ent1;

architecture A1 of Ex is

begin

end A;

architecture A2 of Ex is

begin

end A;

configuration CFG of Ent1 is

end CFG;

package PKG is

end PKG;

package body PKG is

end PKG;architecture A3 of Ex is

begin

end A3;

Common design data


The entity declarationThe entity declaration

A[3:0]

B[3:0]

Cin

Sum[3:0]

Cout

Adder

The entity specifies the interface of a design unit. May be seen as a “black box” description

library ieee; use ieee.std_logic_1164. all ;

entity Adder is port ( A, B : in std_ulogic_vector(3 downto 0); Cin : in std_ulogic; Sum : out std_ulogic_vector(3 downto 0); Cout : out std_ulogic); end Adder;

Entity name

Port signalname

Port mode Port type

Library statementand use clause


Port modesPort modesThree most often used port modes:

• in• out• inout

Mode in

Entity

S

Port signal

Driver

Mode out

Entity

Port signal

DriverS

Signal can not beread inside entity

Mode inout

Entity

Port signal

DriverS

Signal can beread inside entity

Driver

Mode out with internal signal I,The port signal S is assigned tothe internal Signal I

Entity

Port signal

DriverS

Signal I can beread inside entity

I

I


The architectureThe architecture

The architecture defines the contents of the “black box”

entity Adder is

end Adder;

architecture Demo of Adder is

begin

end Demo;

Entity name

Architecturename

Portdeclarations

Architecturedeclarations

Architecturebody


Modeling styles Modeling styles -- sequentialsequential

library ieee;use ieee.std_logic_1164.all;

entity eqcomp4 isport(A, B : in std_logic_vector(3 downto 0);Equals : out std_logic);

end eqcomp4;

architecture seq1 of eqcomp4 isbeginprocess(A, B)beginif A = B thenEquals <= ’1’;

elseEquals <= ’0’;

end if;end process;

end seq1;

architecture seq2 of eqcomp4 isbegin

process(A, B)begin

Equals <= ’0’;if A = B then

Equals <= ’1’;end if;

end process;end seq2;

If two architectures exist for one entity, the default architecture is used. The default architecture is the architecture that is compiled last. A configuration can explicatively specify which architecture to use. Read more about this in Zwolinsky chapter 3.8. You will use a configuration in the last lab.

A=B

A

BEquals


Modeling styles Modeling styles -- concurrentconcurrent

architecture concurrent of eqcomp4 isbegin

Equals <= ’1’ when (A = B) else ’0’;end concurrent;

architecture concurrent_bool of eqcomp4 isbegin

Equals <= not(A(0) xor B(0)) andnot(A(1) xor B(1)) andnot(A(2) xor B(2)) andnot(A(3) xor B(3));

end concurrent_bool;


Modeling styles Modeling styles -- structuralstructural

library ieee;use ieee.std_logic_1164.all;use work.gates.all; -- component declarations found in package gates

entity eqcomp4 isport(A, B : in std_logic_vector(3 downto 0);Equals : out std_logic);

end eqcomp4;

architecture structure of eqcomp4 issignal X : std_logic_vector(3 downto 0);

beginu0 : xnor2 port map(A => A(0), B => B(0), O => X(0));

u1 : xnor2 port map(A => A(1), B => B(1), O => X(1));



u4 : and4 port map(A => X(0), B => X(2), C => X(3), D => X(4), O => Equals);

end structure;


A simple example of a hierarchical/structural VHDL codeA simple example of a hierarchical/structural VHDL code

entity And2 isport (

A, B : in bit;Y : out bit);

end And2;

architecture Gate of And2 isbegin

Y <= A and B;end Gate;

entity Or2 isport (

A, B : in bit;Y : out bit);

end Or2;

architecture Gate of Or2 isbegin

Y <= A or B;end Gate;

File Or2.vhd File And2.vhd

We want to model the following and-or structure (Y = AB + CD)

First we create two VHDL files, containing the description of an or-gate and an and-gate. Name the files the same name as the name of the entity.


Example cont.Example cont.

Next we create a third file, the top-level in the hierarchy. The top-level instantiates the gate models.

A component declaration tells the compiler what each gate looks like

The signal declaration creates architecture internal signals

entity AndOr isport ( A, B, C, D : in bit;

Y : out bit);end AndOr;

architecture struct of AndOr is-- Component declarationscomponent Or2port ( A, B : in bit;

Y : out bit);end component;

component And2port ( A, B : in bit;

Y : out bit);end component;

signal A1, B1 : bit;

begin-- InstancesU1: And2 port map( A => A, B => B, Y => A1);

U2: And2 port map( A => C, B => D, Y => B1);

U3: Or2 port map( A => A1, B => B1, Y => Y);

end struct;

File AndOr.vhd

U2: And2 port map( A => C, B => D, Y => B1);

Create an instance named U2 of entity And2. Connect input A of U2 to input C of AndOr. Connect input B of U2 to input C of AndOr. Connect output Y of U2 to internal signal B1



A more compact way to instantiate entities is direct instantiation. With this approach there is no need for a component declaration (note that this is new for VHDL’93 and some tools may not support it)

Syntax is similar to the previous instantiation, the keyword entity is added and the full name of the library path where the instantiated component can be found.



architecture struct of AndOr is

signal A1, B1 : bit;

begin-- Direct instantiationU1: entity work.And2(gate) port map( A => A, B => B, Y => A1);

U2: entity work.And2(gate)port map( A => C, B => D, Y => B1);

U3: entity work.And2(gate) port map( A => A1, B => B1, Y => Y);

end struct;

Modified file AndOr.vhd

U2: entity work.And2(gate)port map( A => C, B => D, Y => B1);

The library work is the current working library. gate is the architecture name.



But this is much simpler…



architecture struct of AndOr isbegin

Y <= (A and B) or (C and D);

end struct;


GenericsGenericslibrary ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;

entity Adder isgeneric (

Width : integer range 2 to 32 := 16);port (

A, B : in unsigned(Width-1 downto 0);Y : out unsigned(Width-1 downto 0));

end Adder;

architecture RTL of Adder isbegin

Y <= A + B;end RTL ;

A generic parameter may be used to pass a value of a specified type to an entity and its architecture.

Adder_1: Addergeneric map (Width => 22)port map (A => A, B => B, Y => Y);

The instantiation determines the value of the generic parameter. A configuration may also be used to specify generic parameters. If the parameter is not specified it will take its default value (16 in this case)


Signal assignments and delaysSignal assignments and delays

A signal may be assigned future values using the following construct

X <= ‘0’, ‘1’ after 1 ns, ‘0’ after 3 ns, ‘1’ after 8 ns, ‘0’ after 13 ns;

Y <= X after 4 ns;

This is an inertial delay – any pulse shorter than the delay is suppressed. A delay may specifically be defined as a transport delay where no pulses are suppressed.

Y <= transport X after 4 ns;


Delayed signal assignments are not synthesizable!Delayed signal assignments are not synthesizable!

Consider the following

Y <= ((A and B) or (C and D)) after 4 ns;

How can we before synthesis know the delay? Not possible! An estimate of the delay will be known after synthesis. Routing (wiring) delays will be known after place and route. Never model delays for synthesis! Delays are only suitable for simulation.

You may however think that the zero-delay model confusing when you look at the waveforms in simulation


ZeroZero--delay model delay model

Zero-delay Nonzero-delay


Concurrent statementsConcurrent statements

The architecture body contains concurrent statements. Sequentialstatements are not allowed in the architecture body.

Y

X

B

A


entity Test is port ( A, B : in std_logic; X, Y : out std_logic); end Test;

architecture Concurrent of Test is

begin

X <= A xor B;

with A select Y <= B when ’1’, ’Z’ when ’0’, ’-’ when others ;

end Concurrent;

Two concurrentstatements. Order is unimportant

Signal assignmentoperator

Covers all cases


Internal signalsInternal signals

Internal signals can be declared in the declarative region of the architecture

Int Y

X

BA


entity Test is port ( A, B : in std_logic; X, Y : out std_logic); end Test;

architecture Internal of Test is

signal Int : std_logic; begin

Int <= A xor B;

X <= not Int ;

Y <= Int and A;

end Internal;

Signaldeclaration

Internal signal can be read and beassigned new values.

X and Y is not readable!


Processes and sequential statementsProcesses and sequential statements

0

1

Y

X

BA

Sensitivity listProcess is activated whenever an event occurs on signal A or B

Process label

Statements in the process body are executed sequentially!

Process declarativeregion

Process body

-- signal declarations not allowed

library ieee;use ieee.std_logic_1164. all;

entity Test isport (A, B : in std_logic;X, Y : out std_logic);

end Test;

architecture Proc of Test is

begin

P1: process (A, B)

begin

if A = ’1’ and B = ’0’ thenX <= A;Y <= ’1’;

elseX <= B;Y <= ’0’;

end if;

end process P1;

end Proc;


Multiple processes interact concurrentlyMultiple processes interact concurrently

0

1

0

1

Y

X

BA

Process 1 Process 2

Each process execute its statements sequentially. Each process execute when there is an event on one of the signals on its sensitivity list. This may cause an event on another signal that triggers another process

library ieee;use ieee.std_logic_1164.all;

entity Test isport

( A, B : in std_logic;X, Y : out std_logic);

end Test;

architecture Proc of Test issignal Internal : std_logic;

begin

P1 : process (A, B)begin

if A = ’1’ and B = ’0’ thenX <= A; Internal <= ’0’;

elseX <= B; Internal <= ’1’;

end if;end process P1;

P2 : process (A, B, Internal)begin

if Internal = ’1’ thenY <= A;

elseY <= B;

end if;end process P2;

end Proc;


Concurrent vs. sequential executionConcurrent vs. sequential execution

?

A

B

C

D

Y C

DY

Resolution function

Synplify will report errors!Multiple non-tristate drivers for net Y

The signal is updated with the lastvalue assigned to it

architecture Concurrent of Test is begin Y <= A or B; Y <= C and D; end Concurrent;

architecture Sequential of Test is begin process (A, B, C, D) begin Y <= A or B; Y <= C and D; end process ; end Sequential;

A signal that is assigned to within a process is not updated until the process is suspended.


Sensitivity listsSensitivity lists

For a process that models combinational logic, the sensitivity list must be complete! All signals that are read (“inputs” to the process) must be in the sensitivity list.

What does this process model?

process(A)begin

Y <= A or B or C or D;end process;

Our synthesis tool Synplify will assume that the sensitivity list is complete. The function of the synthesized logic will not match the function of the VHDL model you simulated.


Event based simulationEvent based simulation

Delta

Time

SignalUpdate

ProcessExecution

Simulation delta cycle

Delta "time" is orthogonal to simulationtime

Advance in time when no moreprocesses are scheduled to executeat current simulation time


Simulation Simulation -- an examplean example

0 +0 0 0 0 0 U U U 0 +1 0 0 0 0 0 0 U 0 +2 0 0 0 0 0 0 0 5 +0 0 1 0 1 0 0 0 5 +1 0 1 0 1 1 1 0 5 +2 0 1 0 1 1 1 1 10 +0 1 1 1 1 1 1 1 10 +1 1 1 1 1 0 0 1 10 +2 1 1 1 1 0 0 0

t (ns) ∆ A B C D S1 S2 Y

AB

CD

Y

S1

S2

A’0’’0’ 5ns

B’0’’1’ 5ns

C’0’’0’ 5ns

D’0’’1’ 5ns

’1’ 10ns

’1’ 10ns

architecture sim of Test is

signal A, B, C, D : std_logic := ’0’; signal S1, S2, Y : std_logic; begin A <= ’0’ after 5 ns, ’1’ after 10 ns; B <= ’1’ after 5 ns; C <= ’0’ after 5 ns, ’1’ after 10 ns; D <= ’1’ after 5 ns; S1 <= A xor B; S2 <= C xor D; Y <= S1 and S2; end Sim;


Combinational feedback loops Combinational feedback loops

In a synchronous design combinational feedback loops “must” be avoided. (There are some rare exceptions though.)

AS

Assume S = 0 and A = 1.What will happen in simulation?Simulation will never advancein time!

S <= S xor A;


Data objects Data objects -- constantsconstants

A constant can hold a single value of a given type. Must be declared in package, entity, architecture or process declarative region. Can improve maintainability and readability of code.

constant Mult : std_logic_vector := “0001”; -- Opcode multiply

constant Width : integer := 12;


Data objects Data objects -- signalssignals

Holds a list of values, which include the current value, past value and a set of possible scheduled values that are to appear on the signal. Future values can be assigned to the signal using the signal assignment operator.

signal shiftReg : std_logic_vector(7 downto 0);

shiftreg <= shiftreg(6 downto 0) & Input;

May be assigned initial values when declared:

signal Count : std_logic_vector(3 downto 0) := “0101”;

But this is not meaningful for synthesis!

Signals can represent wires and memory holders.


Data objects Data objects -- variablesvariables

Can hold a single value of a given type, but different values can be assigned to the variable at different times using a variable assignment statement. A variable is locally declared in a process or subprograms and can only be used locally. Variables are more abstract compared to signals. Variable assignments are immediately and not scheduled.

variable ShiftReg : std_logic_vector(7 downto 0);

shíftreg := shiftreg(6 downto 0) & Input;

Use variable whenever possible since a variable uses less simulation resources than a signal. A beginner may however find working with signals easier.


Variables in processesVariables in processes

Variabledeclaration

A variable is declared inside the process and is not visible outside the process. A variable is updated immediately. Retains its value through the simulation

Y

D

C

BA

architecture Var of Test isbegin

process(A, B, C, D)variable Temp : std_logic;

begintemp := ’0’;temp := temp xor A;temp := temp xor B;temp := temp xor C;temp := temp xor D;Y <= temp;

end process;end Var;


Data objects Data objects -- filesfiles

Files are only useful for simulation. Obviously a file data object does not belong in synthesis.

You will learn more about files when you write your own test benches in future labs.

file StimFile: TEXT open read_mode is "stim.txt";

file ResultFile: TEXT open write_mode is “Result.txt";


Data types (some of them)Data types (some of them)

• Enumeration data type: Contains a set of user defined values

type MyBit is (’0’, ’1’);type Beer is (Pripps, Falcon, KeyBeer, Guiness);

• Integer data type: Defines a range of integer numbers. Default is a 32-bit integer

type Count is integer range 0 to 10;

• Array data type:

type MyBitVector is array (natural range <>) of Mybit;type MyByte is array (natural range 7 downto 0) of Mybit;

• Record data type:

type FloatType is recordSign : MyBit;Mantissa : MyBitVector(7 downto 0);Exponent : MyBitVector(15 downto 0);

end record;

• Subtype:

subtype Byte is std_ulogic_vector 7 downto 0;


Predefined typesPredefined typespackage STANDARD is type boolean is (false, true); type bit is (’0’, ’1’); type character is ( ASCII chars... ); type severity_level is (note, warning, error, failure); type integer is range -2147483648 to 2147483647; type real is range -1.0E308 to 1.0E308; type time is range -2147483647 to 2147483647 units fs; ps = 1000 fs; ns = 1000 ps; us = 1000 ns; ms = 1000 us; sec = 1000 ms; min = 60 sec; hr = 60 min; end units; subtype delay_length is time range 0 fs to time’high; impure function now return delay_length; subtype natural is integer range 0 to integer’high; subtype positive is integer range 1 to integer’high; type string is array (positive range <>) of character; type bit_vector is array (natural range <>) of bit; type file_open_kind is ( read_mode, write_mode, append_mode); type file_open_status is ( open_ok, status_error, name_error, mode_error); attribute foreign : string;end STANDARD;

What types are meaningfulfor synthesis?


AttributesAttributesThere are many predefined attributes defined in VHDL. Not all can be used for synthesis. Attributes not supported for synthesis either relate to timing or are not necessary to model the physical structure of logic.

Some attributes useful for synthesis:

clock’event returns true if an event occurred on the signal clock

signal A : unsigned(3 downto 0)

A’left returns 3A’right returns 0A’range returns 3 downto 0A’length returns 4


The The std_logic_1164std_logic_1164 packagepackage

The predefined type bit is defined as

Can not model, high impedance, don’t cares etc. So in std_logic_1164 a new type, std_ulogic, is defined:

type std_ulogic is ( ’U’, -- Uninitialized ’X’, -- Forcing Unknown ’0’, -- Forcing 0 ’1’, -- Forcing 1 ’Z’, -- High Impedance ’W’, -- Weak Unknown ’L’, -- Weak 0 ’H’, -- Weak 1 ’-’ -- Don’t care );

type bit is (’0’, ’1’);

std_ulogic_vector is defined as

type std_ulogic_vector is array ( natural range <> ) of std_ulogic;


The resolved type The resolved type std_logicstd_logic

A signal that has multiple drivers must be of a resolved type. std_ulogic is not resolved but std_logic is a resolved type that is derived from std_ulogic. The resolved vector type is called std_logic_vector

---------------------------------------------------------| U X 0 1 Z W L H - | | ---------------------------------------------------------( ’U’, ’U’, ’U’, ’U’, ’U’, ’U’, ’U’, ’U’, ’U’ ), -- | U |( ’U’, ’X’, ’X’, ’X’, ’X’, ’X’, ’X’, ’X’, ’X’ ), -- | X |( ’U’, ’X’, ’0’, ’X’, ’0’, ’0’, ’0’, ’0’, ’X’ ), -- | 0 |( ’U’, ’X’, ’X’, ’1’, ’1’, ’1’, ’1’, ’1’, ’X’ ), -- | 1 |( ’U’, ’X’, ’0’, ’1’, ’Z’, ’W’, ’L’, ’H’, ’X’ ), -- | Z |( ’U’, ’X’, ’0’, ’1’, ’W’, ’W’, ’W’, ’W’, ’X’ ), -- | W |( ’U’, ’X’, ’0’, ’1’, ’L’, ’W’, ’L’, ’W’, ’X’ ), -- | L |( ’U’, ’X’, ’0’, ’1’, ’H’, ’W’, ’W’, ’H’, ’X’ ), -- | H |( ’U’, ’X’, ’X’, ’X’, ’X’, ’X’, ’X’, ’X’, ’X’ ) -- | - |

Resolution table for std_logic

Driver 1

Driver 2

’1’

’Z’

Resolution Function

’1’?


Functions in Functions in std_logic_1164std_logic_1164

A set of overloaded logic functions and conversion functions are defined in std_logic_1164. The logic functions are overloaded so they can be used for the std_logic and std_ulogic (and vector) types

Logic functions:and, nand, or, xor, xnor, not

Conversion functions:To_bit, To_bitvector, To_StdULogic, To_StdULogicVector, ToStdLogicVector

Also in the package, edge detecting functions:rising_edge() and falling_edge()

The std_logic_1164 package does not contain any functions for arithmetic operations


The The numeric_stdnumeric_std packagepackage

In the IEEE synthesis package, numeric_std, the types unsignedand signed are defined.

In the package a set of arithmetic functions are defined as well as conversion functions.

Both std_logic_1164 and numeric_std will be used in the labs. You will see examples in the first lab.

A “quick reference card” for the packages can be found at the course webpages.

type unsigned is array (natural range <>) of std_logic;type signed is array (natural range <>) of std_logic;


Type conversionsType conversions

Because VHDL is a strongly typed language type conversions are unavoidable. Closely related types may be converted using the syntax:

target_type_name(expr)

Types that are not closely related need a type conversion function

Closely related – contain same elements

architecture Y of X is

signal S : std_logic_vector(7 downto 0); signal A, B : unsigned(7 downto 0); signal MyInt : integer; begin

-- This will cause type error S <= B;

-- Type conversion, target is a std_logic_vector S <= std_logic_vector(A);

-- The ’+’ operator is defined for unsigned, -- signed and integer in numeric_std. -- A + B will result in unsiged since the -- operators are of unsigned type S <= std_logic_vector(A + B);

-- to_integer is a type conversion fucntion -- in numeric_std. Note that integer(A + B) -- will result in type error. MyInt <= to_integer(A + B);

-- The ’+’ operator is overloaded in -- numeric_std. A <= unsigned(S) + MyInt; end Y;


Assigning values to arraysAssigning values to arraysarchitecture assign of Examples is

signal Byte : std_logic_vector(7 downto 0) := "01010101";signal Word : std_logic_vector(15 downto 0);

beginByte <= "00001111";

Byte <= (’1’, ’0’, ’1’, ’0’, ’1’, ’0’, ’1’, ’0’);

Byte <= X"0F";

Byte <= (others => ’1’);

Byte <= (7 | 6 => ’1’,others => ’0’);

Byte <= (7 => ’1’,4 => ’1’,3 downto 1 => ’0’,others => ’0’);

Word <= X"FF" & Byte;

Word(15 downto 8) <= (others => Byte(7));Word(7 downto 0) <= Byte;

end Examples;

Initialization notsupported for synthesis

Sign extend (can be done with a single statement)

Concatenation

Positional association

Named association

Hexadecimal

introduction to vhdl - sm.luth.se · pdf file• only a subset of the language is supported...

Documents