Digital VLSI Design

• Full Automation

• Maximum benefit of scaling

• High speed ,

• low power

• Robustness

Design metrics

INVERTER

STATIC CHARACTERISTICS

VTC DESIGN ISSUES

• STATIC POWER CONSUMPTION

• FULL LOGIC LEVELS

• SHARP TRANSITION

• SWITCHING THRESHOLD→ NOISE MARGINS

PRACTICAL VTC

FIVE CRITICAL VOLTAGES

SWITCHING THRESHOLD

• Vth

• Output changes its state

Noise Margins

ImplementationResistive load

Design for Vol

SAT. ENHANCEMENT LOAD INV.

LIN. ENHANCEMENT LOAD INV.

Static characteristics

Operating regions

VOH

VOL

VIL

VIH

V th -switching threshold

Critical voltage

• Nothing

• We can design for wide noise margins

• Set Vth= ½Vdd

Why design for Vth≠ ½Vdd?

Choose appropriate VM

Velocity saturated device

CONSTANT

MOS

Long Channel Vs. Short Channel

SAME

Long Channel Vs. Short ChannelId vs Vgs

Sub-threshold current

Sub-threshold operation

Required----

For velocity saturated device

Estimation of NM USING Piecewise lin. approx.

Determine g at Vin~Vm

Variation in VM by (w/L)

Impact Of Device Variations on Vm

Critical voltage

• Nothing

• We can design for wide noise margins

• Set Vth= ½Vdd

Why design for Vth≠ ½Vdd?

Choose appropriate VM

Effect on kR

Reducing supply voltage

Switching characteristics

Delay Definitions-with input slope

Vout

tf

tpHL tpLH

tr

t

Vin

t

90%

10%

50%

50%

Capacitive load

Cgd

Cdb under transient conditions

Equivalence factor

m= ½ for abrupt junction

Clock (Charge) feedthrough effect

Delay calculationmethod 1

CMOS Inverter Driving a Lumped Capacitance Load

• CMOS Inverter can be viewed as a single transistor either charging the Cload or discharging the Cload– Vin is assumed to switch abruptly– If Vin switches high, the NMOS Tx

discharges Cload while the PMOS Tx turns OFF

– If Vin switches low, the PMOS Tx charges Cload while the NMOS Tx turns OFF

• Cload is comprised of– Cgate due to the gate capacitance

of receiving circuits– Cwire of the interconnect metal– Cparasitics of the inverter output

junctions

Switch Model of CMOS TransistorMODEL-1

Ron

|VGS| < |VT||VGS| > |VT|

|VGS|

Approximate as a simple RC network where R is given as an equivalent resistance of the NMOS and PMOS devices and C is given as the total lumped Cload capacitance

CMOS Inverter: Transient ResponseSwitch model

VDD

Vout

Vin = VDD

Ron

CL

tpHL = f(Ron.CL)

= 0.69 RonCL

t

Vout

VDD

RonCL

1

0.5

ln(0.5)

0.36

Vout = VDD (1 – e –t / RON

CL

) Vout = VDD (e –t / RON

CL

)

Determination of Req

In velocity saturated device

Method 2

CMOS Inverter Propagation Delay(AVERAGE CURRENT THROUGH LOAD)

V DD

Vout

V in = V DD

C LIav

tpHL = C L (V50% -VDD)

Iav

tpLH = C L (V50%-VOL)

Iav

WHERE

Iav, HL = ½ [ic(VIN=VOH, VOUT= VOH)]+ ic(VIN=VOH, VOUT= V50%)]

Iav, LH = ½ [ic(VIN=VOL, VOUT= V50%)]+ ic(VIN=VOL, VOUT= VOL)]

• SIMPLE• Drawback-----neglects variation of cap. Load during the

entire transition

Method-3

Differential equation approach accurate

tpHL

tpLH

Impact of Rise Time on Delayt p

HL(n

sec

)

0.35

0.3

0.25

0.2

0.15

trise (nsec)10.80.60.40.20

Input slope

0.25

or

Design for Performance-(speed)

• Keep capacitances small

• Increase transistor sizes– watch out for self-loading!

• Increase VDD

Delay as a function of VDD

0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.41

1.5

2

2.5

3

3.5

4

4.5

5

5.5

VDD

(V)

t p(nor

mal

ized

)

2 4 6 8 10 12 142

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

3.8x 10

-11

S

t p(sec

)

Device Sizing

(for fixed load)

Self-loading effect:Intrinsic capacitancesdominate

DELAY REDUCTION

Delay as a function of VDD(↑)

0

4

8

12

16

20

24

28

2.00 4.001.00 5.003.00

Nor

mal

ized

Del

ay

VDD (V)

Delay as a function of CL(↓)

DELAY α CL

Delay as a function of W/L(↑)

DELAY α (W/L)-1

85

Need of simple delay model

• Delay depends on many factors—charge, discharge, parasitic, w/L, fan in- fanout, topology

• Existing delay models do not give clear indication of contribution of each factor

• Circuit designers waste too much time simulating and tweaking circuits

86

Using LE in design of inverter chain

87

CKT DESIGN PROBLEMS

• Chip designers face a bewildering array of choices.

• What is the best circuit topology for a function?

• How large should the transistors be?

• How many stages of logic give least delay?

88

Need of simple delay model

• Circuit designers waste too much time simulating and tweaking circuits

• High speed logic designers need to know where time is going in their logic

• CAD engineers need to understand circuits to build better tools

89

Delay in a Logic Gate

90

Delay contributors

• τ is speed of basic transistor• p-intrinsic delay of the gate due to its

own internal capacitances• h—combines the effect of external

load with sizes of transistors• g– effect of circuit topology

91

Observations • Logical effort describes relative ability of gate

topology to deliver current [defined to be 1(best av. of charge and discharge both] for an inverter)

• Electrical effort is the ratio of output to input capacitance

• Delay increases with electrical effort

• Delay increases ---More complex gates have greater logical effort and parasitic delay

Estimation of

CMOS Ring Oscillator Circuit• An odd number of inverter circuits

connected serially with output brought back to input will be astable and can be used an an oscillator (called a ring oscillator)

• Ring oscillators are typically used to characterize a new technology as to its intrinsic device performance

• Frequency and stage are related as follows:

f = 1/T = 1/(2nP)

where n is the number of stages and

P is the stage delay

Ring Oscillator—COMPARING DIFFERENT TECHNOLOGIES

v0 v1 v5

v1 v2v0 v3 v4 v5

T = 2 t p N 2 N tp >> tf +tr

95

Computing Logical Effort

96

Different gates

97

Observations

• More complex gates have larger logical efforts

• Logical efforts grow with increase in no. of inputs

• Complex gates exhibit high g, greater delay

98

Parasitic delay

• It is fixed for a gate

• More complex gate—higher parasitic delay

• Ref. Pinv=1 (inverter parasitic delay )

• For other gates , parasitic delay is written in terms of pinv

99

Parasitic delay

100

How to compute Pinv

• For inv. g=1, dabs= τ(h+pinv)

• In a given tech., plot d vs. h

• Plot would be st. line with slope τ, & intercept- (pinv × τ)

• Pinv can be estimated after obtaining τ

• Draw similar plot for other gates

• Once τ is obtained , g and p of other gates can be found out.

101

Delay equation plot

Choice Of Standard Reference

103

Calculating delay of an inverter

Delay of 2 input Nand gate

Delay of 2 input NOR gate

Skewed Gates

Best WP/WN for min delay

other then un/up

Using logical effort

• Define three parameters for a gate• r = wp/wn = p/n

• γ= pull up path/ pull down path• μ= μ n / μ p

• r = k μ

Case---γ=μ=2 for inv.

108

Case---γ=2, μ=3

109

• Wp/Wn=P/N = r = kµ gives equal rise and fall delay

• γ=2; µ=2; k=1 for inv; k=1/2 for nand2, k=2 for Nor2

• γ=2; µ=3; k=2/3 for inv; k=1/3 for nand2, K=4/3 for Nor2

• For inv.----• Delay α RC

• Delay α μn (1/Wn,p) (Wp+Wn)

• dd α (1/μn) (1/Wn) (Wp+Wn)

•

• du α (1/μp) (1+r)

Condition for minimum average delay

• ∂Av

∂r

• For all gates

=0

EE141 112

Optimum NMOS / PMOS ratio-rabaey

Smaller device size yields faster design

Symmetrical transient response

Cw> Cg chose w largeCw< Cg choose w small

MINIMUM POSSIBLE DELAY

Computing Intrinsic Transistor Capacitance

• Intrinsic PN junction capacitance of the driving circuit must be added to the load capacitance Cload

• Consider the inverter example at left:– Area and perimeter of the PMOS and

NMOS transistors are calculated from the layout and inserted into the circuit model

• NMOS drain area = Wn x Ddrain

• PMOS drain area = Wp x Ddrain

• NMOS drain perimeter = 2 (Wn + Ddrain)

• PMOS drain perimeter = 2 (Wp + Ddrain)

• SPICE simulations were done (bottom left) for a fixed extrinsic load of 100fF with increasing transistor width (Wp/Wn = 2.75)

– Results show diminishing returns beyond a certain Wn (say about 6 um) due to effect of the increasing drain capacitance on the overall capacitive load

MINIMUM DELAY ~ ZERO DELAY

R= Wp/Wn

Non zero value

Area x Delay Figure of Merit• Increasing device width shows

diminishing returns on propagation delay time

• Define a figure of merit as area x delay for the inverter circuit

– Increasing device width Wn shows a minimum in area x delay product

• Unconstrained increase in transistor width in order to improve circuit delay is often a poor tradeoff due to the high cost of silicon real estate on the wafer!!

Design a chain of inv. for min delay

T-network Delay Model Of wire

• Star-delta-transformation• Vout=ZBC/(ZAB+ZBC)• Vout=[(2/RC)/(S+2/RC)]*(1/S)• =(1/s)-1/(s+2/RC)• =U(t)[1-exp(-2/RC)t]• FOR V50% delay• tp=(RC ln2)/2=0.35 RC

Delay in the presence of long wires

Design Of Inverter Chain

For Min. Delay

EE141 126

Sizing a path for minimum delay

EE141 127

Branching effort along a path

Where BH is

→ Used for sizing for delay

EE141 128

Observations regarding F

• F depends on only topology and loading

• F is Indep. of transistor sizes

• F is unchanged if inverters are added or removed

EE141 129

Path Delay D

• Sum of delay of all stages

EE141 130

Condition for min. path delay

EE141 131

On Differentiation:

EE141 132

Thus, minimum stage effort of each stage reqd. for min. delay along a path is

Thus, minimum delay achievable along a path is

We shd. choose transistor sizes such that stage effort is same for all blocks

EE141 133

Example

Compute for each stage

Apply capacitance transformation backwards

i

Chain Of Inverters

C2C1

Ci

CL

1 u u2 uN-1

In Out

uopt = e

135

Optimizing no of stages in a path for min. delay

EE141136

To find optimum N

If pinv = 0,

137

For Ň stages in chain with invertersBest delay per stage , d = gh + pinv

d = ρ + pinv

EE141138

Graphical solAs pinv grows, adding inverters become less advantageous

Chain Of Inverters— BEST NO OF STAGES

C2C1

Ci

CL

1 u u2 uN-1

In Out

uopt = e

Chain Of Inverters— BEST NO OF STAGES

C2C1

Ci

CL

1 u u2 uN-1

In Out

uopt = e

gu= gav x [2 µ / (γ+μ)]

gd= gav x [2 γ / (γ+μ)]

141

For large N, delay expression-

For ρ = 4 Ď = log 4F X FO4

142

Where FO4 = fanout of 4 inverter delay

HERE ρ = gh = 1 x 4 = 4; so d = 5τ

Thus for ρ = 4 Ď = log 4F X FO4 inverter delay

FO4 DELAY

143

144

Wrong no of stages

EE141145

146

Wrong size, L=1

Mis-sized

Ρ=4Ρ=4/ sΡ= 4s

W 4sW 16 W

C=1C=4s

C=16

D = ∑gh + ∑pinv

= (4s + 4/s + 4 ) + 3 pinv

= 15 units (s=1)

EE141147

Power dissipation

Why worry about power?-- Heat Dissipation

DEC 21164

microprocessor power dissipation

Why worry about power — Portability

Multimedia Terminals

Laptop Computers

Digital Cellular Telephony

BATTERY(40+ lbs)

Year

Nom

inal

Cap

acity

(W

att-

hour

s / l

b)

Nickel-Cadium

Ni-Metal Hydride

65 70 75 80 85 90 95 0

10

20

30

40

50

Rechargable Lithium

Expected Battery Lifetime increaseover next 5 years: 30-40%

Where Does Power Go in CMOS?

• STATIC POWER---NIL

• Dynamic Power Consumption

• Short Circuit Currents

• Leakage

Charging and Discharging Capacitors

Short Circuit Path between Supply Rails during Switching

Leaking diodes and transistors

Power consumption

• 4 components

Static power consumptionShort circuit power consumptionLeakage power consumptionDynamic power consumption

• The total power in a CMOS circuit is given by Ptotal = Pd + Psc + Ps where

Pd is the dynamic average power (previous chart), Psc is the short circuit power, and Ps is the static power due to ratio circuit current,

junction leakage, and sub-threshold Ioff leakage current

• Short circuit current flows during the brief transient when the pull down and pull up devices both conduct at the same time where one (or both) of the devices are in saturation

Static power consumption

Short circuit power

CMOS Short-Circuit Power DissipationDerivation

Short Circuit Path

Modelling

t1- t2, Mos operates in saturation

At t2, current reaches its maximum valueAt this point vin=vdd/2, because inverter is symmetrical

I mean= 2x [2/T] x ∫Isat dt : Limits(t1, t2)

Conditions—Vin(t)=(Vdd/τ) t; --assume vin increases linearly with time

tr = tf = trf

Psc = (/12) (Vdd – 2Vt)3 (trf/tpin)

• For a balanced CMOS inverter with n=p= , and Vtn = |Vtp|, the short circuit power can be expressed by

Psc = (/12)(Vdd – 2Vt)3 (tr/f/tpin)

where tpin is the period of the input waveform and trf is the input rise time (or fall time) tr = tf = trf

Effect of load cap on short circuit power

• P short circuit reduces

• Reason---- output start switching after input has completely stabilized

Effect of Cload

Dynamic energy consumption

Energy stored across capacitor

Dynamic power consumption-derivation

Average Dynamic Power in CMOS Inverter

• Average dynamic power derivation:– On negative going input, pull-up

device charges the load capacitance. On positive going input, pull-down device discharges the load into ground.

– Average power given by

Pave = (1/T)CL (dvout/dt) (Vdd – vout)dt + (1/T)(-1) CL (dvout/dt) vout dt where the first integral is taken from 0 to T/2 and the second integral is from T/2 to T

• completion of the integral yields

Pave = CL Vdd2 f where f = 1/T

• Note that the dynamic power is independent of the typical device parameters, but is simply a function of power supply, load capacitance and frequency of the switching!

Vin Vout

CL

Energy/transition = CL * Vdd2

Power = Energy/transition * f = CL * Vdd2 * f

Need to reduce CL, Vdd, and f to reduce power.

Vdd

Not a function of transistor sizes!

Reduce power consumption

• Reduce Vdd• Reduce swing at the output• Reduce CL

• Reduce Switching activity

To keep same speed, can we reduce Vdd, increase (w/L)? No

Inc in W inc in CL

Dynamic Power Consumption - Revisited

Power = Energy/transition * transition rate

= CL * Vdd2 * f0 1

= CL * Vdd2 * P0 1* f

= CEFF * Vdd2 * f

Power Dissipation is Data DependentFunction of Switching Activity

CEFF = Effective Capacitance = CL * P0 1

Power Consumption is Data Dependentuniform distribution of inputs

Example: Static 2 Input NOR Gate

Assume:P(A=1) = 1/2P(B=1) = 1/2

P(Out=1) = 1/4P(01)

= 3/4 1/4 = 3/16

Then:

= P(Out=0).P(Out=1)

CEFF = 3/16 * CL

Transition Probabilities for Basic Gates Non-uniform distribution of inputs

No feedback

Power consumption—Correlated signals

½1

Sizing for min. power consumption

For a given delay constraint

Sizing for power consumption

Vdd=Vddref

Vdd=Vddref

Vdd≠ Vddref

Graphical solution

Why energy reduces for F increasing?• Assume delay reqd is tpref=5ns.

• As F inc CL inc. delay (tp) inc. and dyn. energy inc. linearly

• But as f inc delay reduces exponentially, energy inc.• for F= 1 delay is already small and close to tpref). Inc in f

does not cause much reduction rather energy increment is more

• For F large, delay and energy are large values• Hence as f inc., delay reduces drastically (become less than

tpref ). Hence to have given delay= tpref, energy is dec. which inc. delay to tpref.

• As f is increased further, delay reduction reduces, only energy increases

Design example—0.25um technology, find f, Vdd for tpref=0.2ns. Cext=10Cg1, γ=1, Vref=2.5v

Design a chain of inv for min delay, min energy

Power delay product

Indicates that energy required 0 for Vdd 0 erroneous

Energy delay product

Shd. Be minimum

Energy delay productoptimum Vdd

Combinational logic

STATIC CMOS GATES

asynchronous design

Can Be Made Synchronous By Inserting Latches in between

Design Styles Full Static CMOS or complementary logic

NAND NOR

XOR/ XNOR

DRAWBACK

complementary signals are required

F = D + A. (B+C)

static CMOS gateVTC--Input data dependent

Tphl--Delay computation –NANDstate of intermediate nodes matter --worst case

Drawback of static cmos

• 2N devices required

• Prop delay inc with increase in fanin because of inc in Cint, large series chain

Uniform transistor sizing

• For the gate, Find equivalent inverter model

• Find the required transistor w/L

• Hence estimate w/L of each transistor

Influence of fan-in / fanout on propagation delay

Other delay reduction techniques

• Progressive transistor sizing

• Input reordering

• Logic restructuring

Reduce power consumption

Reduce switching activity

Power consumption due to glitches

Power reduction—balanced signal path for glitch reduction

Logic restructuring for lowering switching activity

Power reduction- Input reordering affects

Power reduction- Time multiplexing of resources—area reduces, activity increases

Very low switching activity Very high switching activity as bus toggles between 0 and 1

Other design styles--Pseudo NMOS

DCVSL

Xor/ XnorADVANTAGE---TRANSISTOR SHARING

DCVSL is advantageous for full adder implementationThen static CMOS

NAND/ AND

Adder

USE OF LOGICAL EFFORT MODEL

GENERAL PATH

223

224

Transistor sizes

All stages shd have same sizesC = n W L Cox; n is a non zero no.Each stage load = 3 (w l) CoxL=min size

225

Transistor sizes• Inverter load at the input = (2pmos+1nmos) gate load

• [Wnmos + Wpmos ]Lmin Cox

• or

• [Wnmos + 2Wnmos ]Lmin Cox

• Here

• Cz=C = [Wnmos + Wpmos ]Lmin Cox

• In a given tech., L is fixed, say 1um

• We take 1Cg= Wmin Lmin Cox

• If C= 100Cg; then Wpmos= Wnmos = ½100 Wmin

EE141 226

Ca = Cb = [Wnmos + Wpmos ]Lmin Cox

Driving Large Capacitances-use LE

VDD

Vin Vout

CL

tpHL = CL Vswing/2

Iav

Transistor

Sizing

Using Cascaded Buffers

C2C1

Ci

CL

1 u u2 uN-1

In Out

uopt = e

design• Determine N, u(=ρ)• cL=un+1 cg

• (n+1)=ln (cL/cg) / ln(u)• Delay=τo (cd+u cg) / (cd+cg) • Delay total = (n+1) τo [(cd+u cg) / (cd+cg)]• Delay total= [ln (cL/cg) / ln(u) ]• * τo [(cd+u cg) / (cd+cg)]• u(ln u-1) = (cd/cg) ~0

• U= e

Other logic design styles

Switch logic