ItalianWorkshoponSPICA Rome,INAFHQ4-5Apr2016

INAF– IAPS,Rome111

1. InstrumentControlUnit:• DPU&OBS(IAPS)• ICUBoxandbackplane (nationalindustry +IAPS)• PowerSupplyUnit(nationalindustry +IAPS)• testsandIntegration ofthe ICU

• MCU(MechanismsControlUnit,NL+B),CCU(CoolerControlUnit,F)e DPU (nationalindustry +IAPS)

1. LNA(LowNoiseAmplifiers) (nationalindustry+IAPS)

2. Participation totheICC (InstrumentControlCenter)IAPS-OABO-UniPD

3. ParticipationtothesteeringcommitteeoftheSAFARIConsortium

4. ResponsibilityofthecoordinationoftheGalaxyevolutionWorkingGroupintheSAFARIscienceTeam

5. Participation totheScienceTeamIAPS-OABO-UniPD-UniBO• TwoitalianCoIs:L.Spinoglio &C.Gruppioni• Scienceassociates:A.Franceschini,F.Pozzi,plusmanyothersinvolvedintheM5

proposalpreparation

TheItalianparticipationtoSAFARI-SPICAiscoordinatedbyIAPS- INAF

ItalianWorkshoponSPICA Rome,INAFHQ4-5Apr2016

INAF– IAPS,Rome2

SAFARIICU DPUOBS

AnnaMariaDiGiorgio,RiccardoCerulliIrelli,RenatoOrfei,DavidBiondi,JohnS.Liu,StefanoPezzuto,GiovanniGiusi

INAFIAPSRomeItaly

M.Viterbini,F.Cairo,CNRISACLorenzoPiazzo,Univ.Roma“LaSapienza”

Bortolino Saggin,PolitecnicoMilano

ICUwillinclude:-DPUtoimplement theInstrumentcontrolanddatahandlingfunctionalities- PSUpowersupplyunittoprovidesecondarypowertotheotherwarmelectronicunits- MCUmechanismscontrolunit(mirrors andwheelscontrol)- CCUcoolercontrolunit(instrument thermalmonitorandcontrol)

-OnlyDPUandPSUwillbesuppliedbyItaly+SAFARIOnBoardSoftware(OBS)

ItalianWorkshoponSPICA Rome,INAFHQ4-5Apr2016

INAF– IAPS,Rome3

AeroflexUT699Leon3-FTprocessor:- 4integratedSpWports, twoofwhichsupporting RMAP- 53MIPSat66MHzclockfrequency:WARNING:canbeinsufficient ifsciencedataratesfromDCUhighlyexceed4Mbits/s(=>compressionalgorithmwithaCPUloadgreaterthan20-30MIPS)

AtmelAT7910SpWRouterconnected totheexternalSpWlinksand toLeonprocessor-TimeCodesfromSPICAnetworkautomaticallypropagated toalltheSafariunits,asrequired bytheinternal synchronizationscheme- non-blocking crossbarswitchconnecting anyinput port toanyoutput port- the8thSpWport oftheRoutercanprovideasecondconnection toCDMU(ifcrossedstrapping required)orathirdconnection to theLeon (toimprovebandwidth)

SmallcapacityActelFPGAtoimplementadditional logic:- control signalsfor subsystemsswitchON/OFF- DPUboard HWmonitoringfunctions- DPUboard reset(TBC)

Estimatedmemoryrequirements:- PROM:256kB- EEPROM:3MB- SRAM:40MB(32+8forEDACredundancy)

DPUHighlevelarchitecture

CDMU

ItalianWorkshoponSPICA Rome,INAFHQ4-5Apr2016

INAF– IAPS,Rome44

DPU On Board Software

•Telemetry and Telecommand exchange with the S/C

•Instrument Commanding, based on the received and interpreted TCs, in agreement with the current instrument operating mode

•Instrument monitoring and control, based on the Housekeeping data (HK) acquired from the other instrument units

•Detectors readout data acquisition, pre-processing and formatting according to the selected Telemetry protocol

• On board time management and synchronization of all the instrument activities

•On board Memories management

ItalianWorkshoponSPICA Rome,INAFHQ4-5Apr2016

INAF– IAPS,Rome5

SAFARILNA

AnnaMariaDiGiorgio,RiccardoCerulliIrelli,RenatoOrfei,DavidBiondi,JohnS.Liu,StefanoPezzuto,GiovanniGiusi

INAFIAPSRomeItaly

M.Viterbini,F.Cairo,CNRISACLorenzoPiazzo,Univ.Roma“LaSapienza”

Bortolino Saggin,PolitecnicoMilano

ItalianWorkshoponSPICA Rome,INAFHQ4-5Apr2016

INAF– IAPS,Rome6

Firstprototypeandpreliminarytest(TAS-I,Milano,INAF/IAPS,CNR/IFN)Main requirements to be satisfied at 135 K are:BW: DC to 3 MHzGAIN: 20 V/VNOISE: < 3nV/sqrt(Hz) (< 1nV/sqrt(Hz) as goal)POWER: < 2 mW/channel (goal), 5 mW/channel MAX

SinglechannelLNAinterfaces,whosecoreistheINFINEONBFP650HeteroJunctionSi:Ge.

Frequency response fromDCto10MHzatTroom andatlowpower(~1mW).The-3dBpoint inthiscondition isaround4

MHz. G~25V/V

The-3dBpointinthiscondition is1.4MHzLimited BWduetothesetup

ItalianWorkshoponSPICA Rome,INAFHQ4-5Apr2016

INAF– IAPS,Rome7

Newprototype:LNA2016• ReconfigurablePCBallowingtestofalternativeconfigurations• Improved4-layerlayoutwithguardingofsensitivenodes• FulldifferentialInput-Output• Cascode inputstagetoallowlargerbandwidth• Assembledwithprovencryo-compatibleEEEparts

Testboxduringassembly(March2016)

overallschematics

Prototype layout