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iiWave Systems TechnologiesWave Systems Technologies

Video IP Cores & SolutionsVideo IP Cores & Solutions&&&&

Case Study “Image Capture / Display”Case Study “Image Capture / Display”Based on “WLAN 802.11b/g”Based on “WLAN 802.11b/g”

iWave Systems Technologies

Agenda

Video IPs List

iWave Image Capture / Display Solution Case study

Sample ApplicationsSample Applications

Block Diagram

Feat resFeatures

FPGA Blocks Description

What we offer

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iWave...Video IPs List

iW-LCD Interface

iW Vid S liW-Video Scalar

iW-Color Space Converter

iW Chroma ResampleriW-Chroma Resampler

iW-Video DeInterlacer

iW-Alpha BlenderiW Alpha Blender

iW-Camera Interface

iW-Video Encoder Interface

iW-Video Decoder Interface

iW-Image Rotation

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Few Sample Applications

Rear View CameraDash Board Display

Security SurveillanceCamera

Car Rear SeatEntertainment


Case Study... Block Diagram

SDRAM

DigitalDisplay

SDRAM

VideoEncoder

AnalogDisplay

SDIO WLANModuleDigital

Sensor

FPGASDIO

RGB / YCrCb

YUV

AnalogSensor

StereoAUDIODVD Pl

VideoDecoder

Stereo Codec

AUDIOPlayer


Case Study... Features

Analog / DigitalCamera

Analog / DigitalCamera FPGAFPGA SDIO WLAN

TransmitterSDIO WLANTransmitter FPGAFPGA Analog / Digital

DisplayAnalog / Digital

DisplaySDIO WLAN

ReceiverSDIO WLAN

Receiver

Board takes analog/digital camera input & displays the image on analog/digital

CameraCamera TransmitterTransmitter DisplayDisplayReceiverReceiver

Board takes analog/digital camera input & displays the image on analog/digital LCD

Camera input to one board & display output from the second board

WiFi communication using Marvell WiFi 88W8688 Chipset

SDIO Interface between FPGA & processor, with SDIO controller implemented in FPGAin FPGA

JPEG Encoder/Decoder implemented in FPGA

Audio & single board camera/display loop back option to support DVD playerAudio & single board camera/display loop back option to support DVD player

Cont..iWave Systems Technologies


Camera Transmit Data path :

Camera interface logic is built in the FPGA.Th NTSC i t l d l h l i d f A l I i

DVD Player Transmit Data path :

The NTSC interlaced analog channel received from Analog Image sensor isdigitized by an ADC and sent to FPGA for capture and further processing.

DVD Player Transmit Data path :

The DVD Player generates NTSC streams which are digitized by an Analogto Digital Converter.

ADC converts standard analog baseband television signals compatible withADC converts standard analog baseband television signals compatible withNTSC standards into 4:2:2 component video data compatible with ITU-RBT.601 standard.

These are then delivered to Camera interface built in the FPGA for captureThese are then delivered to Camera interface built in the FPGA for captureand further processing.

The RCA jack used for the Analog Image Sensor is used to incur the NTSCvideo interface from DVD Player.

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y

Cont..iWave Systems Technologies


WiFi Interface with Video ADC :

ADC converts standard analog baseband television signals compatible withld id NTSC i t 4 2 2 t id d t tibl ith th 8 bitworldwide NTSC into 4:2:2 component video data compatible with the 8-bit

ITU-R BT.601 (YCrCb) interface standard.NTSC Interlaced Video received from Analog Image sensor or DVD monitor

are given to ADC to digitize into YUV formats which is then sent to Cameraare given to ADC to digitize into YUV formats which is then sent to Camerainterface reside in the FPGA.FPGA Interface with Digital Image Sensor :

The Digital Image sensors built with integrated ADC generates YUV/RGBsignals.

These are then sent via Camera interface in the FPGA for capture and furtherprocessing. The Digital image sensor has an image array capable of operatingat up to 60 fps in VGA with complete user control over image quality,formatting and output data transfer.

8Cont..iWave Systems Technologies


WiFi Interface with Digital Image Sensor :

Digital image sensor supports an image array capable of operating at up to 60f i VGA ith l t t l i lit f tti d

WiFi Interface with FPGA :

fps in VGA with complete user control over image quality, formatting andoutput data transfer.

WLAN Module supports a SDIO device that allows a host controller usingthe SDIO bus protocol to access the WLAN device.

WLAN Module acts as the device on the SDIO bus FPGA can accessWLAN Module acts as the device on the SDIO bus. FPGA can accessregisters of SDIO interface directly and can access the shared memory in thedevice.FPGA Interface with SDRAM :FPGA Interface with SDRAM :

The SDRAM is used for the Frame buffering in FPGA.The device is configured in 1 meg x 32 x 4 banks.

9Cont..

Supports 12 rows (A0-A11) and 8 column addressing (A0-A7). It is availablewith CAS latency 3 with 143 MHz clock frequency.



FPGA Interface with Digital Display :

The LCD Controller in the FPGA supports RGB 8:8:8, RGB 6:6:6, RGB5 6 5 RGB 5 5 5 d RGB 4 4 4 d f5:6:5, RGB 5:5:5 and RGB 4:4:4 data formats.

Connector is used for the module electronic interface.

WiFi Interface with Video DAC :WiFi Interface with Video DAC :

The DAC provides the support for composite (CVBS) analog outputs instandard-definition (SD) format.

WiFi Interface with Stereo CODEC :

Low power audio codec offers a combination of high quality audio andadvanced features for digital audio applicationsadvanced features for digital audio applications.

Has three flexible stereo analog input channels which can be configured asline inputs, differential microphone inputs or single ended microphone inputs.

10Cont..iWave Systems Technologies


WiFi Interface with DVD Player :

WiFi UART is supported to control the DVD Player.A St d d D b 9 f l t i id d th b dA Standard D-sub 9 female connector is provided on the board.The WiFi UART TXD for Transmit, RXD for Receive, RTS and CTS lines

for hardware flow control were supported.

Analog Display Receiver Data path :

The LCD controller in the FPGA supports 16 bit YCrCb/RGB 8:8:8 formats.The DAC accepts 16 Bit YCrCb data received from FPGA and converts intoThe DAC accepts 16 Bit YCrCb data received from FPGA and converts into

Composite (CVBS) analog output. This will be sent to DVD Monitor tovisualize the image.

The RCA connector used for the CRT monitor will be used to interconnectThe RCA connector used for the CRT monitor will be used to interconnectDVD monitor.

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FPGA – Block Diagram

Wrapper

DPRAMDPRAM

SDIO 2.0Host

SDIO 2.0Host

CameraCaptureInterface

CameraCaptureInterface

RBC&

JPEGEncoder

Framer/De-Framer

LCDInterface

SDRAMControllerSDRAM

ControllerJPEG

Decoder&

BRC


BRC

FPGA IP Cores

Camera Capture InterfaceInterfaces to a camera sensor and captures data.

LCD InterfaceLCD Interface The logic required to drive an LCD to display the image. Also the color conversion

and image scaling features.

JPEG Encoder (includes Raster-to-Block Converter)JPEG Encoder (includes Raster to Block Converter)A high-performance image encoder (licensed from 3rd party) that complies with

baseline ISO/IEC 10918-1 JPEG standard.

JPEG Decoder (includes Block-to-Raster Converter)JPEG Decoder (includes Block to Raster Converter)An image or video decoder (licensed from 3rd party) that complies with baseline

ISO/IEC 10918-1 JPEG standard.

SDIO Host Controller The SDIO host to initiate a command/data send and receive response/data between

the WLAN module and the imaging module.

SDRAM Controller Image buffer read/write from/to the SDRAM.


Setup - Image


Single Board - Image


What we offer

Image Capture / Display Turnkey solutionImage Capture / Display Turnkey solution

Using iWave’s Comprehensive, Proven, FPGA IPs

Total System Design, Ready to manufactureTotal System Design, Ready to manufacture

High performance / Optimized BOM

Customization services for the Board, FPGA and Embedded ,Software

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Thank YouThank You

For further info. : [email protected] further info. : [email protected] u e o. : g@ w vesys e s.coo u e o. : g@ w vesys e s.co


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