j warnock dac2011 14nm
DESCRIPTION
14 nm technologyTRANSCRIPT
1
IBM Systems and Technology Group
Circuit Design Challengesfor the
14nm Technology Node
Circuit Design Challengesfor the
14nm Technology Node
Jim Warnock
Special Session 26
DAC 2011
2 J. Warnock DAC 2011
OutlineOutline
Introduction
Classical CMOS Scaling: The End of the Road
New Device StructuresWhat do these structures mean for circuit designers?
Wire Interconnects
Reliability
Conclusions
3 J. Warnock DAC 2011
IntroductionIntroduction
14nm technology will pose many challenges, for many types of designs…
This talk will focus on:High-frequency digital CMOS design, ie for high-performance microprocessorsCircuits, wires, reliability, variability…
Many tough physical design issues (not covered here)
Lithography, manufacturing, yield, etc… (not covered here)
Why is 14nm so difficult?
What will designers (and design automation experts) be facing at the 14nm technology node?
4 J. Warnock DAC 2011
OutlineOutline
Introduction
Classical CMOS Scaling: The End of the Road
New Device StructuresWhat do these structures mean for circuit designers?
Wire Interconnects
Reliability
Conclusions
5 J. Warnock DAC 2011
0.1
1
0.01 0.1 1Feature pitch (microns)
Volta
ge (V
)CMOS Supply Voltage Scaling DifficultiesCMOS Supply Voltage Scaling Difficulties
Classical DennardScaling Regime
14nmRegime
Scaled voltage
High-performance voltage
Voltage“gap”
6 J. Warnock DAC 2011
Voltage Scaling DifficultiesVoltage Scaling Difficulties
“The End is Near…”Well, maybe not the end, but things are sure getting tough…
Voltage scaling for high-performance designs is limitedCan’t get much lower than ~ 1VLimited by leakage issues: can’t reduce threshold voltages
If only we had steeper sub-threshold slopes…Limited by variability, esp VT variability
If only we could get rid of random dopant fluctuations (RDF)…Limited by gate oxide thickness
Some relief from high-K materials (postpones the problem for a couple of generations)
Limited voltage scaling + decreasing feature sizes => Increasing electric fields
New device structures needed (short channel control)Reliability challenges (devices and wires)
7 J. Warnock DAC 2011
CMOS Power-performance ScalingCMOS Power-performance Scaling
When scalingwas good…
14nmRegime
Where this curve is flat, can only improve chip freq by: a) pushing core/chip to higher power density (tough these days…)b) design power efficiency improvements (low-hanging fruit all gone)
8 J. Warnock DAC 2011
CMOS Scaling to 14nm: NetCMOS Scaling to 14nm: Net
New device structures will appearOld ones just don’t scale any more…Need some way to push voltages AND VTs at least incrementally lower
Voltage “gap” will continue to increaseDelta between actual supply voltage and scaled valueReliability will be a key focus item
Continued focus on design power efficiency improvementspower frequency
9 J. Warnock DAC 2011
OutlineOutline
Introduction
Classical CMOS Scaling: The End of the Road
New Device StructuresWhat do these structures mean for circuit designers?
Wire Interconnects
Reliability
Conclusions
10 J. Warnock DAC 2011
New Device StructuresNew Device Structures
3D Device structuresTrigateFinFET
Radical 2D structuresExtremely thin SOI
What are the implications for circuit designers?
11 J. Warnock DAC 2011
Trigate/FinFET DevicesTrigate/FinFET Devices
The good news:Expect improved subthreshold slopeExpect improved RDF-induced variabilityAbove could help to enable lower voltage operation
What designers have to worry about:New sources of variability
Fin width will have a significant impact on VT: Expect global, local and random effects/correlationsFin height -> width variability: can’t amortize over wider fingers…
Some of the same old variability issues (continuing to worsen…)Gate line-edge roughening (LER), channel length variabilityMay be exacerbated by 3D effects
“Quantization” of device widthsCan only have integral numbers of fins
Changes in device parasitic R, C compared to usual expectationsG-S cap (Miller cap), S, D contact resistance
12 J. Warnock DAC 2011
0
50
100
σ[V
Tsat
], m
V
1/√ (number of fins)
nFET
pFET1 fin
20,10,5 fins2 fins
Trigate/FinFET Devices: VariabilityTrigate/FinFET Devices: VariabilityReduced RDF-relatedVT variability for FINFETs(~25-50% depending on design)eg. M. Jurczak et al, Proc. 2009 IEEE Int, SOI Conf.
LER-relatedVT variability for FINFETseg. E. Baravelli et al, IEEE T. Nanotechnol. 7, p. 291 (2008).
Warning: considerable spread in reported literature: your mileage may vary
0
10
20
30
40
0 5 10
Planar
Bulk FinFET
SOI FinFET
σ[V
T], m
V
0 5 101/√ (WL) (µm-1)
13 J. Warnock DAC 2011
0
0.2
0.4
0.6
0.8
1
0 1 2 3 4 5 6 7 8 9Device Width (Units of Min width device)
finFET Devices Conventional Devices
Trigate/FinFET Devices: QuantizationTrigate/FinFET Devices: Quantization
Example: min size finFET INVCan have p:n ratio = 1, 0.5, 2(nothing in between)Also, even a “wide” device willalways be just a collectionof very narrow devices…Plus, expect difficulty to createmultiple VT offerings in a fully depleted device scenarioD
evic
e S
treng
th (a
rbU
nits
)
Higher VT(less leakage)
Lower VT(more perf.)
Device Width (ratio to min width device)
• Likely to create most difficulty for SRAM, register file designs• Also small feedback devices, keepers, etc.• Issue for any device tuner, other tools expecting continuous width ranges
14 J. Warnock DAC 2011
• Resistance in contacts to fins might be tricky: assume it can be handled by device engineers! What about G-S cap?
Trigate/FinFET Devices: ParasiticsTrigate/FinFET Devices: Parasitics
G
S
D
D SG
• Expect increase in Cgs comparedto planar structures
• Details will depend on fin vs trigate, fin pitch, height, thickness, etc.
• Might have to watch out for certaintypes of noise issues
• Might decrease static timing accuracy
15 J. Warnock DAC 2011
ETSOI DevicesETSOI Devices
All the good features associated with fully-depleted devices:Expect improved subthreshold slopeExpect improved RDF-induced variabilityAbove could help to enable lower voltage operationNo fin-related quantization, “conventional planar structure”No SOI history effect (no body charge…)
What designers have to worry about:New sources of variability
SOI film thicknessBack interface & oxide quality will affect active device
Same old LER issuesChanges in device parasitic R, C compared to usual expectations
G-S cap (Miller cap): need raised S/D for contactsS, D contact resistance
16 J. Warnock DAC 2011
OutlineOutline
Introduction
Classical CMOS Scaling: The End of the Road
New Device StructuresWhat do these structures mean for circuit designers?
Wire Interconnects
Reliability
Conclusions
17 J. Warnock DAC 2011
Wire Interconnect Scaling (or lack thereof…)Wire Interconnect Scaling (or lack thereof…)
Assume all logic scales with litho shrink factorWire lengths then also would scaleBest case scenario: RC stays constant (“perfect scaling”)
This is already painful, chip area generally hasn’t been shrinking!
Data below shows expectations that wire delays will grow significantly, even in scaled designs.
1
1.2
1.4
1.6
1.8
2
0 50 100 150M1 Metal Pitch (nm)
Rel
ativ
e R
C, s
cale
d 14nmRegime
ITRSdata
ITRS data,but assumingnon-improving dielectric constants
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Wire Scaling ImplicationsWire Scaling Implications
High-performance designs will not be able to tolerate such large RC increases
Will need coarser-pitch, faster wires (ie non-scaled wires)
But also need improved wiring density to leverage technology density
Result: push for more wiring interconnect layers (coarse-pitch)Will still need some number of fine-pitch layers as well for short-run local connections
Improved DA tools (routers) neededOptimize wire plane usage to limit technology complexityNegotiate through special design rules for the finest levelsVia optimizationTricky performance vs wireability tradeoffsMany, many wires will need “special” treatment
Increase width, push higher, add buffers, etc.
19 J. Warnock DAC 2011
OutlineOutline
Introduction
Classical CMOS Scaling: The End of the Road
New Device StructuresWhat do these structures mean for circuit designers?
Wire Interconnects
Reliability
Conclusions
20 J. Warnock DAC 2011
0.01
0.1
1
0 50 100 150M1 Metal Pitch (nm)
Rel
ativ
e Li
fetim
e
1
1.5
2
2.5
3
Rel
ativ
e cu
rren
t den
sity
Interconnect ReliabilityInterconnect Reliability
Reliability will become a significant focus item for designers in 14nm technology
Parameters below taken from ITRS, plotted WRT 2009 dataAssume constant voltage, const frequency for simplicity
14nmRegime
M1 Metal Pitch (nm)
Rel
ativ
e C
urre
nt D
ensi
ty
Rel
ativ
e Li
fetim
e
Lifetime withexpectedcurrent densityscaling
Lifetime atconstantcurrentdensity
21 J. Warnock DAC 2011
New materials likely needed for the finest-pitch planesResistance increases likelyMore impetus to push signal wires higher in the stack
TDDB concerns likely to push technology to higher K materialsHigher dielectric constant materials tend to have better reliabilityWire cap increase drives higher power, increased RCConcern again for finest-pitch planes…
LER, defect-narrowing likely to exacerbate EM concerns
Interconnect ReliabilityInterconnect Reliability
TTF
(Arb
Uni
ts
E (MV/cm)
TEOS
1E-01
1E+01
1E+03
1E+05
1E+07
1E+09
0 2 4 6 8 10 12
Ogawa et al,2003 IRPS
2.2
3.62.9
DielectricConstant4.2
22 J. Warnock DAC 2011
Interconnect Reliability: ImplicationsInterconnect Reliability: Implications
Will need efficient design tool solutions for robust reliabilityLikely many elements with current pushing close to reliability limitsMay need detailed understanding of local switching factors
Local thermal effects likely significant for high-frequency logicIR heating by currents in fine wiresEM effects very sensitively dependent on temperatureWhat happens when hot wires are placed in close proximity?
Answer: they get even hotter (and they heat up the surroundings)Need design tools to help avoid bad thermal situationsNeed thermal analysis tools to detect problematic local situations
Increased overhead from error checking & recovery expectedFor high-reliability systems, checking alone is not enough!Need to be able to recover from hard errorsAbility to take processor cores offline gracefully
Replace with spare core?
23 J. Warnock DAC 2011
OutlineOutline
Introduction
Classical CMOS Scaling: The End of the Road
New Device StructuresWhat do these structures mean for circuit designers?
Wire Interconnects
Reliability
Conclusions
24 J. Warnock DAC 2011
ConclusionsConclusions
Breakdown in scaling is pushing technology in new directions
New devices structures will create new circuit design challengesUnfortunately, fully-depleted device not a panacea for VT variabilityLimited voltage scaling for high-performance chips
Power/power-density limited performance
Biggest challenges for high-performance designs: wiresNon-scaling RCReliability
Circuit/system-level check/recovery features likely to need emphasis for high-reliability systems