Memory Trends Peering into the Future

Server Memory Forum Shenzhen 2012

Outline

• Platform challenge

• Reliability challenge

• Manufacturability challenge

Platform challenge

• New and changing applications – New focus on purpose built platforms

• Database - virtualization drive – More memory per compute unit (Memory footprint).

• Tiered processing with application specific platforms – As DRAM density increase die count decrease.

• Client drive – Slowly increasing memory demand

The memory application space is changing

Platform Challenge

• Up to 2003 very Large memory foot prints where limited to non-commodity architectures

• The open (“64 bit”) address space removed architectural limitation • Connectivity instead of density limited • Driving the tail of distribution faster • Client platforms remain dominant • Could become bimodal BUT??

Memory footprint support spans 3 – 4 orders of magnitude

Disruptive events are on the horizon

• Purpose built “micro – servers” or smaller – Take advantage of highly parallel

applications – Eliminate wasted compute cycles – Smaller memory footprint.

• Take advantage of stacking technology – Wide I/O – High Bandwidth Interface

The Problem – Continue growth at the large memory footprints while an increasing the demand at the low end resulting in even greater skew in the distribution.

Get more data closer

• The closer the data, faster the response. • The closer the data, the fewer wasted compute cycles. • Hard drive being replaced by SSDs • Move SSDs closer – SCSI express. • Even closer yet DDRx attached SSDs • Flash back DRAM • Flash sharing bus with DRAM

– When PCM or … grow up.

Within the lifetime of DDR4 volatile and non volatile memory will share the same bus and address space.

Heresy

• Not all Servers will need memory error checking • Purpose built server • Fault resilient

– Striping across channels – Fault tolerant applications i.e video serving

• Mixed forms on the same platform, possibly the same

server. • Solder down memory

Rethink various applications opening new markets – It’s the Software Systems (ISS)

Result

• DDR4 Must: 1. Support larger address spaces 2. Higher speeds 3. Greater connectivity – a range which span 3 order of

magnitude

• What next – Frequency domain signaling? – Optics?

Is the next DRAM interface a revolutionary step?

Reliability Drive

• Law of large numbers • Consider the following mind

experiment

Consider This

• Most recently accepted number is 23.75 Billion years

• Approximately 8.7e12 days • Or 2.1e14 hours

• Now Consider !

A current platform

• 4 Gb technology • 32 GB DIMMs • 96 DIMMs • 2.7e13 transistors +

• Now Consider • The MTTF of a transistor is the age

of the universe In ones day’s operation;

approximately 3 transistors to fail.

Where do we go from here

• The Good News! – The industry is doing a great job

• THE Bad News – The industry must continue to improve.

• What Next? – Double Device Correction +, this is controller centric solution – Take advantage of latent circuitry within DRAM.

• - remapping such as done in current flash devices. • On chip ECC, as done in current flash devices

Improvements must be done

Manufacturability Drive

• New levels of integration • Smaller purpose built platforms • Stacking technologies • The need for DFT.

Components must be designed with MANUFACTURING in mind!

INEmI – has formed a study group

• This team is adjunct to an iNEMI* study group that is identifying roadblocks to successful usage of IEEE Std 1149.1 Boundary Scan test. The top roadblock identified by that iNEMI study was in finding manufacturing defects in soldered-down memory arrays on complex PC boards. This is due to the current lack of testability features in memory devices. Major OEMs are hitting the breaking point – very anxious to improve the testing process.

*iNEMI – International Electronics Manufactures Initiative.

Expanding upon earlier statements

• Memories are constantly getting faster, more complex, denser –> resistant to testing approaches that have been in use for years.

• Soldered down memory needs testing for mfg defects such as opens, shorts, wrong device, dead device, etc. We are used to pinpoint diagnostics. Leaving these defects to the functional test stages is not economical. Bone piles are increasing.

• Today, we use ICT and/or Boundary Scan to emulate memory write/read cycles; not possible any more.

• DFT in memories would make a powerful cost saving contribution. OEMs are willing to trade these savings for some increased device cost.

iNEMI proposal

• We present a “DFT Tutorial” at the June JEDEC meeting in Washington DC.

• We have accumulated 4 DFT technologies to choose from – you pick the best fit for a given technology.

• Three are “electrical”, one is analog-based, embedded in the package (no die implications).

• We would help you qualify your design specs. • We want your feedback to improve suitability. • Bottom line – work together to make the OEM

manufacturing experience better, lowering costs. Industry working together to produce a better product

Q & A