dukepeople.ee.duke.edu/~jmorizio/ece261/f08/projects/fft.pdf · 2008. 12. 9. · company...

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Complex Multiplier for FFT

ECE 261 Project 2008

Team Members:

Xuan Bao Xiaoyan YinKai Wang Yang Jiang

Complex Multiplier for FFT Algorithm

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Index

Brief Introduction1

Structure implementation2

Feature Evaluation3


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Brief Introduction to the projectFast Fourier Transform (FFT) is an efficient algorithm to compute the Discrete Fourier Transform (DFT) and its inverse. The algorism is based on a factorization of N as described in Fig.1-1. A 16-point DFT is divided into 4 4-point DFT.

x0

x15

x14

x13

x12

x11

x10

x9

x8

x7

x6

x5

x4

x3

x2

x1

X0

X15

X11

X7

X3

X14

X10

X6

X2

X13

X9

X5

X1

X12

X8

X4

Fig.1-1.


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Brief Introduction to the project

(A+Bj)(C+Dj)=(AC-BD)+j(AD+BC)

Fig.1-2.

Fig.1-2. shows the basic unit used for implementing FFT algorithm, the complex multiplier. The function is



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Brief Introduction to the projectThe top level overview of our design is given as Fig 1-3.


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Index

Brief Introduction1

2

Feature Evaluation3

Structure Implementation


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Structure Implementation

Structure consists of…

FIFO × 6Ripple carry Adder × 1Ripple carry Subtractor × 1Signed Multiplier × 4


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FIFO Implementation

SchematicThis is the schematic of one FIFO component. It contains 8 Dflipflops with reset and works as a buffer for both input and output.


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FIFO Implementation

This is the digital simulation result of FIFO component. All possible patterns have been exhaustively tested. To make top level testing easier, we then rewrote the verilog for Dflipflop. The key part of codes is shown above.

Digital Simulation


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FIFO Implementation

Layout


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Ripple Carry Adder Implementation

Halfadder implementation


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Fulladder implementation



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8 bit Ripple Carry Adder implementation


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Layout


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Subtractor Implementation

8 bit Ripple Carry Subtractor implementation


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Subtractor Implementation

Layout


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Multiplier Implementation

Unsigned Multiplication

Algorithm: shift and addition


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Signed Multiplication

Algorithm we use: Baugh-Woodley technique

How to modify?

Need some modifications based on unsigned multiplication.

Only need a few more full adders and change some AND2 gates to NAND2 gates.


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Schematic


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Multiplier ImplementationDigital simulation

Results: 0*-8=0 -3*-5=15

-3*3=-9-3*2=-6

-4*2=-8…

Realizes the multiplication of input X and Y, with the correct outcome Z=XY, which will be sent to Ripple Carry Adder or Ripple Carry Subtractor to calculate:

AD+BC & AC-BD

Consists of:

Nand2 × 6And2 × 10

Full Adders × 9Half Adders × 3

Inv × 1


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Multiplier ImplementationLayout


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System Implementation

Schematic


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Q1= AD+BC

Q2= AC-BD

The latency between input and output is one clock cycle


Digital Simulation


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Layout


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Pass DRC & LVS


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Index

Brief Introduction1

Structure Implementation2

Feature Evaluation3


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Feature Evaluation

Number of transistors

Area (mm^2)

Power Consumption:

Components Totaltransistors

SUM*1 DIFF*1 MULT*4 FIFO*6

252 288 434*4 256*6 3812

2.011*2.416=4.850mm^2

( ) ( ) ( )

2

2 60.1 3812 12 0.8 / 2 2 / 5 10

0.0915 /

P C V f

m fF m

mW MHz

α

λ μ λ μ

= ⋅ ⋅ ⋅

= ⋅ ⋅ ⋅ ⋅ ⋅ ⋅⎡ ⎤⎣ ⎦=


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Feature Evaluation

Power Consumption:From eldo simulation can get latency in critical path:

FIFO_latency=1.45833ns

Multiplier_latency=4.06742ns

Subtractor_latency=0.933838ns

So, total latency=1.45833+4.06742+0.933838=6.459588(ns)


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Feature Evaluation

Power Consumption:So, the maximum frequency is:

So, power consumption is:

9

1 1 155( )_ 6.459588 10

f MHztotal latency −

= = =×

( ) ( ) ( )

2

2 60.1 3812 12 0.8 / 2 2 / 5 10

0.0915 / 15514

P C V f

m fF m

mW MHz MHzmW

α

λ μ λ μ

= ⋅ ⋅ ⋅

= ⋅ ⋅ ⋅ ⋅ ⋅ ⋅⎡ ⎤⎣ ⎦= ⋅=


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Feature EvaluationTop-down demonstration of layout. Firstly, the top level. Let’s take a look at the floor plan.

FIFOFIFO

FIFO FIFO

FIFO

FIFO

Multipli er

Multipli er

Multiplier

Multiplier

Sum

Sub

Complex Multiplier for FFTIndexBrief Introduction to the projectBrief Introduction to the projectBrief Introduction to the projectIndexStructure ImplementationFIFO ImplementationFIFO ImplementationFIFO ImplementationRipple Carry Adder ImplementationRipple Carry Adder ImplementationRipple Carry Adder ImplementationRipple Carry Adder ImplementationSubtractor ImplementationSubtractor ImplementationMultiplier ImplementationMultiplier ImplementationMultiplier ImplementationMultiplier ImplementationMultiplier ImplementationSystem ImplementationSystem ImplementationSystem ImplementationSystem ImplementationIndex Feature Evaluation Feature Evaluation Feature EvaluationFeature Evaluation

dukepeople.ee.duke.edu/~jmorizio/ece261/f08/projects/fft.pdf · 2008. 12. 9. · company...

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