joão canas ferreirajcf/ensino/disciplinas/mieec/pcvlsi/2017-18/... · vlsi síntese rtl 2 contents...
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VLSI Síntese RTL 1
FEUP/DEECFebruary 2015
RTL Synthesis
João Canas Ferreira
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VLSI Síntese RTL 2
Contents
Includes figures from:Douglas J. Smith, HDL Chip Design
Synopsys, Design Compiler User Guide
General overview of the synthesis process Cadence RTL Compiler
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VLSI Síntese RTL 3
Top-down refinement
Progressive refinement of the descriptionsLower levels are increasingly more detailed
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VLSI Síntese RTL 4
RTL descriptions
Register transfer level Description involves registers and combinational circuits Synchronous systems (one or more clock signals)
It is important to describe the implementation explicitly in these terms
R RCombinational
clk
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VLSI Síntese RTL 5
Main steps
[Translation] HDL → internal representation of data and control flow
[Generic optimizations] Function inlining Constant propagation Loop unrolling
[Logic optimization] Logic synthesis Optimization of combinational circuits Retiming
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VLSI Síntese RTL 6
RTL synthesis
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VLSI Síntese RTL 7
Simplified model of design flow process
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VLSI Síntese RTL 9
Logic optimizations
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VLSI Síntese RTL 10
Technology mapping (1)
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VLSI Síntese RTL 11
Technology mapping (2)
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VLSI Síntese RTL 12
Electrical environment (1)
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VLSI Síntese RTL 13
Electrical environment (2)
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VLSI Síntese RTL 14
Conteúdo
Includes figures from :Douglas J. Smith, HDL Chip Design
Synopsys, Design Compiler User Guide
General overview of the synthesis process Cadence RTL Compiler
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VLSI Síntese RTL 15
Work flow
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VLSI Síntese RTL 16
Elaboration
This step includes:
Setup of internal data structures
Register inferencing
High level optimizations
dead code removal
Semantic verifications
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VLSI Síntese RTL 17
Naming
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VLSI Síntese RTL 18
Information hierarchy
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VLSI Síntese RTL 19
Constraints (1)
set output_load [get_attribute capacitance [find /libraries/gscl45nm/ -libpin INVX4/A] ]
set_attribute external_pin_cap ${output_load} /designs/${DESIGN}/ports_out/*
(Synopys Design Compiler)
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VLSI Síntese RTL 20
Signal delays
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VLSI Síntese RTL 21
Constraints (2)
set clock [define_clock -period 2000 -name clk [clock_ports]] #definition of clock signal
external_delay -input 0 -clock clk [find / -port ports_in/*] # input delaysexternal_delay -output 0 -clock clk [find / -port ports_out/*]
set_attribute slew_rise 400 [find / -clock clk] # assumed by cell libraryset_attribute slew_fall 400 [find / -clock clk]
set_attribute external_driver [find [find / -libcell INVX4] -libpin Y] \/designs/mips/ports_in/* # input pins
set_attribute external_driver "" [find / -port clk] # ideal clock
(Synopys Design Compiler)
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VLSI Síntese RTL 23
Interaction with physical synthesis
One of the possible work flows