joão canas ferreirajcf/ensino/disciplinas/mieec/pcvlsi/2017-18/phy3.pdf · clock tree synthesis...
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VLSI Síntese física 1
FEUP/DEECMay 2018
Physical synthesis
João Canas Ferreira
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VLSI Síntese física 2
Contents
Includes figures from::Michael Smith, Application-Specific Integrated Circuits
(chap. 16 & 17)
J. Rabaey, A. Chandrakasan, B. NikolicDigital Integrated Circuits, 2ª ed, Prentice-Hall
Introduction
Floorplanning
Placement
Routing
SoC Encounter
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VLSI Síntese física 3
Contents
Introduction
Floorplanning
Placement
Routing
SoC Encounter
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VLSI Síntese física 4
Generic synthesis flow
Physical synthesis
accurate values for timinganalysis / simulation
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VLSI Síntese física 5
Estimating timing charcateristics
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VLSI Síntese física 6
Interconnect delay
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VLSI Síntese física 7
EStimating the propagation delay of nets
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VLSI Síntese física 8
Contents
Introdução
Floorplanning
Placement
Routing
SoC Encounter
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VLSI Síntese física 10
Floorplanning in action
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VLSI Síntese física 11
Congestion analysis
Global aspect ratio must be controlled so that die fits into packaging cavity.
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VLSI Síntese física 12
Packaging cavity
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VLSI Síntese física 13
“Pad-limited” vs. “core-limited”
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VLSI Síntese física 14
Pads
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VLSI Síntese física 16
Clock signal distribution
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VLSI Síntese física 18
Contents
Introduction
Floorplanning
Placement
Routing
SoC Encounter
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VLSI Síntese física 21
Estimating the length of the interconnect
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VLSI Síntese física 22
Estimating the length of the interconnect (2)
Sum of all n*(n-1) point to point connections divided by n/2
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VLSI Síntese física 24
Contents
Introduction
Floorplanning
Placement
Routing
SoC Encounter
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VLSI Síntese física 26
Estimating the interconnect delay
Elmore delay
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VLSI Síntese física 30
Cell connections
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VLSI Síntese física 31
Internal view of a standard cell
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VLSI Síntese física 33
Example: routing with the metal levels
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VLSI Síntese física 34
Conteúdo
Inclui figuras de:Michael Smith, Application-Specific Integrated Circuits
Introdução
Planeamento (floorplanning)
Colocação (placement)
Encaminhamento (routing)
O sistema SOC Encounter
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VLSI Síntese física 35
SoC Encounter design flow
Import netlist
Floorplan +power plan
Placement(+ refinement)
Clock tree synthesis
Routing
RC parameterextraction
Other tasks: - Generation of layer geometry information (gds2) - Delay calculation (SDF = Standard Delay Format, IEEE 1497, IEC 61523-3) - Information about parasitics for logical synthesis
(SPEF: IEEE 1841) - DRC and ERC (Electrical rule checking) - ECO (Engineering Change Order)
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VLSI Síntese física 42
Clock tree synthesis
specifyClockTree -clkfile ctgen.const
ckSynthesis -rguide muladd_top_cts.guide \-report muladd_top_cts.ctsrpt
AutoCTSRootPin clkMaxDelay 3000psMinDelay 1000psSinkMaxTran 1000psBufMaxTran 1000psMaxSkew 200psNoGating NOBuffer BUF2 BUF4 BUF6 BUF8 BUF12 BUF15 INV0 INV1 INV2 INV3 INV4 INV8 INV10 INV12 INV15 CLKIN0 CLKIN1 CLKIN2 CLKIN3 CLKIN4 CLKIN6 CLKIN8 CLKIN10 CLKIN12 CLKIN15 CLKBU2 CLKBU4 CLKBU6 CLKBU8 CLKBU12 CLKBU15End
Information for routing(guides)
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VLSI Síntese física 43
CLK
H-tree
Example of a clock tree
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VLSI Síntese física 44
Árvore H mais realista
[Restle98]
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VLSI Síntese física 45
Clock distribution on the Alpha 21164 (1)
trise = 0.35ns tskew = 150ps
tcycle= 3.3ns
Placement on the “die”
pre-driver
final drivers
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VLSI Síntese física 46
Clock Drivers
Clock distribution on the Alpha 21164 (2)
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VLSI Síntese física 47
“Skew” of Alpha processor