jump to first page one-gigabit router oskar e. bruening and cemal akcaba advisor: prof. agarwal
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One-gigabit Router
Oskar E. Bruening
and Cemal Akcaba
Advisor: Prof. Agarwal
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Contents Project background The big picture What we are building Project milestones Resources Technical Risks What’s next?
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Background Chip manufacturing technology
has evolved a lot since 1970s. The uses of computers have
changed a lot too. Super-computer architecture
techniques for exploiting parallelism.
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Background Remember 6.004? Pipelining and
hardware scheduled superscalars. These approaches do not scale
well. A 4-stage pipeline, not a 4x
performance boost. Too much complexity.
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Motivation
Want to do fast signal processing with a lot of data
Run computations parallel Supercomputers Beowulf clusters
Increased performance, high price Might not be worth it
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Parallel HW Problems
Inter processor communication expensive: Extra layers of software (driver,
network protocols) slow down Going through extra hardware
(routers, switches) No or limited shared memory
Customizing expensive
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Parallel User Problem
Programmer needs to turn algorithm parallel No Idle nodes Effective communication
Effective spread Effective gathering and evaluation
No Waiting / Deadlocks
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The Raw Processor 2-D mesh of identical tiles. Each tile has its own processor. Tiles connected by dynamic and
static networks. Current implementation has 16
tiles (4x4).
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Raw Architecture Workstation (Raw)
Simple wire-efficient architecture, that scales with increasing VLSI gate densities.
Approach aims to provide better performance by exploiting fine-grain parallelism.
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The Raw Evaluation Board The Raw processor 4 FPGAs External memory PCI bus Other peripherals
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Our project A gigabit Ethernet router.
A router connects many computers with each other on a network
The work break down: Cemal - Ethernet Controller Oskar - Router Software
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Ethernet Controller
Ethernet controller is a device that allows the interfacing to Ethernet.
Sending & Receiving Ethernet packets.
Will provide the Ethernet access of the evaluation board
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What needs to be done?
Hardware interfacing Filtering Media Access Control (MAC) Manchester decoding/encoding of
data streams An interface to rest of the board
Software interfacing
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Challenges
To decide what needs to be built and what needs to be bought from a hardware vendor.
To decide what portion of these tasks are to implemented using Raw resources.
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Resources Required
The Raw evaluation board Simulator Hardware specifications Access time
Time and patience
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Project Milestones
Spring 2003: preliminary design Summer 2003: final design Fall 2003: implementation IAP 2004: testing and debugging Spring 2004: system integration
and completion of thesis
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Risks
Error # 42 The evaluation board
Complexity
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What’s next ?
IAP & Spring 2003 : UROP Familiarizing with the evaluation
board and the raw processor Learning more about Ethernet
controllers Coming up with a preliminary
design Summer 2003: UROP cont.
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Raw Software
Hub = wire connection Switch = package redirect by MAC Router = package redirect by
network protocol
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What needs to be done? Switch
Ethernet Controller interface Package Analysis
Header Recognition Target Identification Create Lookup Table
Router IP protocol
Can be expanded
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Challenges
Learn Raw architecture Show that signal processing is
easier to do on Raw than VLSI with same result
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Resources Required
Raw Evaluation Board Software Compiler Hardware Simulator
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Project Milestones
Switch Ethernet Controller interface Package Analysis
Header Recognition Target Identification Create Lookup Table
Router IP protocol
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What’s next?
Spring 2003: Urop Familiarize with Raw software Design Algorithms
Summer, Fall ‘03, Spring ‘04 Make it work
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One-gigabit Router
Oskar E. Bruening
and Cemal Akcaba