k36 schematic 8-9-2007.bak
TRANSCRIPT
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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APPLE INC.
6
DESIGNER
DESCRIPTION OF CHANGE
REV.
A
D
C
B
A
D
C
B
8 7 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY ITIII NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
TITLE
DRAWING NUMBER
SHT OF
METRIC
DRAFTER
ENG APPD
QA APPD
RELEASE
DESIGN CK
MFG APPD
SCALE
NONE
MATERIAL/FINISHNOTED ASAPPLICABLE
SIZE
DTHIRD ANGLE PROJECTION
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
X.XXX
DO NOT SCALE DRAWING
REV ZONE ECN
CKAPPD
DATE
ENGAPPD
DATE
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
ANGLES
TABLE_TABLEOFCONTENTS_ITEM
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DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
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8/9/2007
MK
MK
REFERENCED FROM M70
MK
MM-MARY(YUAN) MALD-LINDA DUNNLT-LAWRENCE TANMK-MARC KLINGELHOFERRC-RAY CHANGDK-DINESH KUMARRX-RAYMOND XU
ES
Schematic / PCB #’s
LT
LD
RX
LT
ES
ES
MK
MK
MK
MK
RX
ES
RX
ES
LD
ESES
RXRX
DKRXRX
ESRXES
ES
MKMKMK
RXRXRX
ESESLD
LDLDLTLT
RXDK
LD
LT
LTLT
LT
RXRX
DKDK
RX
LD
ES
RX
MK
ES
RX
RXRXRX
LD
RXMK
MKRX
RX
ES
RX
RX
LD
K36 MLB SCHEMATIC
ES
K36 EE DRIS:
LT
DVT BUILD
22
SB Power & Ground
Page
07/17/200645 50GPUSMC SUPPORT
10/30/200644 49T9_MLBSMC
09/05/200643 48USBIR CONTROLLER & BT INTERFACE
06/29/200642 47USBCONNECTOR MISC
06/30/200641 46USBUSB EXTERNAL CONNECTORS
07/17/200640 45GPUSATA CONNECTOR
07/17/200639 44GPUPATA CONNECTOR
07/17/200638 43GPUFIREWIRE PORT
08/30/200537 40ENETFIREWIRE CONTROLLER
09/14/200636 39USBETHERNET CONNECTOR
10/07/200635 38USBYukon Power Control
10/07/200634 37USBEthernet (Yukon)
08/19/200533 34ENET
06/20/200533MEMORYMemory Active Termination
06/20/200531 32MEMORYDDR2 SO-DIMM Connector B
06/20/200530 31MEMORYDDR2 SO-DIMM Connector A
06/06/200629 30DSIMON-WFClock Termination
06/06/200628 29DSIMONClock (CK505)
07/26/200527 28NBSB Misc
06/01/200626 27WFERRYSB Decoupling
10/30/200625 26T9_MLB
10/30/200624 25T9_MLBSB Pwr Mgt, GPIO, Clink
10/30/200623 24T9_MLBSB PCI, PCIe, DMI, USB
10/30/200623T9_MLBSB Enet, Disk, FSB, LPC
06/15/200621 22WFERRYNB Graphics Decoupling
06/15/200620 21WFERRYNB Standard Decoupling
10/30/200619 20T9_MLBNB Grounds
10/30/200618 19T9_MLBNB Power 2
10/30/200617 18T9_MLBNB Power 1
10/30/200616 17T9_MLBNB DDR2 Interfaces
10/30/200615 16T9_MLBNB Misc Interfaces
10/30/200614 15T9_MLBNB PEG / Video Interfaces
10/30/200613 14T9_MLBNB CPU Interface
5/23/0512 13MASTERCPU ITP700FLEX DEBUG
04/26/200611 12MSARWARCPU Decoupling & VID
11/12/200610 11T9_MLB_NOMECPU Power & Ground
11/12/20069 10T9_MLB_NOMECPU FSB
07/17/20068 9GPUSIGNAL ALIAS /RESET
06/15/20067 8WFERRYPower Aliases
07/25/20056 7TPFUNC TEST 1 OF 2
N/A5 5N/ARevision History
07/18/20054 4SMC
06/30/20053 3POWERPower Block Diagram
05/11/20062 2WFERRY-WFSystem Block Diagram
76 06/12/2006WFERRY
106FireWire & SMC Constraints
75 06/12/2006WFERRY
105Clock Constraints
74 06/12/2006WFERRY
104SB Constraints (2 of 2)
73 06/12/2006WFERRY
103SB Constraints (1 of 2)
72 06/08/2006WFERRY
102Memory Constraints
71 06/12/2006WFERRY
101NB Constraints
70 06/08/2006WFERRY
100CPU/FSB Constraints
69 05/21/05EUGENE
94MINI-DVI CONNECTOR
68 06/06/2005GRAPHIC
92EXTERNAL TMDS
67 06/23/2006GPU
90INVERTER,LVDS,TMDS
66 08/19/2005SMC
7965 06/12/2006
DSIMON-WF78
S3 FET & S3/S5 Control64 12/06/2005
ENET77
3.42V/1.25V Switcher63 07/13/2005
POWER76
5V/3.3V Supplies62 07/13/2005
POWER75
1.8V/0.9V Supplies61 07/13/2005
POWER73
1.5V / 1.05V Supplies60 06/29/2006
GPU72
Render VCore Supplies59 07/13/2005
POWER71
IMVP6 CPU VCore Regulator58 05/31/2006
DSIMON-WF70
S0 FETS & Power Sequencing57 07/13/2005
POWER69
DC-In & Battery Connectors56 03/12/2007
M70AUDIO68
AUDIO: JACK TRANSLATORS55 03/12/2007
M70AUDIO67
AUDIO: JACK54 03/12/2007
M70AUDIO66
AUDI0: SPEAKER AMP53 03/12/2007
M70AUDIO62
AUDIO: CODEC52 04/26/2006
WFERRY61
SPI ROMs51 08/23/2005
SMC59
SMS50 11/10/2005
ENET56
Fan49 06/21/2006
GPU55
TEMPERATURE SENSE48 07/17/2006
GPU53
CPU Current & Voltage Sense47 06/01/2006
WFERRY52
SMBUS CONNECTIONS
SCHEM,MLB,K36
?? ?? ?
761
01051-7455
46 06/01/2006WFERRY
51LPC+ Debug Connector
09/05/20061 1USBTable of Contents
Page Contents Sync(.csa) Date
SCHEM,MLB,K36051-7455 CRITICALSCH1
PCBF,MLB,K36820-2279 CRITICALPCB1
Contents Sync(.csa) Date
CONFIGURATION OPTIONS
32
PBUS Supply/Battery Charger
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
Core ~1.2V
2.? GHz
U1000
PG 49
PG 49
HEAT-PIPE/FIN
U5920 SUDDEN MOTION DETECT PG 51
J5100
PG 44
POWER SENSE PG 48
FAN CONN PG 50
PG 46
Bluetooth
J4810
PG 41PG 43PG 42PG 43
J4850
PG 56
PG 55
PG 54
Pg 53
Pg 37
PG 38
Pg 34
Pg 36
PG 39
PG 40
J4501
PG 57-67PG 57
PCI-E
1.05 - 1.25V
Core
NB-GMCH
CPU
800/1066? MHz
Pg 14TMDS
U9200
SDVO
J9401
DVI-I
GPIO
PG 68
GPIOs
CONTROLLER
U4800
Pg 22
Pg 15
J9001
MUX
Out
RGB
LVDS
Pg 14DMI
Pg 17,18,19
U1400
64-Bit
J4600
USB Connectors
J4601
J4700
GeyserTrackpad/Keyboard
3GCONNECTOR
IR
PG 44
Pg 22
J3201
J3101
Pg 13
U5500
U5520
J5601
8
Core 1.05V
SB-ICH8
CLnk 0Pg 24
97
CAMERA
SATA-0
U2300
Pg 23
CodecAudio
ConnsAudio
AmpsSpeaker
U6600/10/20
TRANSLATORSJACK
J6702/03 INTERNAL SPEAKERJ6701 INTERNAL MIC
J6750/00 LINE IN/OUT
J4300
FW32306
J3900
J4401
PG 54
J3201J3101
ITP CONNPG 12
J1302
FSB
Main Memory
x4 DMI
2.5 GHz
TV
Boot ROM
DC/BattSupplyConn
533/667/800? MHzPg30,31
Pg 24
LPC
SMB
Pg 24
Pg 22
SATA
SATA-2
SATA-1
Pg 23
PCI-E
UATA
Pg 22
Ln6
Ln5
Ln4
Ln3
Ln2
Ln1
ConnFireWire
U4000
32-Bit
33 MHz
E-NETConn
E-NET
NINEVEH
U3700
AirPortMini PCI-E
Pg 33
J3400
U6200
CPU
Temp Sense
Power J6900/50
LPC ConnPrt
SerFan
SPI
U6100/50
UC500
U2900
Clk GenDIMM’s
Pg 23
USB
AZALIAPg 23
PCIPg 24
CLnk 1Pg 22
E-NET
Pg 25
Core
43
21
56
Pg 23
SPIDMI
Conn
UATA
ConnSATA
Pg 15/16
DIMM
1.8V - 64 Bits
DDR2 - Dual Channel
Pg 15
Pg 15
CLnk 0
Pg 32
TermParallel
Misc
Clocks
U2900
CK 505
Pg 29
TERMS
Pg 28
Pg 9
Pg 10
A B,0 BSA BSB ADC
SMC
U4900
PG 69
Int Disp
PG 67
Conn
01
76
SYNC_DATE=05/11/2006
System Block Diagram
2
SYNC_MASTER=WFERRY-WF
051-7455
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
K36 POWER SYSTEM ARCHITECTURE
Q7859 075VS5_RUNSS
3.3V
Q3810
Q7001
TPS625101.25V S0
ENA
PP4V5_AUDIO_ANALOG
VOUT
(PAGE 21)U2265
TPS731125MCH DPLL
R7502
18VOUT2
PP1V5_S0_REG
PP1V8_S3_REG
Q7006
19
15
PP1V8_S3_REG_R
PP3V3ENET_SS 15
P1V25_S0_NB_DPLL
15
Q7007
(10.75A MAX CURRENT)
0.9V
1V25S0_RUNSS
RUNSS_GATE_D
Q7006
START (S0)GFX_VR_EN
Q7004
CHGR_EN
Q7860
17-1 PM_ENET_EN_L
PPBUS_G3H
SMC_BATT_ISENSE
01
U7970
A
VOUT
MAX8719VIN
U7950 D7950
U7975
ENRGYSTR LDO
SMC_ENRGYSTR_LDO_EN
6A FUSE
SHGN*
(PAGE 66)
VOUT
GPU_VCORE
U7200ISL6263
(PAGE 60)
02
ENA
VIN
21(7.7A MAX CURRENT)PPVCORE_S0_NB_GFX_IMVP
(PAGE 62)
TPS51116
1.8V
02
15P1V8S0_EN
SMC_PM_G2_EN
LOGIC
PPVBAT_G3H_CHGR_REG
IMVP_VR_ON
ENA2
TPS51120
(PAGE 63)
PP1V2_ENET_REG
RSMRST_PWRGD
PGOOD1,2
(PAGE 59)U7100
VR_ON
02
PGOOD
CLKEN#
VOUTCPUVCORE
ISL9504VIN
CHGR_EN(S5)
ENABLES
VIN
ISL6257HRZU7900
(PAGE 66)
VOUT
SMC_DCIN_ISENSEA
BATTERY 3S2P
BATT_POS_F
Q786011
PM_SLP_S4_L
PM_SLP_S3_L
PM_S4_STATE_L
ICH
DELAY (S3) 12P3V3S3_EN_LRC
RCDELAY (S3)
P5VS3_EN_L12
Q3802
Q3801
PM_ENET_EN_L
IN
ACADAPTER DCIN
ENA1(S5)
3V3S5_RUNSS
PP1V05_S0_REG
VR_PWRGD_CK505_L
PGOOD_1V05S0
PGOOD2
VOUT2
PP3V42_G3H_REG
VOUT2
VOUT1
02
PPBUS_G3H
PPDCIN_G3HD6901
SMC_ADAPTER_EN
PM_SLP_S3_L
1V8S3_RUNSSS5
1V5S0_RUNSS(S0)
WOL_EN
04-1
STARTSOFT
P25
06
(S5)
17
17
A
12
S3
U7870
14
18
17
18
18
16
15
17
SOFTSTART
U7500
PP0V9_S0_REG
U5300PPVCORE_CPU_S0
(36A MAX CURRENT)
P5VS0_EN
(7.5A MAX CURRENT)
09
CURRENT)
PP3V3_S5_REG
Q7865
(4A MAX CURRENT)PP1V5_S0_REG
(8A MAX CURRENT)
PGOOD_1V5S0
SMC_CPU_VSENSE
Q7000
Q7866
(5A MAX
PP5V_S5_REG
24
29
28
27
26
30
23
22
20
19
VOUT1
14
(PAGE 45)
VLDOIN 13
P1V8_S0_FET
16
P5VS3_EN_L
PP5V_S3
4.5V AUDIOTPS79501U6201
TPS51124U7300
VOUT(PAGE 35)
PP3V3_S5
CLK_PWRGD
PM_SB_PWROK
17
17 15
13
15
15
15
15
14
GATE B
GATE D
P3V3S0_EN
P1V8S0_EN
RUNSS_GATE_D
ISL6130IRZA
5V
13
12
10
CPUPWRGD(GPIO49)PWROK
09
05
08
PP5V_S5
VR_PWRGOOD_DELAY
08
07
04
03
02
02
7A FUSE
FSB_CPURST_L
RSMRST_OUT(P15)
IMVP_VR_ON(P16)
PLT_RST*PWR_BUTTON(P90)
P17(BTN_OUT)
SLP_S3_L
SLP_S5_L
BATTERY ONLY:
SMC_ONOFF_L
ALL_SYS_PWRGD
U2801
PP1V8_S0_FET
PM_SLP_S3_L
PP3V3_S0_FET
PGOOD_1V8S3
PP5V_S0_FET
(PAGE 58)
ENA*
U7000
P5VS0_EN
VOUT
SMC_CPU_ISENSE
U4900
RST*
RSMRST_IN(P13)
(PAGE 9)
PWRGOOD
U2300(PAGE 22)
RSMRST*
PWRBTN*
PLTRST*
(PAGE 28)U2900
SLG8LP537V
CLOCK
PP1V05_S0_REG_RR7302
3.425V G3HOT
PGOOD1
VOUT1
1V5S0_RUNSS(S0)
(S0)1V05S0_RUNSS
(S5)
SMC
U4900
Q70071V05S0_RUNSS(S0)
SOFT
VIN ADAPTER IN :
VREG3
1.2V YUKON
ENA
ENA
VIN
IMVP_VR_ON
HCPURST*
99ms DLY
Q7859
MAX8516
U7790
U7600
(PAGE 44)
SMC_RESET_L
SLP_S5_L(P95)
PM_RSMRST_L
PM_PWRBTN_L
P60
VIN
1.05V
VIN
SLP_S4_LSLP_S4_L(P94)
SLP_S3_L(P93)
(PAGE 13)U1400
CRESTLINE
CPU
VIN
RESET*
PLT_RST_L
ENA1
ENA2
CPU_PWRGD
SMCENA
U3830
V
SMC_RESET_LU5000
RN5VD30A-FSMC PWRGD
ENABLE
(PAGE 64)
(PAGE 45)
LT3470PBUSB_VSENSE
(PAGE 61)
Q5350
1.5V
ICH8M
VRMPWRGD
CK_PWRGD
PWRGD
VIN
PWROK
U1000
VR_PWRGOOD_DELAY
25
V
18
U2803VR_PWRGD_CK505
PP5V_S0_FET
PM3V3ENET_SS
P3V3_ENET_FET
GATE C
RST*
19
RESET*SENSE
PP1V25_S0_REG
PP1V9_ENET_REG
17
18
RSMRST_PWRGD
PWRGD(P12)
TPS3808-1.25VU7200
VIN
VIN
ENAPP3V3_ENET_FET
16
GATE A
P3V3S0_EN
12
(PAGE 58)
MR*
VOUTU3820
TPS79501DRB1.9V S3
(PAGE 64)
U7720
VOUT(PAGE 53)
P3V3S3_EN_L
1V25S0_RUNSS
(PAGE 35)
PGOOD_SEQUENCER
UVLO_A
UVLO_B
UVLO_C
UVLO_D
PBUS CONVERTER/BATTERY CHARGER
23
01
06-1
10-1
17-1
PP1V25_S0_FET
PP3V3_S3
PP3V3_S0_FET 16
PGOOD_1V05S0
PGOOD_1V5S0
3
01
SYNC_DATE=06/30/2005SYNC_MASTER=POWER
Power Block Diagram
76
051-7455
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
SIGNAL
Signal aliases required by this page:
NBCFG_PEG_REVERSE
0.031
0.076
Page Notes(NONE)
NBCFG_DMI_X2
>
>> >
>
>
>
BOMOPTION
0.014
0.014
TOTAL
0.014
L8-L9
>>
>>
BOM OPTION 630-7935
TRACE WIDTH(MM)
>>
>>
>>
>>
>
>>
>>
>
>>
>>
>>
>>
>>
>
CONCEPT
>
L4 SIGNAL
INVERTER_UNBUF
>ISL6130
NBCFG_SDVO_AND_PCIE
ITP
0.1
YUKON_ULTRA
>>
>>
>>
>>
LAYER
COMMON
LPCPLUS
0.018
L7-L8
BETTERL1-L2
YUKON_EC
ISL6126
NBCFG_DMI_REVERSE
L1 SIGNAL(TOP)
CONFORMAL_COAT
GOOD
BEST
---
0.07
L11-L12L12 SIGNAL(BOTTOM)
L6-L7
L7 POWER
L5-L6
L4-L5L5 GND
L6 POWER
L2 GROUND
L2-L3L3 SIGNAL
THICKNESS
0.014
0.076
0.014
0.014
1.276
0.156
0.0470.07
0.076
(MM)
0.047
0.1
0.1
---
0.1
0.1
---
---
(NONE)
(NONE)
L3-L4 0.1560.014
0.076
0.07
MLB STACKUP
---
0.079
ODD_PWR_RESUME
ODD_PWR_CORE
STANDOFF
FANCY
NORMAL
M70 GOOD
ARB_ONLY
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
BOM OPTION REMOVED
K36
K36_PGM
K36 GOOD K36 BETTER K36 BEST630-9104 630-9105 630-9106EVT EVT EVT
L10 SIGNAL
0.031
0.07
0.079
NBCFG_DYN_ODT_DISABLE
NO_REBOOT_MODE
INVERTER_BUF
ALTERNATE
Power aliases required by this page:
BOM options provided by this page:
GROUND POWER POWER GROUND SIGNAL(High Speed) SIGNAL(High Speed) GROUND
GROUND SIGNAL
BOTTOM111098765
32Top
L9-L10L9 SIGNAL
BOARD STACK-UP AND CONSTRUCTION
LOCKED BOOTROM PN 341S2197
L11 GROUNDL10-L11
0.076
SIGNAL(High Speed) SIGNAL(High Speed)
4
BOM TABLE FOR HF POSCAPS
---0.014L8 GROUND
CONFORMAL_COAT 0.018
PAGE_BORDER=TRUE
SYNC_MASTER=SMC
01
4 76
SYNC_DATE=07/18/2005
051-7455
K36
K36CRITICAL
EEE:Z571 CRITICAL BEST826-4393
EEE:Z56 CRITICAL1 BETTER826-4393
EEE:Z55826-4393 1 CRITICAL GOOD
CRITICAL K36
GOOD
BEST
U1000
2
CRITICAL1
1
CRITICAL
CRITICAL
BETTER
CRITICAL
U1000
1
1
U1000
U2300
U1400
516-0162
338S0434
343S0448
LBL,P/N LABEL,PCB,28MMX6MM
LBL,P/N LABEL,PCB,28MMX6MM
LBL,P/N LABEL,PCB,28MMX6MM
1 IC,16MBIT 8PIN SPI SERIAL FLASH,SOIC8341S2196 K36_PGMCRITICAL
IC,CYPRESS,CY7C63833,ENCORE_II,USB_CONTR341S2093 K36_PGMU48001
341S2198 IC,SMC,HS8/21161 CRITICALU4900
341S2060 IC,EEPROM,SERIAL IIC,8KBIT,SO81 K36_PGMCRITICAL
CONFIGURATION OPTIONS
CRITICAL4 C4610,C4611,C6830,C6831 K36128S0147 HF VERSION OF 128S0057
CRITICAL K36HF VERSION OF 128S0085 C6605
K36CRITICALHF VERSION OF 128S0111 C7220,C7352,C7542
CRITICAL K36C2130,C2716,C7543
K36CRITICAL
3128S0164
6 HF VERSION OF 128S0115 C6204,C6205,C7651,C7652,C7691,C7692
CRITICAL K362 HF VERSION OF 128S0113 C2173,C2700
CRITICAL K36128S0157 1 HF VERSION OF 128S0122 C2220
IN-LINE SODIMM CONNECTOR
IC,ICH8,BGA
IC,CRESTLINE,GM965,667
IC,MDC,SR,E1,2.0G,800FSB,4M,BGA
IC,MDC,SR,G0,2.2G,800FSB,4M,BGA
IC,MDC,SR,G0,2.2G,800FSB,4M,BGA1
337S3463
337S3500
337S3500
J3101,J3201
U6100
U3780
CRITICAL
K36_PGM
CRITICAL K361128S0162 HF VERSION OF 128S0123 C2140
K36CRITICAL128S0135 HF VERSION OF 128S01292 C6601,C6603
HF VERSION OF 128S0073
1
3
128S0150
128S0160
128S0148
128S0169
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
- ALL 128S0122 BECOME 128S0157.- ALL 128S0115 BECOME 128S0150.
- ADD ISOLATION BUFFER FOR ODD_RESET_L SIGNAL, ADD 100K PULL-DOWN TO ODD_PWR_EN_L, ADD ’DRAG’ CIRCUIT TO
- LOWER RDS(ON) MOSFET (FDC606P - APN: 376S0552) FOR ODD AND LCD POWER - RADAR: TBD
- HIGH-PRECISION 0.1% RESISTORS TO INCREASE OUTPUT VOLTAGE REGULATION (5V, 3.3V, PBUS_LDO) ACCURACY - RADAR:4972500
- FIX LINDA CARD POWER ALIAS (NEED TO CONNECT TO PP3V42_G3HOT INSTEAD OF PP3V3_S5) - RADAR: 4927858
- CHANGE BOM STUFFING TO SPEED UP PORT POWER SHUT-OFF RESPONSE TIME DURING ACTIVE LATE-VG EVENT (RADAR: 4985252)
- CHANGE BOM STUFFING TO ENABLE ON-BOARD MICROPHONE CONNECTOR (M42/M42A SOLUTION) INSTEAD OF ROUTING
- CHANGE BEST CPU FROM 337S3465(2.4GHZ) TO 337S3464(2.2GHZ).
- ADD BOM OPTION TABLE FOR ALL SANYO POSCAP TO USE HF PARTS.CSA PAGE 4:- ADD OMIT TO ALL ABOVE PARTS SO THE HF PARTS IN BOM TABLE TAKE OVER.- ALL 128S0129 BECOME 128S0135.- ALL 128S0123 BECOME 128S0162.
- ALL 128S0113 BECOME 128S0160.- ALL 128S0111 BECOME 128S0169.- ALL 128S0085 BECOME 128S0148.- ALL 128S0073 BECOME 128S0164.- ALL 128S0057 BECOME 128S0147.PER CE, ALL SANYO POSCAPS HAVE NEW HF PART NUMBERS.
8/9/2007
M70 EVT TO DVT CHANGES
M70 EVT TO DVT CHANGES
- TEST POINT MOVEMENTS REQUESTED BY ICT AND MAC-1 GROUPS - RADAR: 4924481
- MODIFY FIREWIRE CONNECTOR SYMBOL TO SUPPORT MINI-DVI CONNECTOR WITH TAB
- CHANGE 10UF, 16V CPU VCORE CAPS TO 10UF, 6.3V CAPS - RADAR: 4952553
- CHANGE LOAD CAP STUFFING OPTION FOR RTC AND ETHERNET CRYSTALS TO MEET 5XESR (-R) REQUIREMENT
PROPERLY DISCHARGE ODD POWER WHEN IT’S TURNED OFF - RADAR: 4923903
M70 PROTO TO EVT CHANGES
- ADD 270K PULL-DOWN RESISTOR ON HTPLG - RADAR: 4888755
- MOVE SMC RESET BUTTON PAD TO TOP SIDE OF MLB - RADAR: 4920913
CSA PAGE 8:
- 4954357 BREAK OUT =PP3V3_S3_AIRPORT_AUX(J3400,PIN 24) FROM PP3V3_S3_AP_AUX AGAIN.- 4954357 MOVE C3409 AND C3410 FROM PP3V3_S3_AP_AUX RAIL TO =PP3V3_S3_AIRPORT_AUX RAIL.
- NORMAL CHANGES FROM 514-0409 TO 514-0459, FANCY CHANGES FROM 514-0411 TO 514-0479.- CHANGE J6750 FROM 514-0408 TO 514-0458 (DIFFERENT JEDEC, SAME LANDPATTERN).- UPDATE BOM OPTION TABLE FOR J6750.- NORMAL CHANGES FROM 514-0408 TO 514-0458, FANCY CHANGES FROM 514-0410 TO 514-0478.
- CHANGE J6700 FROM 514-0409 TO 514-0459 (DIFFERENT JEDEC, SAME LANDPATTERN).
- CHANGE R9201 AND R9202 FROM 5.23K TO 2.94K.
- NORMAL CHANGES FROM 514-0375 TO 514-0480, FANCY CHANGES FROM 514-0376 TO 514-0481.
- CHANGE L7900 FROM 152S0302 TO 152S0670 FOR CORRECT AVL.
- SMC PART NUMBER CHANGES FROM 341S2088 TO 341S2198.
CSA PAGE 29:- ADD ALIAS =PP3V3_S3_SMBUS_SMC_MGMT TO PP3V3_S3.
- UPDATE EEE CODES, Z55 FOR GOOD, Z56 FOR BETTER, Z57 FOR BEST.
CSA PAGE 32:- STUFF C3110 AND C3111.CSA PAGE 31:
CSA PAGE 9:
- FIX MOJO-CARD SMC TX, RX REVERSAL - RADAR: 4910888
CSA PAGE 90:
- CHANGE SB FROM 338S0427 TO 338S0434.
- CHANGE J3900 FROM 514S0143 TO 514-0443.
- REMOVE NO_TEST=TRUE FOR 1V8S3_COMP, 1V8S3_FSET, 3V3S5_COMP, 3V3S5_FSET, 1V05S0_COMP, 1V05S0_FSET, IMVP6_RBIAS, IMVP6_COMP, 5VS5_RUNSS, 1V5S0_RUNSS.
- REMOVE ALIASES FOR GND_CHASSIS_AUDIO_SPKRCONN,GND_CHASSIS_AUDIO_SHIELD1,GND_CHASSIS_AUDIO_SHIELD2,GND_CHASSIS_AUDIO_SHIELD3,MIC_SHIELD_LVDS_R,MIC_SHLD_CONN.
- ADD FUNC_TEST=TRUE FOR THRM_FINSTACK_P/N.
7/6/2006
- CHANGE U5500 FROM M70 EMC1033 CIRCUIT TO M71 EMC1043 CIRCUIT.
- CHANGE J4810 FROM 518S0369 TO 518S0521.
- CHANGE C2700 FROM 128S0051 TO 128S0113 PER CE.
7/5/2006
- CHANGE R2514 TO 100K.CSA PAGE 29:
- RENAME CPU_VID_R<6:0> TO CPU_VID<6:0>.CSA PAGE 71:- ADDED R6856 NO STUFF.- CONNECTED MIC_SHLD_CONN TO GND_CHASSIS_AUDIO_MIC THROUGH R6854.CSA PAGE 68:- ADDED R6740 NO STUFF.- REMOVED DZ6772.- ADDED L6771 AND L6773 TO MIC INPUT EMI FILTER.- CHANGED ALL TRANSIENT SUPPRESSORS TO 6.8V/100PF DEVICES (WERE ORIGINALLY 8V/100PF DEVICES).CSA PAGE 67:- ADDED SMALL 15PF COMPENSATION CAP. TO U6201 FEEDBACK NETWORK (C6224).- ADDED A NO STUFF PULL-UP TO CODEC_DVDD AT GPIO1.- RE-CONNECTED /SHDN INPUT OF U6801 SO THAT IT’S CONTROLLED BY U6200 PORTA VREF. - DISCONNECTED GPIO1 AND TERMINATED IT WITH A 10K PULL DOWN.CSA PAGE 62:- RE-DRAW CPU VOLTAGE SENSE RC FILTERING.CSA PAGE 53:- REMOVE TEXT NOTE WILL CHANGE TO 606P.CSA PAGE 44:- CHANGE R2902 FROM 1OHM TO 0OHM.- CHANGE R2900, R2901 FROM 2.2OHM TO 0OHM.- NOSTUFF C2907, C2910, C2916, C2911, C2914.- CHANGE L2902 AND L2903 FROM 155S0302 TO 0OHM R2906 AND R2907.
- ADD R2597 AND R2596 FOR 10K PU ON GPIO6 AND GPIO17(EXTGPU_RST_L).CSA PAGE 25:- RENAME LVDS_VREFH/L TO TP_LVDS_VREFH/L.CSA PAGE 15:- DELETE TEXT NOTE AND WITH RESET BUTTON.CSA PAGE 13:- REMOVE R1290 TO R1296 ON CPU_VID<0:6>.CSA PAGE 12:- ADD SPN ALIASES FOR CK505_PCI2/4_CLK.- ADD SPN ALIASES FOR TP_CK505_SRC7_N/P.- REMOVE ALIAS FOR =FWPWR_PWRON.
CSA PAGE 9:- ADD FUNC_TEST=TRUE FOR PP1V05_S0_R.
- REMOVE NO_TEST=TRUE FOR CK505_PCI4_CLK_SPN, CK505_SRC1_N/P_SPN, CK505_SRC3_N/P_SPN, CK505_SRC7_N/P_SPN, CK505_SRC_CLKREQ1/3_L?SPN.
CSA PAGE 8:
- CHANGE J9000 FROM 518S0369 TO 518S0521.CSA PAGE 90:- CHANGE J6703 FROM 518S0369 TO 518S0521.- CHANGE J6702 FROM 518S0487 TO 518S0519.CSA PAGE 67:- CHANGE J5601 FROM 518S0369 TO 518S0521.CSA PAGE 56:- J5550 CHANGES FROM 2PIN TO 4PIN.
CSA PAGE 55:
CSA PAGE 48:
6/29/2007
M70 DVT TO K36 CHANGES
- REMOVE R4660 AND R4601 (U4675 BYPASS RESISTORS).CSA PAGE 46:- CHANGE J2800 FROM 518S0487 TO 518S0519.CSA PAGE 28:
CSA PAGE 27:- CHANGE C2173 FROM 128S0051 TO 128S0113 PER CE.CSA PAGE 21:- REPLACE ALL M70 WITH K36 (TEXT, BOM OPTIONS, 630 NUMBERS).CSA PAGE 4:
- 5040728 CHANGE L9404 FROM 155S0303 TO 155S0348.CSA PAGE 94:- REPLACE BATTERY INTERFACE CIRCUIT WITH THE ONE ON M42B ESTAR.- CHANGE J6900 FROM 518S0287 TO 518S0526.CSA PAGE 69:- CHANGE J4700 FROM 516S0251 TO 516S0588.CSA PAGE 47:- ADD NOSTUFF R4660 AND R4661.- REMOVE MIN_NECK_WIDTH=0.3MM FROM PP5V_S3_USB2_EXTA/B.- CHANGE U4600 FROM 353S1245 TO 353S1728.CSA PAGE 46:- EDIT BOM OPTION TABLE.
CSA PAGE 39:- CHANGE STRAPPING FROM 0010 ON GFX_VID<1:4> TO 0001 ON GFX_VID<0:3>.- CHANGE GFX_VID<1:4> TO GFX_VID<0:3>.- SIZING DOWN R2205 FROM 0603 TO 0402 FOR PLACEMENT.- 5282756 ADD C2207 (0.1UF, 0402).CSA PAGE 22:- ADD R1600 (0OHM, 0402) TO CONNECT GFX_VID<4> TO GND.- CONNECT GFX_VID<0:3> TO GFX_VID0:3 ON NB.- DISCONNECT GFX_VID<0> TO GND.CSA PAGE 16:
- CHANGE NB FROM 338S0426(500M) TO 343S0448(667M).- CHANGE BEST CPU FROM 337S3457(2.2G) TO 337S3465(2.4G).- CHANGE BETTER CPU FROM 337S3456(2.0G) TO 337S3464(2.2G).- CHANGE GOOD CPU FROM 337S3471(1.8G) TO 337S3463(2.0G).CSA PAGE 4:
CSA PAGE 49:- 5040728 STUFF C9421 FOR EMI.
3/5/2007
- 5048817 SYNC 1P25V REGULATOR CIRCUIT FROM M82, CHANGE R AND C TO 0402, CHANGE =PP3V3_S5_P1V25S0 TO =PP3V3_S5_1V25S0,C7723 FROM 2.2NF TO 10000PF, C7724 FROM 22PF TO 100PF, C7728 FROM 2.2NF TO 10000PF,AND REVERT REFERENCE DESIGNATORS. (CHANGE FROM TPS62510 TO LTC3412A)
3/12/2007
- 4924443 CHANGE R2514 FROM 100K PULL-UP TO 47K PULL-UP.CSA PAGE 45:
- 4924443 CHANGE R2514 FROM 100K PULL-DOWN TO 10K PULL-UP TO 3.3V_S5.
- 4986074 CHANGE L2205 TO R2205(100OHM,5%,1/10W,0603).
CSA PAGE 69:- ADD TEXT NOTE TO UPDATE J4700 FROM 516S0251 TO 516S0588 WHEN SYMBOL IS READY.
- 4986074 CHANGE R9469 FOR CRT_TVO_IREF FROM 1.3K TO 1.21K.
- ADD TEXT NOTE TO UPDATE J6900 FROM 518S0287 TO 518S0526 WHEN SYMBOL IS READY.
- DELETE LVDS_VREFH AND LVDS_VREFL TO GROUND TO FIX LVDS GLITCH.
- ADD TEXT NOTE TO CHANGE L9404 FROM 155S0303 TO 155S0348 WHEN SYMBOL IS READY.
CSA PAGE 77:
- SYNC FROM AUDIO TEAM.
3/14/2007
CSA PAGE 47:
CSA PAGE 94:
CSA PAGE 79:
- UPDATE SYMBOL FOR J4501.
CSA PAGE 22:
- NO STUFF 3G CONNECTOR CIRCUITRY
CSA PAGE 62,66,67,68:
CSA PAGE 67:
CSA PAGE 25:
3/8/2007
CSA PAGE 25:
CSA PAGE 62,66,67,68:- SYNC FROM AUDIO TEAM.CSA PAGE 94:
MICROPHONE THROUGH LVDS CABLE
CSA PAGE 34:
- 5029811 CHANGE Q7940 FROM 376S0326 TO 376S0558.
- 4999533 SWAP PIN 2 AND PIN 3 OF MIC CONNECTOR, BACK TO M42 PIN OUT.
Revision History
- WAKE-ON-WIRELESS SUPPORT - RADAR: 4954357
CSA PAGE 4:
CSA PAGE 8:
- ADD CRITICAL TO U2900.CSA PAGE 44:- ADD CRITICAL TO U4401.CSA PAGE 46:
CSA PAGE 49:
CSA PAGE 52:
- STUFFED R6740.
CSA PAGE 68:- NO STUFFED R6854CSA PAGE 72:
CSA PAGE 50:
- SMC MANAGEMENT SMBUS CONNECTION:
7/10/2007
- BOOTROM PART NUMBER CHANGES FROM 341S2085 TO 341S2196.
- SMB_ME_CLK AND SMB_ME_DATA ON SOUTHBRIDGE DISCONNECTED FROM SMB_MGMT_CLK AND SMB_MGMT_DATA FROM SMC.B - THE 10K PULL-UP RESISTORS (R5230 AND R5231), AND STILL REMAIN CONNECTED TO PP3V3_S5_SMBUS_SB_ME AND STAY ON THE SB SIDE.
- ADD TWO NEW 10K PULL-UP RESISTOR (R5232 & R5233) TO =PP3V3_S3_SMBUS_SMC_MGMT.B
CSA PAGE 59:
- ICH8-M ME SMBUS:
- CHANGE R5077 FROM PULL-UP TO A PULL-DOWN RESISTOR AND NAME IT SMC_SMS_INT.
- REMOVE ALIAS FOR =SMC_SMS_INT TO SMC_PG1 - SIGNAL SHOULD JUST BE CALLED SMC_SMS_INT.
- ADD R4670 & R4671. (USB BYPASS ROUTING).- CHANGE U4675 FROM APN 353S1505 TO APN 353S1742. (SMALL PACKAGE)
CSA PAGE 59:
CSA PAGE 46:
CSA PAGE 67:
CSA PAGE 39:
CSA PAGE 50:
CSA PAGE 62:
CSA PAGE 67:
7/11/2007
- CHANGE R7208 FROM 8.66K TO 15.8K.
- MADE DZ6702, DZ6703, DZ6704, DZ6705, DZ6752, DZ6753, DZ6754, DZ6755, DZ6770, DZ6771B CRITICAL.
- REMOVED NO STUFF RESISTORS R6730, R6731, AND R6732. ALSO REMOVED L6774.
- MADE NO_TEST ATTRIBUTE VISIBLE FOR NET NC_VRP CONNECTED TO PIN 37 OF U6200.- CHANGED C6210 FROM A CASE-R 10UF TANT. CAP. TO A SMA-LF 3.3UF TANT. CAP.
-ADD 2ND SMS (U5930).
- THE PULL-UP RESISTORS SHOULD BE CONNECTED BETWEEN SMB_MGMT_CLK AND SMB_MGMT_DATA TO =I2C_SMS_SCL AND =I2C_SMS_SDA OF THE NEW ACCELEROMETER.
- STUFF U5930 (DIGITAL ACCELEROMETER) CIRCUIT.
- STUFF C3210 AND C3211.
- REMOVE R5077 (BECOMES R5931).
- ADD R5931 (WAS R5077 BEFORE), 10K PD ON SMC_SMS_INIT.- ADD R5930, 10K PU ON SMC_SMS_INT.
- UPDATE PN FOR FANCY RJ45 CONNECTOR, 514-0475.
- CHANGE Z0901 AND Z0906 FROM 998-1178 TO 998-1186 (NON-PLATED).
- 4954357 ADD =PP3V3_S3_AIRPORT_AUX BACK TO PP3V3_S3 ALIAS.
- UPDATE BOM OPTION TABLE FOR J6700.
7/17/2007
CSA PAGE 59:
CSA PAGE 43:
7/12/2007
- UPDATE SYMBOL FOR U5930, VENDOR PART NUMBER CHANGES FROM SMB380 TO BMA150.
CSA PAGE 38:
CSA PAGE 4:
7/13/2007
- UPDATE BOM OPTION TABLE FOR J9401.CSA PAGE 94:
CSA PAGE 79:
- CHANGE C3831 AND C3832 FROM 138S0582 TO 138S0554 (DON’T NEED LOW-PROFILE PARTS).
7/24/2007
CSA PAGE 4:- CHANGE BETTER AND BEST CPU TO G0 STEPPING PARTS (FROM 337S3464 TO 337S3500).CSA PAGE 22:- STUFF R2242 AND NOSTUFF R2247.CSA PAGE 92:
- CHANGE R9211 AND R9212 FROM 16.5K TO 9.09K.
CSA PAGE 62:
- CHANGE J4300 FROM 514-0289 TO 514-0456 (SAME JEDEC).
- UPDATE BOM OPTION TABLE FOR J4600 AND J4601.
- ADD PAGE_TITLE AUDIO: CODEC.
- NORMAL CHANGES FROM 514-0288 TO 514-0457, FANCY CHANGES FROM 514-0315 TO 514-0477.
- CHANGE J4600 AND J4601 FROM 514-0288 TO 514-0457 (DIFFERENT JEDEC, SAME LANDPATTERN).
- NORMAL CHANGES FROM 514-0359 TO 514-0456, FANCY CHANGES FROM 514-0316 TO 514-0476.- UPDATE BOM OPTION TABLE FOR J4300.
051-7455
Revision History
5 76
01
SYNC_MASTER=N/A SYNC_DATE=N/A
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
FUNC_TEST
INVERTER CONNECTOR FUNC_TEST
Battery charger FUNC_TEST
DC-JACK FUNC_TEST
MIC FUNC_TEST
USB FUNC_TEST
Battery FUNC_TEST
SMC FUNC_TEST
FIREWIRE FUNC_TEST
SMBus FUNC_TEST
Other Func Test Points
Fan Connectors
SLEEP LED FUNC_TEST
Battery Digital Connector
NO_TEST
FUNC_TEST
NO_TEST
NO_TEST
Audio FUNC_TEST
Functional Test Points
FUNC_TEST
FUNC_TEST
LPC+ Debug Connector
SPEAKER FUNC_TEST
THERMAL FUNC_TEST
Power Supply FUNC_TEST
Power Supply NO_TESTsNO_TEST
CLOCK NO_TESTSNO_TEST
FIREWARE NO_TESTS
LVDS NO_TESTS
I1
I10
I11
I111
I112
I113
I114
I115
I116
I117
I118
I119
I12
I120
I122
I125
I15
I151
I152
I153
I154
I155
I156
I157
I158
I159
I16
I160
I161
I162
I163
I164
I166
I167
I168
I169
I17
I171
I172
I173
I174
I175
I176
I177
I178
I18
I180
I181
I182
I183
I186
I187
I188
I189
I19
I190
I191
I194
I195
I199
I20
I200
I201
I202
I203
I204
I205
I206
I207
I208
I209
I21
I210
I211
I212
I213
I214
I215
I219
I22
I220
I221
I222
I223
I224
I225
I226
I227
I228
I229
I23
I230
I231
I232
I233
I234
I235
I236
I237
I238
I239
I24
I240
I241
I242
I243
I244
I25
I29
I3
I31
I32
I33
I36
I38
I4
I44
I45
I46
I47
I48
I57
I58
I59
I60
I61
I63
I71
I72
I73
I74
I75
I76
I77
I78
I79
I80
I81
I82
I83
I84
I85
I86
I87
I88
I89
I9
I90
I91
I92
I93
I94
I95
I96
051-745576
01
6
FUNC TEST 1 OF 2
IMVP6_RBIAS
TRUE CK505_CPU1_N
CK505_DOT96_27M_NTRUETRUE CK505_DOT96_27M_P
TRUE CK505_CPU2_ITP_SRC10_NTRUE CK505_CPU1_P
CK505_CPU2_ITP_SRC10_PTRUE
TRUE CK505_CPU0_PTRUE CK505_CPU0_N
TRUE SMC_TMSDEBUG_RESET_LTRUESMC_TRST_LTRUE
TRUE LPC_AD<1>
TRUE =PP5V_S0_LPCPLUS
TRUE LPC_AD<0>
TRUE ACZ_BITCLKTRUE ACZ_SDATAOUT
TRUE MIC_HIMIC_LOTRUEMIC_SHIELDTRUEMIC_HI_CONNTRUE
TRUE INV_BKLIGHT_PWM_LTRUE PP5V_INV_F
PPVBAT_G3H_CHGR_OUTTRUE
TRUE ACIN_ENABLE_GATE
PPBUS_ALL_INV_CONNTRUE
TRUE USB2_3G_F_NTRUE USB2_BT_F_NTRUE USB2_BT_F_PTRUE TP_USB_EXTC_NTRUE TP_USB_EXTC_P
TP_USB_EXCARD_NTRUETP_USB_EXCARD_PTRUE
ACZ_RST_LTRUE
TRUE USB2_3G_F_P
TRUE INV_GND
TRUE SYS_ONEWIRE
LPC_AD<3>TRUE
SMC_TCKTRUE
TRUE LVDS_B_DATA_P1_SPN
TRUE FW_C_TPA_P_SPN
TRUE FW_B_TPBIAS_SPN
TRUE PP3V3_S5
TRUE PP1V8_S3
TRUE SMC_LID
SPKRCONN_R_P_OUTTRUE
SPKRCONN_L_N_OUTTRUESPKRCONN_L_P_OUTTRUE
TRUE PPFW_SWITCH
TRUE SYS_LED_ANODE
SMBUS_SMC_B_S0_SDATRUE
SMBUS_SMC_B_S0_SCLTRUE
LINDACARD_GPIOTRUE
SMC_TDITRUE
TRUE SMC_MD1TRUE SMC_TX_LTRUE FWH_INIT_L
PCI_CLK33M_LPCPLUSTRUELPC_AD<2>TRUE
INT_SERIRQTRUEPM_SUS_STAT_LTRUE
SMC_RESET_LTRUE
TRUE SMC_TDO
TRUE BOOT_LPC_SPI_L
=PP5V_S0_FAN_RTTRUEFAN_RT_PWMTRUEFAN_RT_TACHTRUE
TRUE SMC_FAN_1_CTL
TRUE SMC_ADAPTER_ENTRUE SMC_BC_ACOK
GND_BT_FTRUE
TRUE PP0V9_S0
TRUE BATT_POS
SMBUS_BATT_SCL_FTRUESMBUS_BATT_SDA_FTRUE
TRUE BATT_NEG
SMC_FAN_3_TACHTRUE
LVDS_B_DATA_P2_SPNTRUE
TRUE LVDS_B_DATA_N0_SPN
TRUE FW_C_TPB_P_SPN
TRUE =PP3V3_S0_FAN_RT
TRUE FW_C_TPB_N_SPN
TRUE LVDS_B_CLK_N_SPN
LVDS_B_DATA_N1_SPNTRUE
TRUE FW_C_TPA_N_SPNTRUE FW_B_TPB_P_SPN
TRUE FW_C_TPBIAS_SPN
TRUE LVDS_B_CLK_P_SPN
TRUE FW_B_TPB_N_SPN
TRUE FW_B_TPA_N_SPN
=PP5V_S0_AUDIOTRUEGND_AUDIO_AMPTRUE
TRUE GND_AUDIO_CODEC
=PP5V_S0_AUDIO_AMPTRUE
TRUE SMC_BS_ALRT_L
TRUE LVDS_B_DATA_N2_SPN
SMC_BATT_CHG_ENTRUE
TRUE SMC_BATT_TRICKLE_EN_L
TRUE ACZ_SYNC
TRUE ACZ_SDATAIN<0>
TRUE SMC_BATT_ISET
SMC_NMITRUESMC_RX_LTRUE
TRUE =PP1V05_S0_REG
PP18V5_G3HTRUE
TRUE =PP3V42_G3H_LPCPLUS
TRUE SMC_FAN_1_TACH
PM_CLKRUN_LTRUETRUE LPC_FRAME_L
TRUE CK505_SRC8_N
TRUE CK505_LVDS_P
TRUE CK505_SRC2_PTRUE CK505_SRC2_N
TRUE CK505_SRC4_NTRUE CK505_SRC4_PTRUE CK505_SRC5_N
CK505_SRC5_PTRUE
TRUE CK505_SRC8_P
TRUE CK505_SRC6_NCK505_SRC6_PTRUE
TRUE THRM_DIMM_DX_F_N
SPKRCONN_SUB_P_OUTTRUESPKRCONN_SUB_N_OUTTRUE
MIC_SHLD_CONNTRUEMIC_LO_CONNTRUE
THRM_HEATPIPE_PTRUETHRM_HEATPIPE_NTRUE
PP5V_S5TRUE
PPBUS_G3HTRUE
PP3V3_S3_BT_FTRUE
TRUE THRM_FINSTACK_PTRUE THRM_DIMM_DX_F_P
PP5V_S3TRUEPP3V3_S3TRUE
SMC_MANUAL_RST_LTRUETRUE SMC_CPU_VSENSE
SPKRCONN_R_N_OUTTRUE
TRUE PP3V42_G3H
TRUE PP1V2_ENET_S0PP5V_S0TRUEPP3V3_S0TRUE
TRUE ALL_SYS_PWRGD
TRUE PP1V5_S0TRUE PP1V8_S0
TRUE PP1V05_S0
PPVCORE_S0_CPUTRUETRUE PP1V05_S0_R
TRUE THRM_FINSTACK_N
IMVP6_COMP5VS5_RUNSS1V5S0_RUNSS
CK505_LVDS_NTRUE
TRUE CK505_PCIF1_CLK
TRUE FW_B_TPA_P_SPN
57C4
46B6
45B3
66A6
46B4
57A8
45D5
44D5
57C7
54D8
45D5
46B6
75D3
75D3
75D3
75D3
75D3
75D3
75D3
75D3
46B6
46C6
46C6
57C8
46C4
46B4
45C5
46B4
46B4
44C5
75C3
46C4
46B4
46B4
46B4
46B6
38C6
57C3
56C4
54C8
57A2
66A4
66A3
44C5
44C5
46B6
75C3
75D3
75C3
75C3
75C3
75C3
75C3
75C3
75C3
75C3
75C3
56A6
58A3
75C3
75D3
59B7
29D6
29B6
29B6
29D6
29D6
29D6
29D6
29D6
45C5
46B6
46B6
44C8
46C6
44C8
53C7
53C7
56A6
56A6
55D3
66C2
66A6
53B7
45D5
44C8
45C5
44B5
55C2
55C2
55C2
45A3
76C3
76C3
24D5
45C5
46B6
44B8
46C4
44C8
44C8
44C5
45D7
45C5
46B6
50C4
50B4
35C7
45B6
44A8
50C4
53A7
54B8
45C5
45B6
45B6
53C7
53C7
66A8
46B4
44B8
61B8
46C6
50C4
37A5
44C8
29B6
29C6
29C6
29C6
29C6
29C6
29C6
29C6
29B6
29B6
29C6
55C2
55C2
55D3
55D3 48B1
55C2
45D1
44D8
45D2
59B7
65C5
61B5
29C6
29B6
59A4
28C4
28A4
28A4
28C4
28C4
28C4
28C4
28C4
44B5
27D1
44C1
22D4
7A7
22D4
8A5
8A5
55B3
55B3
55B1
67D2
67D3
66B5
57C3
67D3
43A4
43C2
43C2
8B2
8B2
8B2
8B2
8A5
43A4
67D2
44B8
22D4
44B5
8D5
8D1
8D1
7D1
7B4
42C3
54D1
54C1
54C1
38D3
40C5
47C5
47C5
24A7
44B5
44D1
41A8
46C5
29B3
22D4
24C8
24D5
44C3
44B5
23B5
7A7
50B3
50C3
44A8
33C7
44C5
43C2
7D7
57B5
57A5
57A5
57A5
44A4
8D5
8D5
8D1
7C4
8D1
8D5
8D5
8D1
8D1
8D1
8D5
8D1
8D1
7A7
8A4
8B4
7A7
44C5
8D5
44C8
44C8
8A5
8A5
44B5
44C1
41A8
7D8
7B1
7B1
44A8
24C8
22D4
28A4
28B4
28B4
28B4
28B4
28B4
28B4
28B4
28A4
28B4
28B4
49B6
54B1
54B1
55A1
55B1
49D6
49D6
7C1
7B1
43D2
49C6
49B6
7A4
7A4
45D8
44C5
54C1
7C1
7B5
7A7
7D4
27A5
7C7
7B7
7D7
7D7
7D7
49C6
59A4
63B5
58B1
28B4
28B6
8D1
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
"G3H" RAILS
"S5" RAILS"S0,S0M" RAILS
(REGULATOR OUTPUT CPU 0.90V PWR)
(DDR2 TERMINATION 0.9V PWR)
(REGULATOR OUTPUT CPU VCORE PWR)
(CPU VCOR PWRE)
"S3" RAILS
051-745576
SYNC_DATE=06/15/2006
Power AliasesSYNC_MASTER=WFERRY
01
7
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=3.3V
PP3V3_S3
=PP3V3_S3_SMBUS_SMC_MGMT=PP3V3_ENET_P3V3ENETFET
=PPVCORE_S0_NB_GFX
=PP5V_S0_3G=PP5V_S0_LPCPLUS=PP5V_S0_ISENSECAL=PP5V_S0_FAN_RT=PP5V_S0_AUDIO=PP5V_S0_AUDIO_AMP=PP5V_S0_CPU_IMVP
=PP5V_S0_SB
VOLTAGE=5V
PP5V_S0MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
=PP5V_S0_NB_GFX_IMVP=PP5V_S0_LCD=PP5V_S0_TMDS=PP5V_S0_NB_TVDAC
=PP5V_S0_SATA
VOLTAGE=1.25V
PPVCORE_S0_NB_GFXMIN_LINE_WIDTH=0.5 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
=PP1V8_S0_NB_DPLL
MAKE_BASE=TRUE
PP1V8_S0MIN_LINE_WIDTH=0.4 mm
VOLTAGE=1.8VMIN_NECK_WIDTH=0.2 mm
=PP1V5_S0_NB_FOLLOW=PP1V5_S0_AIRPORT
=PP1V5_S0_SB_VCCUSBPLL=PP1V5_S0_SB_VCC1_5_A
=PP1V5_S0_SB_VCC1_5_A_ARX=PP1V5_S0_SB=PP1V5_S0_NB_TVDAC=PP1V5_S0_CPU
VOLTAGE=1.5V
PP1V5_S0
MIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
=PP1V25_S0_FET=PP1V25_S0_NB_VCCA=PP1V25_S0_NB_VCC=PP1V25_S0_NB_PLL=PP1V25_S0_NB_VCCAXF
=PP1V25_S0_NB_VCCDMI
=PP1V25_S0_NB_PLLMAKE_BASE=TRUE
PP1V25_S0
MIN_NECK_WIDTH=0.2 mmVOLTAGE=1.25V
MIN_LINE_WIDTH=0.6 mm
=PP1V05_S0M_NB_VCCAXM=PP1V25R1V05_S0_NB_VTT=PP1V25R1V05_S0_FSB_NB=PPVCORE_S0_NB=PP1V05_S0_NB_PCIE
MAKE_BASE=TRUEVOLTAGE=1.05VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mmPP1V05_S0_R
=PPVCORE_S0_SB
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
VOLTAGE=1.05VMAKE_BASE=TRUE
PP1V05_S0
=PP0V9_S3M_MEM_TERM
=PP3V3_S0_SB_VCC3_3_IDE=PP3V3_S0_SB_VCC3_3_VCCPCORE
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
PP3V3_S5
=PP3V3_S5_FET=PP3V3_S5_SB=PP3V3_S5_SB_GPIO=PP3V3_S5_SB_USB=PP3V3_S5_SB_PM
=PP3V3_S5_SB_VCCSUS3_3_USB=PP3V3_S5_SB_VCCSUS3_3=PP3V3_S5_SB_3V3_VCCSUSHDA=PP3V3_S5_FWLATEVG
=PP3V3_S5_SMBUS_SB_ME=PP3V3_S5_ROM=PP3V3_S5_LCD
=PP3V3_S5_1V25S0=PP3V3_S5_AIRPORT_AUX
VOLTAGE=5V
PP5V_S5MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUE
=PP5V_S5_SB
=PP5V_S5_USB
=PP5V_S5_PWRCTL=PP5V_S5_FET
VOLTAGE=3.42VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.3 mmPP3V42_G3H
=PP3V42_G3H_SMC=PP3V42_G3H_SMCVREF=PP3V42_G3H_SMBUS_SMC_BSA=PP3V42_G3H_ACIN=PP3V42_G3H_LIDSWITCH=PP3V42_G3H_PWRCTL=PP3V42_G3H_SB_RTC=PP3V42_G3H_SMCUSBMUX=PP3V42_G3H_LPCPLUS
VOLTAGE=18.5VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.6 MMPP18V5_G3H
=PP18V5_G3H_CHGR
MIN_LINE_WIDTH=0.6 mmPPDCIN_G3H
MAKE_BASE=TRUEVOLTAGE=18.5VMIN_NECK_WIDTH=0.2 mm
=PPVIN_G3H_P3V42G3H
PPBUS_G3H
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
VOLTAGE=18.5VMAKE_BASE=TRUE
=PPDCIN_G3H
=PPBUSA_G3H
=PP5V_S5_PATA
=PP5V_S5_1V8S30V9S0
=PP3V3_S0_AIRPORT
=PP3V3_S0_SB
=PP3V3_S5_REG
=PP3V3_S0_THRM_SNR
=PP18V5_G3H_INRUSH
=PP3V3_S5_SB_CLINK1
=PP3V3_S0_NB
=PP3V3_S0MWOL_SB_CLINK0
=PPSPD_S0_MEM
MIN_NECK_WIDTH=0.2 mm
PP1V2_ENET_S0
MAKE_BASE=TRUEVOLTAGE=1.2V
MIN_LINE_WIDTH=0.6 mm
=PP1V2_ENET_PHY=PP1V5_S0_SB_VCC1_5_A_ATX
=PP3V3_S0_PBATTISENS
=PPBUS_S5_FWPWRSW
=PP5V_S5_1V51V05S0
=PP3V3_S0_NB_FOLLOW=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S0_SB_PM=PP3V3_S0_RSTBUF
=PP3V3_S0_SMC_LS=PP3V3_S0_LPCPLUS=PP3V3_S0_SMBUS_SB
=PP3V3_S0_LCD
=PPVIN_S5_IMVP
=PPVIN_S5_1V5S0=PPVIN_S5_1V05S0
=PPVIN_S5_5VS5=PPVIN_S5_3V3S5
=PPVIN_S5_1V8S30V9S0=PPBUS_S5_INV
=PP3V3_S0_PATA
=PP3V3_S0_SMBUS_SMC_0_S0=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_FW
=PP3V3_S0_SB_VCC3_3_DMI
PPVCORE_S0_CPU
VOLTAGE=0.9VMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 mmMIN_NECK_WIDTH=0.3 MM
=PPVORE_S0_CPU_REG
=PP0V9_S0_REG
=PPVCORE_S0_CPU
=PPVIN_S5_NB_GFX_IMVP=PPVIN_S5_CPU_IMVP
=PPVCORE_S0_NB_GFX_IMVP
=PP1V8_S0_TMDS
=PP1V8_S0_FET
=PP1V5_S0_REG
=PP5V_S3_IR=PP5V_S3_GEYSER=PP5V_S3_SYSLED
=PP3V42_G3H_REG
=PP5V_S5_REG
=PP5V_S3_CAMERA
=PP1V25_S0_REG
=PP5V_S0_FET
=PP1V05_S0_REG
=PP1V05_S0_REG_R
=PP3V3_S0_SB_VCCGLAN3_3
=PP3V3_S0_PDCISENS
=PP3V3_S0_CPUPOWER
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
PP1V9_ENET_S0MIN_LINE_WIDTH=0.6 mm
VOLTAGE=2.5V
=PPBUSB_G3H
=PP3V3_S0MWOL_SB_VCCLAN3_3
=PPVIN_S0_NB_DPLL
=PP3V3_S0MWOL_SB_VCCCL3_3
=PP3V3_S0_FET
=PP3V3_S0_NB_VCCHV
=PP3V3_S0_SB_VCC3_3_SATA
=PP5V_S3_FET
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
MIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
PP3V3_S0MIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3V
=PP3V3_S0_SB_PCI
=PP3V3_S0_TMDS
=PP3V3_S0_AUDIO
=PP3V3_S0_FAN_RT=PP3V3_S0_ENET
=PP3V3_S0_IMVP=PP3V3_S0_NB_GFX_IMVP
=PP1V8_S0_YUKON
=PP1V8R2V5_ENET_PHYPP3V3_ENET_FETMIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mmVOLTAGE=3.3VMAKE_BASE=TRUE
=PP1V8_S0_NB_LVDS
=PP5V_S0_IDE_RESET
=PP3V3R1V5_S0_SB_VCCHDA
=PP3V3_S0_NB_VCCA_PEG_BG
=PP3V3_S0_CK505=PP3V3_S0_NB_VCCSYNC
=PP3V3_S0_TMDS
=PP1V9_ENET_REG
=PP1V8_S3_MEMVREF=PP1V8_S3_FET
=PP1V8_S3_MEM
=PP1V8_S3M_MEM_NB
=PP1V8_S3_REG
=PP1V8_S3_NB_VCC
=PP3V3_S3_PDCISENS=PP3V3_S3_SMBUS_SMC_A_S3
VOLTAGE=1.8VMAKE_BASE=TRUE
MIN_NECK_WIDTH=0.4 mmMIN_LINE_WIDTH=0.6 mm
PP1V8_S3_MEM_NB
PP5V_S3
VOLTAGE=5VMIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm
MAKE_BASE=TRUE
=PP3V3_S3_ENETPWRCTL
=PP3V3_S3_FET
VOLTAGE=0.9V
PP0V9_S0MIN_LINE_WIDTH=0.4 mm
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mm
=PP1V05_S0_SB_CPU_IO
=PP1V05_S0_CPU
=PP1V25_S0_SB_DMI
=PP1V2_ENET_REG
=PP3V3_ENET_PHY
=PP1V8_S3_REG_R
=PP3V3_S3_AIRPORT_AUX=PP3V3_S3_FW=PP3V3_S3_PCI=PP3V3_S3_BT=PP3V3_S3_SMS
=PP1V8_ENET_P1V8ENETFET
PP1V8_S3MIN_LINE_WIDTH=0.6 mmMIN_NECK_WIDTH=0.2 mm
MAKE_BASE=TRUEVOLTAGE=1.8V
69C8
69C8
69C2
69C2
12C5
69B7
69B7
12B3
58D3
68D8
68D8
31D6
11A3
51B8
48B5
58C4
21B7
68C8
29D2
68C8
31D4
31D2
10C7
48B3
54D8
20D8
35C7
65B5
45D8
66B8
24D8 48B3
59D8
58C3
20A8
68B7
56B5
29B2
68B7
31B2
30D2
9D5
21C5
56C4
54C8
26D6
20D3
20D3
20D8
29C6
20B4
26C6
65C4
26D8
26D2
33D7
58D5
45D4
66A8
31A7
24B3
67C6
11D7
59D4
66C3
58B8
18B3
68B2
55D8
28D8
68B2
30D6
20C8
26C4
9C5
51B6
17D5
46C6
50C4
53A7
54B8
26B6
26C2
26D5
26C8
11B3
20B4
20A8
20B4
17C1
20C8
29B6
17D7
26D2
45D2
26B4
26A6
65A5
24A8
26D2
26B6
26B2
38A8
33D6
58C6
45C1
66A5
46C6
39C8
49D2
31A3
26C6
22D7
26B4
27B8
67B7
63B6
26A8
10D7
59C2
58C4
62C5
45A4
58D4
61B8
61C5
26D3
26B2
58B3
15C7
26B8
26C2
45D1
68B1
53D7
50C4
26C4
20A6
28D3
21B5
68B1
35D1
20A6
30D4
17D7
62C2
65C3
25C3
9B6
26A6
6A2
47C3
35D3
17B7
43B5
6D2
48B8
6D2
6D1
6D1
59D8
26D8
6A2
60D2
67D7
69D7
21D6
40C6
21A7
6B2
21D5
33D2
25A6
25B6
25B6
26A8
21D8
10B7
6B2
58A3
20B8
20A8
7C7
20D4
18C3
7C7
17B3
18D3
13B7
17D3
20D5
6B2
25D3
6B2
32D4
25C3
25C3
6A2
58C5
24A3
24D8
23C8
27C5
25A3
25A3
25B3
38A6
47A7
52C6
67C7
64B6
33C7
6A2
26D8
41C8
65B6
58B3
6A2
44D4
45C8
47C3
57C4
57A8
65C7
27D7
41A6
6D2
6A2
66D8
64C6
6A2
57D3
66C2
39D6
62C5
33C6
26D8
63B1
49C2
57D1
24B1
69C8
24C1
30A7
6A2
34D6 25B6
66B3
38D5
61C4
20B2
22D2
25B3
27B6
27D4
45D4
46C4
47D8
67B5
45A6
61B3
61B5
63A6
63B3
62B3
67D4
39C2
47D5
47C5
38C6
25C3
6B2 59D1
62B8
10B5
60C2
48D7
60C2
68D6
58B8
61B1
43D8
42D6
40B6
64C4
63B8
67A5
64B2
58C8
6B2
61C7
25A6
60C2
48D2
66C2
25A3
25A6
58A3
15B7
25C3
65B4
25B6
6A2
23A3
7C4
53A7
6D2
8A4
59D8
60C7
36D8
34C7 35D4
21C5
39B7
25B3
18C6
28C8
18D6
7C4
35B2
20A5
58C5
30B2
15D2
62B2
20A4
62A2
47D3
6A2
35D7
65A4
6A2
22D2
9B5
25C3
35C1
34D6
62C4
33C2
37D5
37C5
43D3
51C7
35C3
6A2
TABLE_5_ITEM
TABLE_5_ITEM
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
TABLE_5_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
FOR LAYOUT PLACEMENT
BUT, NEED CHANGE TO HIGH STANDOFF SYMBOL
CPU HEATSINK STANDOFF SCREW HOLE
Z0903 USE SAME Z0913 NON SHAPE OF A HOOF SYMBOL NB CFG ALIASES
DCIN CONNECTOR CHASSIS GND
NO-CONNECT UNUSED LVDS INTERFACE PORTS
(EMI PAD FOR INVERTER GONNECTOR)
DIP DIMM CONNECTOR CHASSIS GND
USB PORT [0] = External USB2.0 Port A
USB PORT [1] = PCI-E Mini Card
USB PORT [2] = 3G USB
USB PORT [3] = CAMERA
USB PORT [4] = IR CONTROLLER
USB PORT [5] = Trackpad(Geyser)
USB PORT [6] = BLUETOOTH
NO-CONNECT UNUSED FIREWIRE INTERFACE PORTS
ANALOG SWITCH GPIO
NB ALIASES
USB PORT [9] = Unused
USB PORT [8] = Unused
USB PORT [7] = External USB2.0 Port B
SO-DIMM ALIASES
PCI_EXP ALIASES
SATA ALIASESNO-CONNECT UNUSED SATA INTERFACE PORTS
NO-CONNECT UNUSED PCI_EXP INTERFACE PORTS
NO-CONNECT UNUSED SDVO INTERFACE PORTS
NO-CONNECT UNUSED ADDRESS INTERFACE PORTS
FIREWIRE ALIASES
DIP DIMM CONNECTOR CHASSIS GND
NC NC
I/O CONNECTOR CHASSIS GND
PCI_EXPRESS GRAPHICS ALIASES
AIRPORT CARD STANDOFF SCREW HOLE
Ethernet ALIASES
SATA,LVDS CONNECTOR CHASSIS GND
LVDS ALIASES
NO-CONNECT UNUSED CLOCK INTERFACE PORTSCLOCK ALIASES
NO-CONNECT UNUSED CLOCK INTERFACE PORTS
SB ALIASES
BATTERY,AUDIO,DIP DIMM CONNECTOR CHASSIS GNDCHASSIS GND
15R2P3-7SQBNP
OMITZ0906
Z09021
7X7R2P3-5B
OMIT
C09081
2
0.01UF10%16VCERM402
C09071
2 X5R16V10%
402
0.1UF
15R2P3-7SQBNP
OMITZ0901
Z09091
5R2P3-7SQB
OMIT
Z09111
OMIT
5R2P3-7B
Z09101
OMIT
5R2P3-7SQB
R09121
2
5%01/16WMF-LF402
Z09131
OMIT
STDOFF-4.2OD3.95H-5.52R3.37-6BZ09121
OMIT
STDOFF-4.2OD2.15H-1.2-3.2-TH
Z09081
OMIT
5P0R2P3-7BLB
ZS09201 EMI-SPRINGCLIP-SM-M42
Z09041
OMIT
STDOFF-4.2OD3.95H-5.52R3.37-7SQB
Z09211
OMIT
STDOFF-4.5OD3.95H-1.1-3.2-TH
Z09071
OMIT
6P5R2P6-7SQB
Z09031
OMIT
STDOFF-4.2OD3.95H-5.52R3.37-6B
C09301
2
0.1UFX5R10%16V
402
C09101
2 16VX5R402
10%0.1UF
C09111
2402CERM16V10%0.01UF
C09161
2402
16V10%0.1UFX5R
C09171
2
0.01UF10%16V402CERM
C09141
2 16V10%
402
0.1UFX5R
C09151
210%
402
0.01UF16VCERM
C09121
2 X5R
0.1UF10%16V
402
C09131
2402
10%0.01UFCERM16V
C09181
2402
10%X5R16V0.1UF C09191
2
0.01UF10%16VCERM402
R09101
2MF-LF
5%1/16W
402
0
R09211
2
1/16WMF-LF402
5%0
Z09051
OMIT
STDOFF-4.5OD3.95H-1.1-3.2-TH
R09111
2
1/16W
05%
MF-LF402
XW08021 2
SM
XW08011 2
SM
4 STANDOFFZ0903,Z0904,Z0905,Z0921860-0876 THERMAL STANDOFF
1860-0723 STANDOFFZ0912STANDOFF WIRELESS
860-0749 1 STANDOFFZ0913STANDOFF W/THRU HOLES,WIRELESS
051-7455
SYNC_DATE=07/17/2006
76
01
8
SIGNAL ALIAS /RESETSYNC_MASTER=GPU
=GND_CHASSIS_DIPDIMM_LEFT
=GND_CHASSIS_AUDIO_MIC
=GND_CHASSIS_AUDIO_JACK
=GND_BATT_CHGND
GND_CHASSIS_IOSATA_C_R2D_C_P_SPN
MAKE_BASE=TRUE
SATA_C_D2R_N_SPNMAKE_BASE=TRUE
FW_B_TPA_P
TP_HDA_SDIN2CPU_THERMAL_SCREW_UP
=GND_CHASSIS_TMDS_UPPER
=GND_CHASSIS_RJ45
GND_CHASSIS_DCINMAKE_BASE=TRUEVOLTAGE=0V
=GND_CHASSIS_LVDS
=GND_CHASSIS_3GPOWERMAKE_BASE=TRUE
LVDS_B_CLK_P_SPNLVDS_B_DATA_N0_SPN
MAKE_BASE=TRUE
=GND_CHASSIS_FW_DOWN=GND_CHASSIS_USB
USB_EXTA_P
USB_EXTA_N
MAKE_BASE=TRUE
USB2_3G_P=USB2_3G_P
MAKE_BASE=TRUEEXTAUSB_OC_L
USB2_AIRPORT_NMAKE_BASE=TRUE
USB2_CAMERA_PMAKE_BASE=TRUE
USB2_CAMERA_NMAKE_BASE=TRUE
MAKE_BASE=TRUE
USB_IR_P
MAKE_BASE=TRUE
USB_IR_N
MAKE_BASE=TRUEUSB2_GEYSER_P
MAKE_BASE=TRUEUSB2_GEYSER_N
USB_BT_PMAKE_BASE=TRUE
USB_BT_NMAKE_BASE=TRUE
=USB2_IR_P
MEM_CLK_P_5_SPNMAKE_BASE=TRUE
=PP3V3_S0_ENET
=YUKON_EC_PP2V5_ENET
MAKE_BASE=TRUEHDN_SPIN3_SPN MAKE_BASE=TRUEHDN_SPIN2_SPN MAKE_BASE=TRUEHDN_SDIN1_SPN
TP_HDA_SDIN3
NB_CFG<3>
NB_CFG<4>
NB_CFG<6>NB_CFG<7>
NB_CFG<8>
=GND_CHASSIS_TMDS_DOWN
=GND_CHASSIS_FW_UPPER
MAKE_BASE=TRUETP_NB_CFG<3>
MAKE_BASE=TRUEACZ_SYNCACZ_BITCLK
MAKE_BASE=TRUE
MEM_A_A15_SPNMAKE_BASE=TRUE
=NB_TDB_FORCE
=NB_TDE_SENSE
=NB_CLK96M_DOT_P
=GFX_VR_EN
MAKE_BASE=TRUEPM_EXTTS_L<1>
MAKE_BASE=TRUE
TP_USB_EXTC_N
=USB2_EXTA_N
TP_MEM_CLKN5 MEM_CLK_N_5_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEPEG_D2R_P10_SPN
PEG_D2R_P<9>PEG_D2R_P<8>PEG_D2R_P<7>
PEG_D2R_P<5>PEG_D2R_P<4>
PEG_D2R_P<0>PEG_D2R_N<15>
PEG_D2R_N<13>
PEG_D2R_N<6>
TP_LVDS_B_DATAP3
=NB_CLK100M_DPLLSS_P=NB_CLK100M_DPLLSS_N
=NB_TDE_FORCE
=NB_CLK96M_DOT_N
MAKE_BASE=TRUENB_CLK100M_DPLLSS_N MAKE_BASE=TRUE
NB_CLK100M_DPLLSS_P MAKE_BASE=TRUE
NB_CLK96M_DOT_N
NB_CLK96M_DOT_PMAKE_BASE=TRUE
CLINK_MPWROKMAKE_BASE=TRUE
GFX_VR_ENMAKE_BASE=TRUE
PM_EXTTS_L<0>MAKE_BASE=TRUE
MEM_CLK_N_2_SPNMAKE_BASE=TRUE
MEM_B_A15_SPNMAKE_BASE=TRUE
SATA_B_R2D_C_N
SATA_C_D2R_P
MAKE_BASE=TRUE
TP_USB_EXCARD_P
MAKE_BASE=TRUE
TP_USB_EXCARD_N
EXTBUSB_OC_LMAKE_BASE=TRUE
USB2_EXTB_NMAKE_BASE=TRUE
USB2_EXTB_PMAKE_BASE=TRUE
=USB2_BT_N
MAKE_BASE=TRUESATA_B_D2R_N_SPN
SATA_C_R2D_C_N_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEPCIE_A_D2R_N_SPNTP_PCIE_A_D2R_N
=NB_CLINK_MPWROK
DIMM_OVERTEMPA_L
DIMM_OVERTEMPB_L
MAKE_BASE=TRUELVDS_A_DATA_N3_SPN
LVDS_B_DATA_N2_SPNMAKE_BASE=TRUE
=GND_AUDIO_AMP
MEM_CLK_P_2_SPNMAKE_BASE=TRUE
USB_EXTC_P
USB_EXTC_N
HDA_SDOUT
PEG_R2D_C_P<15>
HDA_RST_LHDA_SDIN0
MAKE_BASE=TRUEPEG_R2D_C_P7_SPN
MAKE_BASE=TRUEPEG_R2D_C_P8_SPNPEG_R2D_C_P9_SPN
MAKE_BASE=TRUE
MAKE_BASE=TRUEPEG_R2D_C_P4_SPNMAKE_BASE=TRUEPEG_R2D_C_N15_SPN
MAKE_BASE=TRUEPEG_R2D_C_N8_SPN
MAKE_BASE=TRUEPEG_R2D_C_N6_SPN
PEG_R2D_C_N4_SPNMAKE_BASE=TRUE
PEG_D2R_P14_SPNMAKE_BASE=TRUE
PEG_R2D_C_N5_SPNMAKE_BASE=TRUEPEG_R2D_C_N<6>
PEG_R2D_C_N<7>PEG_R2D_C_N<8>
PEG_R2D_C_N<10>PEG_R2D_C_N<11>PEG_R2D_C_N<12>
MAKE_BASE=TRUEPEG_R2D_C_N13_SPN
MAKE_BASE=TRUEPEG_R2D_C_P5_SPN
MAKE_BASE=TRUEPEG_R2D_C_P6_SPN
MAKE_BASE=TRUEPEG_R2D_C_N9_SPN
MAKE_BASE=TRUEPEG_R2D_C_N7_SPN
MAKE_BASE=TRUEPEG_D2R_P13_SPNPEG_D2R_P12_SPN
MAKE_BASE=TRUE
PEG_D2R_P11_SPNMAKE_BASE=TRUE
TP_PCIE_A_R2D_C_P
TP_PCIE_B_D2R_P
TP_PCIE_FW_R2D_C_P
MAKE_BASE=TRUEPEG_D2R_P5_SPN
MAKE_BASE=TRUEPEG_D2R_N14_SPN
MAKE_BASE=TRUEPCIE_D_R2D_C_P_SPNMAKE_BASE=TRUEPCIE_D_R2D_C_N_SPN
MAKE_BASE=TRUEPCIE_C_D2R_P_SPN
TP_PCIE_B_D2R_N
MAKE_BASE=TRUEPCIE_B_R2D_C_P_SPN
MAKE_BASE=TRUEPCIE_C_D2R_N_SPN
TP_PCIE_A_R2D_C_N
SATA_C_D2R_P_SPNMAKE_BASE=TRUE
SATA_B_R2D_C_N_SPNMAKE_BASE=TRUESATA_B_R2D_C_P SATA_B_R2D_C_P_SPNMAKE_BASE=TRUE
SATA_B_D2R_PMAKE_BASE=TRUE
SATA_B_D2R_P_SPNSATA_B_D2R_N
MAKE_BASE=TRUEPEG_D2R_N0_SPNPEG_D2R_N2_SPN
MAKE_BASE=TRUE
PEG_R2D_C_P<7>
MAKE_BASE=TRUELVDS_B_DATA_P0_SPN
FW_C_TPB_N
PEG_D2R_P4_SPNMAKE_BASE=TRUE
PEG_D2R_P<6>
MAKE_BASE=TRUEPEG_D2R_N15_SPN
FW_B_TPBIAS_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEFW_B_TPA_P_SPN
MAKE_BASE=TRUEFW_B_TPB_N_SPN
FW_C_TPA_PFW_C_TPA_NFW_C_TPB_P
GND_CHASSIS_CPU
MAKE_BASE=TRUEFW_C_TPB_N_SPNFW_C_TPB_P_SPN
MAKE_BASE=TRUE
FW_C_TPA_N_SPNMAKE_BASE=TRUE
FW_C_TPA_P_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEFW_C_TPBIAS_SPN
MAKE_BASE=TRUEFW_B_TPA_N_SPN
FW_B_TPB_NFW_C_TPBIAS
FW_B_TPB_P
FW_B_TPBIAS
FW_B_TPA_N
PEG_D2R_P0_SPNMAKE_BASE=TRUE
PEG_D2R_P<15>
=GND_CHASSIS_DIPDIMM_CENTER
GND_CHASSIS_FANSCREW
=GND_DCIN_CHGND
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_BT_P
USB_BT_N
USB_EXCARD_P
USB_EXTB_OC_L
USB_EXTA_OC_LMAKE_BASE=TRUE
USB2_EXTA_NMAKE_BASE=TRUE
USB2_EXTA_P=USB2_EXTA_P
=EXTAUSB_OC_L
USB_MINI_P
USB_MINI_NMAKE_BASE=TRUE
USB2_AIRPORT_P=USB2_AIRPORT_P
=USB2_AIRPORT_N
USB_EXTD_NUSB_EXTD_P
USB2_3G_NMAKE_BASE=TRUE
=USB2_3G_N
USB_CAMERA_P
USB_CAMERA_N
=USB2_CAMERA_P
MAKE_BASE=TRUEVOLTAGE=0V
GND_CHASSIS_RIGHT
=EXTBUSB_OC_L
=USB2_EXTB_P
=USB2_BT_P
=USB2_GEYSER_P
TP_PCIE_A_D2R_P
NB_RIGHT_DOWN_SCREW
MAKE_BASE=TRUEPEG_R2D_C_N14_SPN
CPU_THERMAL_SCREW_DOWN
GND_CHASSIS_CENTERMAKE_BASE=TRUEVOLTAGE=0V
PEG_D2R_N<0>
=USB2_EXTB_N USB_EXTB_N
=USB2_IR_N
USB_EXCARD_N
PEG_D2R_P8_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEVOLTAGE=0V
GND_CHASSIS_IO
=USB2_CAMERA_N
=USB2_GEYSER_N
TP_LVDS_A_DATAP3
PEG_D2R_P6_SPNMAKE_BASE=TRUE
PEG_D2R_N8_SPNMAKE_BASE=TRUE
LVDS_B_CLK_N LVDS_B_CLK_N_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUELVDS_B_DATA_N3_SPN
LVDS_B_DATA_N<0>LVDS_B_CLK_P
MAKE_BASE=TRUELVDS_B_DATA_P1_SPN
LVDS_B_DATA_N1_SPNMAKE_BASE=TRUE
LVDS_B_DATA_N<1>LVDS_B_DATA_N<2>TP_LVDS_B_DATAN3
LVDS_B_DATA_P<0>LVDS_B_DATA_P<1>
PEG_D2R_N<7>PEG_D2R_N<8>PEG_D2R_N<9>PEG_D2R_N<10>PEG_D2R_N<11>PEG_D2R_N<12>
PEG_D2R_N<14>
PEG_D2R_P<2>PEG_D2R_P<3>
PEG_D2R_P<10>PEG_D2R_P<11>PEG_D2R_P<12>PEG_D2R_P<13>PEG_D2R_P<14>
PEG_R2D_C_N<4>PEG_R2D_C_N<5>
PEG_R2D_C_N<9>
PEG_R2D_C_N<13>PEG_R2D_C_N<14>PEG_R2D_C_N<15>PEG_R2D_C_P<4>PEG_R2D_C_P<5>PEG_R2D_C_P<6>
PEG_R2D_C_P<8>PEG_R2D_C_P<9>PEG_R2D_C_P<10>PEG_R2D_C_P<11>PEG_R2D_C_P<12>PEG_R2D_C_P<13>PEG_R2D_C_P<14>
PEG_R2D_C_P11_SPNMAKE_BASE=TRUE
PEG_R2D_C_P10_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEPEG_R2D_C_N10_SPN
MAKE_BASE=TRUEPEG_R2D_C_N11_SPN
MAKE_BASE=TRUEPEG_R2D_C_N12_SPN
PEG_D2R_P9_SPNMAKE_BASE=TRUE
PEG_D2R_P2_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEPEG_D2R_N6_SPN
PEG_D2R_N3_SPNMAKE_BASE=TRUE
SATA_C_D2R_N
PCIE_B_D2R_N_SPNMAKE_BASE=TRUE
PCIE_A_R2D_C_P_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEPCIE_A_R2D_C_N_SPNPCIE_A_D2R_P_SPN
MAKE_BASE=TRUE
SATA_C_R2D_C_PSATA_C_R2D_C_N
TP_PCIE_FW_D2R_P
TP_HDA_SDIN1
HDA_SYNCHDA_BIT_CLK
MAKE_BASE=TRUE
TP_USB_EXTC_P
PEG_R2D_C_P12_SPNMAKE_BASE=TRUEPEG_R2D_C_P13_SPNMAKE_BASE=TRUEPEG_R2D_C_P14_SPNMAKE_BASE=TRUEPEG_R2D_C_P15_SPNMAKE_BASE=TRUE
TP_NB_CFG<4>MAKE_BASE=TRUE
MAKE_BASE=TRUETP_NB_CFG<6>
MAKE_BASE=TRUETP_NB_CFG<7>
MAKE_BASE=TRUETP_NB_CFG<8>
LVDS_B_DATA_P<2>
MAKE_BASE=TRUEVOLTAGE=0V
GND_CHASSIS_SATA
VOLTAGE=0VGND_CHASSIS_IO1MAKE_BASE=TRUE
PEG_D2R_N7_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEACZ_RST_L
MAKE_BASE=TRUEACZ_SDATAIN<0>
MAKE_BASE=TRUEACZ_SDATAOUT
=GND_AUDIO_CODEC
MEM_A_A<15>
TP_MEM_CLKP5
TP_LVDS_A_DATAN3
CPU_THERMAL_SCREW_RIGHT
MAKE_BASE=TRUEFW_B_TPB_P_SPN
USB_EXTB_P
=NB_TDB_SENSE
MAKE_BASE=TRUELVDS_B_DATA_P3_SPNMAKE_BASE=TRUELVDS_B_DATA_P2_SPN
MAKE_BASE=TRUELVDS_A_DATA_P3_SPN
PEG_D2R_N4_SPNMAKE_BASE=TRUEPEG_D2R_N5_SPNMAKE_BASE=TRUE
PEG_D2R_N<5>PEG_D2R_N<4>PEG_D2R_N<3>PEG_D2R_N<2>
VOLTAGE=0VINVT_CHGND
MAKE_BASE=TRUE
TP_MEM_CLKN2
TP_MEM_CLKP2
=ENET_VMAIN_AVLBL
MAKE_BASE=TRUE
GND_AUDIO_AMP
MAKE_BASE=TRUE
GND_AUDIO_CODEC
MEM_B_A<15>
MAKE_BASE=TRUEPEG_D2R_P7_SPN
MAKE_BASE=TRUEPEG_D2R_P15_SPN
MAKE_BASE=TRUEPCIE_D_D2R_P_SPNMAKE_BASE=TRUEPCIE_D_D2R_N_SPNPCIE_C_R2D_C_P_SPN
MAKE_BASE=TRUE
TP_PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_R2D_C_NTP_PCIE_EXCARD_R2D_C_P
PEG_D2R_N13_SPNMAKE_BASE=TRUE
PEG_D2R_N9_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUEPEG_D2R_N10_SPN TP_PCIE_FW_R2D_C_N
TP_PCIE_FW_D2R_N
MAKE_BASE=TRUEPCIE_C_R2D_C_N_SPN
MAKE_BASE=TRUEPCIE_B_R2D_C_N_SPNMAKE_BASE=TRUEPCIE_B_D2R_P_SPN
MAKE_BASE=TRUECLINK_MPWROK=SB_CLINK_MPWROK MAKE_BASE=TRUEVR_PWRGD_CK505VR_PWRGD_CLKEN
MAKE_BASE=TRUESB_CLK100M_SATA_OE_LSB_SATA_CLKREQ_L
MAKE_BASE=TRUETP_SB_GPIO17EXTGPU_RST_L
TP_CK505_SRC1_NTP_CK505_SRC1_PTP_CK505_SRC3_N
MAKE_BASE=TRUECK505_SRC1_N_SPN
CK505_SRC3_N_SPNMAKE_BASE=TRUE
CK505_SRC1_P_SPNMAKE_BASE=TRUE
MAKE_BASE=TRUECK505_PCI4_CLK_SPN
MAKE_BASE=TRUECK505_SRC7_P_SPN
MAKE_BASE=TRUECK505_PCI2_CLK_SPN
MAKE_BASE=TRUECK505_SRC7_N_SPN
CK505_PCI2_CLKTP_CK505_SRC7_P
CK505_PCI4_CLK
TP_CK505_SRC7_NCK505_SRC3_P_SPN
MAKE_BASE=TRUETP_CK505_SRC3_PMAKE_BASE=TRUE
PEG_D2R_P3_SPN
MAKE_BASE=TRUEPEG_D2R_N12_SPN MAKE_BASE=TRUEPEG_D2R_N11_SPN
TP_PCIE_EXCARD_D2R_N
TP_PCIE_B_R2D_C_P
TP_PCIE_B_R2D_C_N
MAKE_BASE=TRUEENET_CLKREQ_L=ENET_CLKREQ_L
=GND_CHASSIS_DIPDIMM_RIGHT
56C4 56B8 56B5
56B4 56B1 56A8 56A4 55B3
54C8 54B8
67B2
41C4
73B3
73B3
54C8
54A8
67A6
41C2
23C2
23C2
54B8
73B3
73B3
73B3
73B3
53D3
69C4
67A4
43B5
41A4
73B3
73B3
8C1
8C1
53C7
53C7
44B8
75B3
75B3
75B3
75B3
27A6
44B8
54A8
73B3
73B3
73B3
73C3
73C3
31A5
73B3
73B3
23C2
23C2
23C2
23C2
73B3
73B3
73B3
73B3
73B3
73B3
73B3
73C3
73C3
53B7
53C7
53C7
53B7
73B3 27A6
24C5
75D3
75D3
34B8
30A5
56A4
55C3
57A6
37B3
22C8
69A4
36B2
67A2
43A5 6A7
6A7
38B1
41A2
23C2
23C2
43A4
43C4
7C4
34C7 22C8
15B6
15B6
15B6
15B6
15B6
69A3
38B1
6C1
6C1
19C2
19D2
15C3
15B3
15B7
6C1
41A8
15C6
14C3
14C3
14C3
14C3
14C3
14C3
14C3
14C3
14D3
15C6
15C3
15C3
19C2
15C3
29C3
29C3
29B3
29B3
8B3
60C6
15B7
22B6
22B6
6C1
6C1
43C3
23D5
15A3
30C4
31C4
6A7
54A5
23C2
23C2
22B8
14A3
22C8
22C8
14B3
14B3
14B3
14B3
14B3
14B3
23D5
23D5
23D5
23D5
23D5
22B6
22B6
22B6
14B3
37B3
14C3
6B7
6B7
6B7
37B3
37B3
37B3
6B7
6B7
6B7
6B7
6B7
6B7
37B3
37B3
37B3
37B3
37B3
14C3
30D5
57C8
23C2
23C2
8C2
8C2
8C2
8B2
23C2
23C8
23C8
41A8
41C8
23C2
23C2
33B3
33B3
23C2
23C2
43A4
23C2
23C2
67B4
41C8
41B5
43C3
42C7
23D5
14D3
41B5 23C2
43C4
23C2
8D7
67A4
42C7
15C6
14C5 6A7
14C5
14C5
6A7
6A7 14C5
14C5
15C6
14C5
14C5
14D3
14D3
14D3
14C3
14C3
14C3
14C3
14C3
14C3
14C3
14C3
14C3
14C3
14C3
14B3
14B3
14B3
14B3
14B3
14B3
14B3
14B3
14B3
14B3
14B3
14B3
14B3
14A3
14A3
14A3
22B6
22B6
22B6
23D5
22C8
22C8
22C8
6C1
14C5
40C8
6C1
6D1
6D1
53A7
30C4
15C6
15C6
6B7
23C2
19C2
6A7
14D3
14D3
14D3
14D3
67C2
15C6
15C6
34C2
6D1
6D1
31C4
23D5
23D5
23D5
23D5
23D5
8B1 24C3
27A8 24C5
28B4 24C5
24B5
28B4
28B4
28B4
28B6
28B4
28B6
28B4
28B4
23D5
23D5
23D5
28A4
31D4
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
BI
BI
BI
BI
LOCK*
INIT*
A20M*
A6*
A3*
A4*
A14*
A16*
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
BCLK1
BCLK0
THERMTRIP*
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM2*
BPM1*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BNR*
RSVD9
RSVD8
RSVD7
RSVD6
RSVD5
RSVD4
RSVD3
RSVD2
RSVD1
RSVD0
SMI*
LINT1
LINT0
STPCLK*
FERR*
ADSTB1*
A35*
A34*
A33*
A32*
A31*
A30*
A29*
A28*
A19*
A18*
A17*
ADSTB0*
A13*
A12*
BPRI*
A20*
A21*
A22*
A23*
A24*
A26*
A27*
A9*
A8*
A7*
A11*
A25*
THERMDC
IGNNE*
ADS*
A10*
A15*
A5*
NC
1 OF 4
CONTROL
THERMAL
XDP/ITP SIGNALS
H CLK
RESERVED
ADDR GROUP0
ADDR GROUP1
ICH
DINV1*
D31*
D30*
D25*
D11*
D12*
D13*
D14*
DSTBP0*
DINV0*
D9*
D8*
D7*
D6*
D19*
D18*
DATBP1*
D0* D32*
D1*
D2*
D5*
D16*
D20*
D21*
D22*
D23*
D24*
D26*
D27*
D28*
D29*
DSTBN1*
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
BSEL0
BSEL1
BSEL2
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
COMP0
COMP1
COMP2
COMP3
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
D17*
D4*
D3*
DSTBN0*
D15*
D10*
2 OF 4
DATA GRP 3
DATA GRP 2
MISC
DATA GRP 0
DATA GRP 1
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
NC
LAYOUT NOTE:
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP0,2 CONNECT WITH ZO=27.4OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP1,3 CONNECT WITH ZO=55OHM,
PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)
0.1" AWAY
PLACE TESTPOINT ON
FSB_IERR_L WITH A GND
0.5" MAX LENGTH FOR CPU_GTLREF
REFERENCED TO GND
PLACE C1000 CLOSE TO CPU_TEST4
PIN. MAKE SURE CPU_TEST4 IS
R10021
2
1%1/16W
54.9
MF-LF402
R10041
2
685%1/16W
402MF-LF
R10051
2
1/16W1%
MF-LF
1K
402
R10061
2
1%
MF-LF
2.0K
1/16W
402
R1019
1%
MF-LF1/16W
54.9
402
R101827.4
1/16WMF-LF
1%
402
R1017
1%
MF-LF1/16W
54.9
402
R1016
1%
MF-LF1/16W
27.4
402
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B3 70C3
13A3 70C3
13B3 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B5 70C3
13B3 70C3
13A3 70C3
13B3 70C3
15B6 22C4 59C7 70B3
22C4 70B3
13B3 70D3
13A5 70B3
27B3
12B1 22C4 70C3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13D5 70D3
13C5 70D3
13C5 70D3
13C5 70D3
13B3 70D3
13B3 70D3
13B3 70D3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13C5 70C3
13B3 70C3
13B3 70C3
13B3 70C3
29B6 70B3
29A6 70B3
29C6 70B3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13D3 70C3
13C3 70C3
13C3 70C3
13A3 70C3
13A3 70C3
13A3 70C3
13A3 70C3
13A3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70D3
13C3 70D3
13C3 70D3
13B3 70D3
13B3 70D3
13B3 70D3
13B3 70D3
13B3 70D3
13B3 70D3
13B3 70D3
12B2 70A3
12B2 70A3
12B2 70A3
12B3 70A3
12B2 70A3
12B2 70A3
9A7 12B5 70B3
12B4 27C6
45B5 45C3 59C8 70C3
49B7
15A6 22C2 45B3 70B3
22C4 46B2 70B3
12B5 13A5 70D3
13A3 70D3
13A3 70D3
13A3 70D3
13B3 70D3
9A7 12B2 12B3 70B3
9B7 12B3 70B3
9B7 12B2 70B3
9A7 12B3 70A3
49C7
29D3 75C3
29D3 75C3
22C4 70C3
22C4 70B3
22C4 70C3
22C4 70C3
22C4 70B3
22C4 70B3
22C2 70C3
R10300
1/16WMF-LF
5%
NOSTUFF
402 R10071
2
1/16W5%
MF-LF
1K
NOSTUFF
402
R10031
2
1/16W1%
MF-LF
54.9
402
R1020
1%
MF-LF1/16W
54.9
402
R102154.9
1/16WMF-LF
1%
402
R102254.9
1/16WMF-LF
1%
402
13C3 70C3
13C3 70C3
13C3 70C3
13C3 70C3
R1023649
1/16WMF-LF
1%
402
R10121
2
1/16W5%1K
NOSTUFF
MF-LF402
C10001
2 X5R
NOSTUFF
0.1uF10%16V
402
U1000
N3
P5
P2
L2
P4
P1
R1
Y2
U5
R3
W6
A6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
J4
U2
V4
W3
AA4
AB2
AA3
L5
L4
K5
M3
N2
J1
H1
M1
V1
A22
A21
E2
AD4
AD3
AD1
AC4
G5
F1
C20
E1
H5
F21
A5
G6
E4
D20
C4
B3
C6
B4
H4
B1
AC2
AC1
D21
K3
H2
K2
J3
L1
C1
F3
F4
G3
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
A3
D5
AC5
AA6
AB3
A24
B25
C7
AB5
G2
AB6
OMIT
MEROMFCBGA
U1000
B22
B23
C21
R26
U26
AA1
Y1
E22
F24
J24
J23
H22
F26
K22
H23
N22
K25
P26
R23
E26
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
G22
T25
N25
Y22
AB24
V24
V26
V23
T22
U25
U23
F23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
AE24
AD24
G25
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
E25
AC22
AD23
AF22
AC23
E23
K24
G24
M26
H25
N24
U22
AC20
E5
B5
D24
J26
L26
Y26
AE25
H26 AA26
AF24
AD26
AE6
D6
D7
C23
D25
C24
AF26
AF1
A26
OMIT
MEROMFCBGA
R1024
1%
MF-LF1/16W
54.9
PLACEMENT_NOTE=Place R1024 near ITP connector (if present)
402
SYNC_DATE=11/12/2006SYNC_MASTER=T9_MLB_NOME
76
051-7455 01
9
CPU FSB
TP_CPU_TEST5
FSB_DINV_L<1>
FSB_D_L<31>
FSB_D_L<30>
FSB_D_L<25>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>
FSB_D_L<9>
FSB_D_L<8>
FSB_D_L<7>
FSB_D_L<6>
FSB_D_L<19>
FSB_D_L<18>
FSB_DSTB_L_P<1>
FSB_D_L<0> FSB_D_L<32>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<5>
FSB_D_L<16>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_DSTB_L_N<1>
CPU_GTLREF
CPU_TEST1
CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST6
CPU_BSEL<0>
CPU_BSEL<1>
CPU_BSEL<2>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_COMP<3>
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L
FSB_D_L<17>
FSB_D_L<4>
FSB_D_L<3>
FSB_DSTB_L_N<0>
FSB_D_L<15>
FSB_D_L<10>
FSB_LOCK_L
CPU_INIT_L
CPU_A20M_L
FSB_A_L<6>
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<14>
FSB_A_L<16>
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_CLK_CPU_N
FSB_CLK_CPU_P
PM_THRMTRIP_L
CPU_THERMD_P
CPU_PROCHOT_L
XDP_DBRESET_L
XDP_TRST_L
XDP_TMS
XDP_TDO
XDP_TDI
XDP_BPM_L<4>
XDP_BPM_L<3>
XDP_BPM_L<1>
XDP_BPM_L<0>
FSB_HITM_L
FSB_HIT_L
FSB_TRDY_L
FSB_RS_L<2>
FSB_RS_L<1>
FSB_RS_L<0>
FSB_CPURST_L
CPU_IERR_L
FSB_BREQ0_L
FSB_DBSY_L
FSB_DRDY_L
FSB_DEFER_L
FSB_BNR_L
TP_CPU_RSVD9
TP_CPU_RSVD8
TP_CPU_RSVD7
TP_CPU_RSVD6
TP_CPU_RSVD5
TP_CPU_RSVD4
TP_CPU_RSVD3
TP_CPU_RSVD2
TP_CPU_RSVD1
TP_CPU_RSVD0
CPU_SMI_L
CPU_NMI
CPU_INTR
CPU_STPCLK_L
CPU_FERR_L
FSB_ADSTB_L<1>
FSB_A_L<35>
FSB_A_L<34>
FSB_A_L<33>
FSB_A_L<32>
FSB_A_L<31>
FSB_A_L<30>
FSB_A_L<29>
FSB_A_L<28>
FSB_A_L<19>
FSB_A_L<18>
FSB_A_L<17>
FSB_ADSTB_L<0>
FSB_A_L<13>
FSB_A_L<12>
FSB_BPRI_L
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<9>
FSB_A_L<8>
FSB_A_L<7>
FSB_A_L<11>
FSB_A_L<25>
CPU_IGNNE_L
FSB_ADS_L
FSB_A_L<10>
FSB_A_L<15>
FSB_A_L<5>
XDP_TCK
XDP_TDO
XDP_TMS
XDP_TDI
XDP_TRST_L
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V05_S0_CPU
CPU_THERMD_N
XDP_TCK
XDP_BPM_L<5>
XDP_BPM_L<2>
12C5
12C5
12C5
12C5
12B3
12B3
12B3
12B3
11A3
11A3
11A3
11A3
10C7
10C7
10C7
10C7
70B3
9D5
9D5
9D5
9C5
12B3
70B3
70B3
70B3
70A3
9C5
9B6
9C5
9B6
12B2
12B5
12B2
12B3
12B3
9B5
9B5
9B6
9B5
70B3 70B3
70B3
70B3
70B3
70C3
9C6
9C6
9C6
9C6
9C6
7C7
7C7
7C7
7C7
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VCC
VSSSENSE
VCCSENSE
VID6
VID5
VID4
VID3
VID2
VID1
VID0
VCCA
VCCP
VCC
3 OF 4
VSS VSS
4 OF 4
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
11.5 A (Deeper Sleep)
25.0 A (Deep Sleep HFM)
27.4 A (Sleep HFM)
17.0 A (Auto-Halt/Stop-Grant SuperLFM)
27.4 A (Auto-Halt/Stop-Grant HFM)
30.4 A (LFM)
25.5 A (SuperLFM)
9.4 A (Enhanced Deeper Sleep)
2500 mA (after VCC stable)
4500 mA (before VCC stable)
16.0 A (Deep Sleep SuperLFM)
16.8 A (Sleep SuperLFM)
41.0 A (HFM)
44.0 A (Design Target)
Standard Voltage:
(CPU CORE POWER)
130 mA
(CPU IO POWER 1.05V)
(CPU INTERNAL PLL POWER 1.5V)
Low Voltage: Ultra Low Voltage:
17.0 A (Design Target)23.0 A (Design Target)
21.0 A (HFM)
18.7 A (LFM)
TBD A (SuperLFM)
TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant SuperLFM)
TBD A (Sleep HFM)
TBD A (Sleep SuperLFM)
TBD A (Deep Sleep HFM)
TBD A (Deep Sleep SuperLFM)
TBD A (Deeper Sleep)
TBD A (Enhanced Deeper Sleep) TBD A (Enhanced Deeper Sleep)
TBD A (Deeper Sleep)
TBD A (Deep Sleep HFM)
TBD A (Sleep HFM)
TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (HFM)
TBD A (LFM)
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
TBD A (Auto-Halt/Stop-Grant LFM)
TBD A (Sleep LFM)
TBD A (Deep Sleep LFM)
CPU_VID<2>
CPU_VID<3>
CPU_VID<5>
=PPVCORE_S0_CPU
CPU_VCCSENSE_N
CPU_VCCSENSE_P
CPU_VID<0>
CPU_VID<1>
=PPVCORE_S0_CPU
CPU_VID<6>
CPU_VID<4>
=PP1V5_S0_CPU
=PP1V05_S0_CPU
SYNC_DATE=11/12/2006SYNC_MASTER=T9_MLB_NOME
CPU Power & Ground
051-7455 01
10 76
MF-LF402
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
1/16W1%100
2
1R1100
FCBGA
MEROM
OMIT
V25
V22
V5
V2
U24
U21
U6
U3
T26
T23B8
T4
T1
R25
R22
R5
R2
P24
P21
P6
P3
B6
N26
N23
N4
N1
M25
M22
M5
M2
L24
L21
AF2
L6
L3
K26
K23
K4
K1
J25
J22
J5
J2
A23
H24
H21
H6
H3
G26
G23
G1
G4
F25
F22
A19
F2
F19
F16
F13
F11
F8
F5
E24
E21
E19
A16
E16
E14
E11
E8
E6
E3
D26
D23
D19
D16
A14
D13
D11
D8
D4
D1
C25
C22
C2
C19
C16
A11
C14
C11
C8
AF25
A25
AF21
C5
AF19
AF16
AF13
AF11
AF8
AF6
A2
AE26
AE23
AE19
B24
AE16
AE14
AE11
AE8
AE4
AE1
AD25
AD22
AD19
AD16
B21
AD13
AD11
AD8
AD5
AD2
AC24
AC21
AC19
AC16
AC14
B19
AC11
AC8
AC6
AC3
AB26
AB23
AB19
AB16
AB13
AB11
B16
AB8
AB4
AB1
AA25
AA22
AA19
AA16
AA14
AA11
AA8
B13
AA5
AA2
Y24
Y21
Y6
Y3
W26
W23
W4
W1
B11
A8
A4
U1000
FCBGA
MEROM
AE7
AE2
AF3
AE3
AF4
AE5
AF5
AD6
AF7
N6
N21
M21
K21
J21
M6
K6
J6
W21
V21
T6
T21
R6
R21
V6
G21
C26
B26
AF20
AF18
AF17
AF15
AF14
AF12
AF10
AF9
AE20
AE18
B7
AE17
AE15
AE13
AE12
AE10
AE9
AD18
AD17
AD15
AD14
A20
AD12
AD10
AD9
AD7
AC18
AC17
AC15
AC13
AC12
AC9
A18
AC7
AB7
AB20
AB18
AB17
AB15
AB14
AB12
AB10
AC10
A17
AB9
AA20
AA18
AA17
AA15
AA13
AA12
AA10
AA9
AA7
A15
F20
F18
F17
F15
F14
F12
F10
F9
F7
E20
A13
E18
E17
E15
E13
E12
E10
E9
E7
D18
D17
A12
D15
D14
D12
D10
D9
C18
C17
C15
C13
C12
A10
C10
C9
B20
B18
B17
B15
B14
B12
B10
B9
A9
A7
U1000
70A3 59A5 59A4
70A3 59A5 59A4
70A3 59C7
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
MF-LF402
1001%1/16W
2
1R1101
70A3 59C7
70A3 59C7
70A3 59C7
70A3 59C7
70A3 59C7
70A3 59C7
OMIT
12C5 12B3 11A3
48B5
48B5
9D5
48B3
48B3
9C5
11D7
11D7
9B6
10D7
10B5
11B3
9B5
7D7
7D7
7C7
7C7
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
LAYOUT NOTE:
CPU VCORE HF AND BULK DECOUPLING
C1250, C1251, C1252 AND C1253 NEED TO USE 6mOHM CAPS.
PLACE ON BOTTOMSIDE
PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)
PLACE ON BOTTOMSIDELAYOUT NOTE:
LAYOUT NOTE:
LAYOUT NOTE:
LAYOUT NOTE:PLACE C1235 CLOSE TO CPU
PLACE INSIDE SOCKET CAVITY (ON BOTTOMSIDE)
4x 330uF. 20x 10uF 0805
1X 330UF, 6X 0.1UF
VCCP (CPU I/O) DECOUPLING
VCCA (CPU AVdd) DECOUPLING
PLACE C1281 NEAR PIN B26 OF U1000LAYOUT NOTE:
1x 10uF, 1x 0.01uF
C1235 1
2 3
CRITICAL
330uF10%2.5VTANTD2T
C12371
220%10VCERM
0.1UF
402
C12381
2
0.1UF
CERM10V20%
402
C12391
220%10VCERM
0.1UF
402
C12401
2
0.1UF
CERM10V20%
402
C12411
2
0.1UF
CERM10V20%
402
C12101
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12161
2805-2
6.3VX5R
CRITICAL
10%10UF
C12011
2805-2
6.3VX5R
CRITICAL
10UF10%
C12021
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12031
2805-2
6.3VX5R
CRITICAL
10UF10%
C12041
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12051
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12061
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12071
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12081
2805-2
6.3VX5R
CRITICAL
10UF10%
C12091
2805-2
6.3VX5R
CRITICAL
10UF10%
C12141
2805-2
6.3VX5R
CRITICAL
10%10UF
C12131
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12121
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12111
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12191
2805-2
6.3VX5R
CRITICAL
10UF10%
C12001
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12361
2402
0.1UF
CERM10V20%
C12151
2805-2
6.3VX5R
10UF10%
CRITICALC12171
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12181
2805-2
6.3VX5R
10UF
CRITICAL
10%
C12811
2
0.01UF16VCERM402
10%
C1280 1
2
10uF20%6.3VX5R603
C12501
23
D2T
2.0V
330UF10%
CRITICAL
TANT
C12511
23
D2T
2.0V
330UF
TANT
10%
CRITICAL
C12521
23 2.0V
330UF
CRITICAL
TANT
10%
D2T
C12531
23
D2T
2.0V
330UF
TANT
10%
CRITICAL
CPU Decoupling & VID
76
01
SYNC_DATE=04/26/2006SYNC_MASTER=MSARWAR
11
051-7455
=PPVCORE_S0_CPU
=PP1V05_S0_CPU
=PP1V5_S0_CPU
12C5 12B3 10C7
48B5
9D5
48B3
9C5
10D7
9B6
10B5
9B5
10B7
7D7
7C7
7C7
OUT
IN
IN
OUT
OUT
OUT
OUT
IO
IN
OUT
IN
IO
IO
IO
IO
IO
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
(FROM CK505 HOST 133/167MHZ)
516S0394
INDICATE THAT ITP IS USING TAP I/F, NC IN 965GM CHIPSET SYSTEM.
TO ICH8M SYS_RST*, AND WITH SYSTEM RESET LOGIC
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’SITP TCK SIGNAL LAYOUT NOTE:
CONNECTOR’S FBO PIN.TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
(DBA#)
(DEBUG PORT ACTIVE)
(DBR#)
(DEBUG PORT RESET)
(FBO)
CPU ITP700FLEX DEBUG SUPPORT
(TCK)
C13001
2
0.1UFX5R10%
ITP
16V402
R13021 2
ITP
22.61%
1/16WMF-LF402
R13011
2
NOSTUFF
54.9
MF-LF402
1/16W1%
R13001 2
ITP
MF-LF402
1/16W1%
22.6
J1302
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
4
56
78
9
ITP
M-ST-SM
CRITICAL
QT500306-L021-9F
01
12 76
SYNC_DATE=5/23/05CPU ITP700FLEX DEBUGSYNC_MASTER=MASTER
051-7455
=PP1V05_S0_CPU
XDP_TDO
XDP_TRST_L
XDP_BPM_L<2>
CPU_PWRGD
XDP_BPM_L<1>
FSB_CPURST_L XDP_BPM_L<4>
=PP1V05_S0_CPU
ITPRESET_L
ITP_TDO
XDP_TMSLVDS_CTRL_DATALVDS_CTRL_CLK
XDP_TCKXDP_BPM_L<5>
XDP_BPM_L<0>
XDP_DBRESET_L
XDP_BPM_L<3>
CPU_XDP_CLK_PCPU_XDP_CLK_N
XDP_TCK
XDP_TDI
12B3
12C5
11A3
11A3
10C7
10C7
9D5
9D5
9C5
9C5
70B3
70B3
9B6
70B3
70A3
70C3
70D3
9B6
70B3
12B3
12B2
70B3
9B5
9C6
9C6
70A3
22C4
70A3
13A5 70A3
9B5
9C6
67A7
67A7
9C6
70A3
70A3
27C6
70A3
9C6
9C6
7C7
9A7
9A7
9C6
9B2
9C6
9D6 9C6
7C7
9B7
14D5
14D5
9A7
9C5
9C6
9C6
9C6
29D3
29D3
9A7
9B7
BI
BI
BI
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
H_D0*
H_D3*
H_D2*
H_D33*
H_D34*
H_D35*
H_D1*
H_D4*
H_D10*
H_A4*
H_A5*
H_A6*
H_A7*
H_A8*
H_A9*
H_A10*
H_A11*
H_A12*
H_A13*
H_A14*
H_A15*
H_A16*
H_A17*
H_A18*
H_A19*
H_A20*
H_A21*
H_A22*
H_A23*
H_A24*
H_A25*
H_A26*
H_A27*
H_A28*
H_A29*
H_A30*
H_A31*
H_A32*
H_A33*
H_A34*
H_A35*
H_ADS*
H_ADSTB0*
H_ADSTB1*
H_A3*
H_D7*
H_D8*
H_D9*
H_D11*
H_D12*
H_D13*
H_D14*
H_D15*
H_D16*
H_D17*
H_D18*
H_D19*
H_D20*
H_D21*
H_D22*
H_D23*
H_D25*
H_D26*
H_D27*
H_D28*
H_D29*
H_D30*
H_D32*
H_D36*
H_D37* H_BNR*
H_D38* H_BPRI*
H_D39*
H_D40* H_DEFER*
H_D41* H_DBSY*
H_D42*
H_D43*
H_D44* H_DPWR*
H_D45* H_DRDY*
H_D46* H_HIT*
H_D47* H_HITM*
H_D48* H_LOCK*
H_TRDY*
H_D51*
H_D52*
H_D53*H_DINV0*
H_D54*H_DINV1*
H_D55*H_DINV2*
H_D56*H_DINV3*
H_D57*
H_D58*H_DSTBN0*
H_D59*H_DSTBN1*
H_D60*H_DSTBN2*
H_D61*H_DSTBN3*
H_D62*
H_D63* H_DSTBP0*
H_DSTBP1*
H_DSTBP2*
H_SWING
H_RCOMP
H_REQ0*
H_SCOMP H_REQ1*
H_SCOMP* H_REQ2*
H_REQ3*
H_CPURST* H_REQ4*
H_CPUSLP*
H_RS0*
H_RS1*
H_AVREF H_RS2*
H_DVREF
H_D5*
H_D6*
H_D31*
H_BREQ*
H_D24*
H_D49*
H_D50*
H_DSTBP3*
HPLL_CLK
HPLL_CLK*
HOST
(1 OF 10)
BI
BI
BI
BI
BI
IN
IN
IN
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
9D8 70C3
9D8 70C3
9C8 70C3
9D6 70D3
9D6 70D3
9D6 70D3
9D6 70D3
9D6 70D3
9B2 70D3
9D6 70D3
9D8 70C3
C14251
2
402
16V10%0.1uF
X5R
R14261
2402
1/16W1%
MF-LF
2.0K
R14251
2402
1/16W1%
MF-LF
1K
9C4 70D3
9B4 70C3
9C2 70C3
9B2 70C3
9C4 70D3
9B4 70C3
9D8 70C3
9C2 70C3
9B2 70C3
9C4 70D3
9B4 70C3
9C2 70C3
9B2 70C3
9C6 70D3
9C6 70D3
9D6 70D3
9D8 70C3
9D6 70D3
9D6 70D3
9D6 70D3
9D8 70C3
9D8 70C3
9D8 70C3
9D8 70C3
9C8 70C3
9D8 70C3
R14201
2402
1/16W1%
MF-LF
54.9
R14151
2402
1/16W1%
MF-LF
24.9
R14101
2402
1/16W1%
MF-LF
221
R14111
2402
1/16W1%
MF-LF
100C14101
2
402
16V10%0.1uF
X5R
9D8 70C3
U1400
G17
C14
K16
B13
L16
J17
B14
K19
P15
R17
B16
H20
L19
D17
M17
N16
J19
B18
E19
B17
J13
B15
E17
C18
A19
B19
N19
B11
C11
M11
C15
F16
L13
G12
H17
G20
B9
C8
E8
F12
B6
E5
E2
G2
M10
N12
N9
H5
P13
K9
M2
W10
Y8
V4
G7
M3
J1
N5
N3
W6
W9
N2
Y7
Y9
P4
M6
W3
N1
AD12
AE3
AD9
AC9
AC7
AC14
AD11
AC11
H7
AB2
AD7
AB1
Y3
AC6
AE2
AC5
AG3
AJ9
AH8
H3
AJ14
AE9
AE11
AH12
AJ5
AH5
AJ6
AE7
AJ7
AJ2
G4
AE5
AJ3
AH2
AH13
F3
N8
H2
C10
D6
K5
L2
AD13
AE13
H8
K7
M7
K3
AD2
AH11
L7
K2
AC2
AJ10
A9
E4
C6
G10
C2
M14
E13
A11
H13
B12
E12
D7
D8
W1
W2
B3
B7
AM5
AM7
FCBGA
CRESTLINE
OMIT
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
R14211
2402
1/16W1%
MF-LF
54.9
9D6 70D3
29D3 75C3
29D3 75C3
9D6 12B5 70D3
9A2 70B3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C8 70C3
9C4 70D3
9D8 70C3
9D8 70C3
9D8 70C3
9D8 70C3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70D3
9C4 70C3
9B4 70C3
9C4 70C3
9C4 70C3
9B4 70C3
9B4 70C3
9B4 70C3
9B4 70C3
9B4 70C3
9D8 70C3
9B4 70C3
9B4 70C3
9B4 70C3
9B4 70C3
9B4 70C3
9B4 70C3
9B4 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9D8 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9D8 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9C2 70C3
9B2 70C3
9C2 70C3
9C2 70C3
9B2 70C3
9B2 70C3
9B2 70C3
9D8 70C3
9B2 70C3
9B2 70C3
9B2 70C3
9B2 70C3
9B2 70C3
9B2 70C3
9B2 70C3
9B2 70C3
9B2 70C3
9D6 70D3
SYNC_MASTER=T9_MLB
13 76
01051-7455
NB CPU InterfaceSYNC_DATE=10/30/2006
=PP1V25R1V05_S0_FSB_NB
FSB_D_L<47>
FSB_D_L<3>
FSB_D_L<2>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<1>
FSB_D_L<10>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<11>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<32>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<42>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<48>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
NB_FSB_SCOMP
NB_FSB_SCOMP_L
FSB_CPURST_L
FSB_CPUSLP_L
FSB_D_L<6>
FSB_D_L<31>
FSB_D_L<24>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<12>
FSB_D_L<43>
FSB_D_L<5>
FSB_D_L<4>
FSB_D_L<0>
FSB_D_L<38>
FSB_D_L<41>
FSB_D_L<59>
NB_FSB_SWING
NB_FSB_RCOMP
NB_FSB_VREF
FSB_A_L<3>
FSB_A_L<6>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<11>
FSB_A_L<10>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<32>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADS_L
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
FSB_BPRI_L
FSB_BNR_L
FSB_BREQ0_L
FSB_DEFER_L
FSB_DBSY_L
FSB_DPWR_L
FSB_CLK_NB_P
FSB_CLK_NB_N
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_TRDY_L
FSB_LOCK_L
FSB_DINV_L<0>
FSB_DINV_L<1>
FSB_DINV_L<2>
FSB_DINV_L<3>
FSB_DSTB_L_N<0>
FSB_DSTB_L_N<1>
FSB_DSTB_L_N<2>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<0>
FSB_DSTB_L_P<1>
FSB_DSTB_L_P<2>
FSB_DSTB_L_P<3>
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_RS_L<1>
FSB_RS_L<0>
FSB_RS_L<2>
29C6 29B6 7C7
IN
IN
OUT
IN
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
BI
L_BKLT_CTRL
L_VDD_EN
PEG_TX15*
PEG_TX14*
PEG_TX13*
PEG_TX12*
PEG_TX11*
PEG_TX10*
PEG_TX9*
PEG_TX8*
PEG_TX7*
PEG_TX6*
PEG_TX5*
PEG_TX4*
PEG_TX3*
PEG_TX2*
PEG_TX1*
PEG_TX0*
PEG_TX15
PEG_TX14
PEG_TX13
PEG_TX12
PEG_TX11
PEG_TX10
PEG_TX9
PEG_TX8
PEG_TX7
PEG_TX6
PEG_TX5
PEG_TX4
PEG_TX3
PEG_TX2
PEG_TX1
PEG_TX0
PEG_RX14
PEG_RX15*
PEG_RX14*
PEG_RX13*
PEG_RX12*
PEG_RX11*
PEG_RX15
PEG_RX13
PEG_RX12
PEG_RX11
PEG_RX10
PEG_RX9
PEG_RX8
PEG_RX7
PEG_RX6
PEG_RX5
PEG_RX4
PEG_RX3
PEG_RX2
PEG_RX1
PEG_RX0
PEG_RX10*
PEG_RX9*
PEG_RX8*
PEG_RX7*
PEG_RX6*
PEG_RX5*
PEG_RX4*
PEG_RX3*
PEG_RX2*
PEG_RX1*
PEG_RX0*
PEG_COMPI
PEG_COMPO
CRT_DDC_DATA
L_CTRL_DATA
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA0
LVDSB_DATA2*
LVDSB_DATA1*
LVDSB_DATA0*
LVDSA_DATA2
LVDSA_DATA0
LVDSA_DATA1
LVDSB_CLK*
LVDS_VREFL
LVDS_IBG
TVC_RTN
TVA_RTN
TVB_RTN
TVC_DAC
TVB_DAC
TVA_DAC
CRT_RED*
CRT_RED
CRT_GREEN*
CRT_GREEN
CRT_BLUE*
CRT_BLUE
CRT_VSYNC
CRT_TVO_IREF
CRT_HSYNC
CRT_DDC_CLK
L_BKLT_EN
L_DDC_CLK
TV_DCONSEL0
TV_DCONSEL1
LVDSA_DATA2*
L_DDC_DATA
LVDSA_DATA1*
LVDSA_DATA0*
LVDSB_CLK
LVDSA_CLK
LVDSA_CLK*
LVDS_VREFH
L_CTRL_CLK
LVDS_VBG
VGA
TV
LVDS
(3 OF 10)
PCI-EXPRESS GRAPHICS
BI
BI
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
rails must be filtered except for VCCA_CRT.
Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).
decoupling. Otherwise, tie VCCD_LVDS to GND also.
Can leave all signals NC if LVDS is not implemented.
S-Video: DACB & DACC only
Unused DAC outputs must remain powered, but can
share filtering with VCCA_CRT_DAC.
Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.
Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,
CRT & TV-Out Disable
All CRT/TVDAC rails must be powered. All
omit filtering components. Unused DAC outputs
VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,
VCCD_CRT, VCCD_QDAC and VCC_SYNC.
NOTE: Must keep VDDC_TVDAC powered
and filtered at all times!
Internal Graphics Disable
Follow instructions for LVDS and CRT & TV-Out Disable above.
TV_DCONSELx to GND.
Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and
Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.
Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).
Tie VCC_AXG and VCC_AXG_NCTF to GND.
Leave GFX_VID<3..0> and GFX_VR_EN as NC.
Tie TVx_DAC and TVx_RTN to GND. Must power all
TV-Out Disable / CRT Enable
CRT Disable / TV-Out Enable
VSYNC and CRT_TVO_IREF to GND.
Can tie the following rails to GND:
TV-Out Signal Usage:
Composite: DACA only
Component: DACA, DACB & DACC
should connect to GND through 75-ohm resistors.
TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can
Tie VCC_TX_LVDS and VCCA_LVDS to GND.
LVDS Disable
If SDVO is used, VCCD_LVDS must remain powered with proper
SDVOC_RED
SDVOC_GREEN
SDVOC_BLUE
SDVOC_CLKP
SDVOB_BLUE
SDVOB_CLKP
SDVOB_RED#
SDVOB_GREEN#
SDVOB_BLUE#
SDVOB_CLKN
SDVOC_RED#
SDVOC_GREEN#
SDVOC_BLUE#
SDVOC_CLKN
SDVOB_RED
SDVOB_GREEN
SDVO_FLDSTALL
SDVO_INT
SDVO_TVCLKIN
SDVO_INT#
SDVO_TVCLKIN#
SDVO Alternate Function
SDVO_FLDSTALL#
8C6
8C6
R15101
2402MF-LF1/16W1%24.9
67B8
8C6
69B8
69A8
69A8
69D7
69D8
69D7
69A8
8C6
69B8
69A8
67A8 71C3
U1400
H32
G32
K33
G35
K29
J29
F33
F29
E29
C32
E33
J40
H39
E39
E40
C37
D35
K40
L41
L43
N41
N40
C45
D46
G50
G51
E50
E51
F48
F49
E42
D44
E44
G44
A47
B47
A45
B45
N43
M43
J50
J51
L50
L51
AC45
AD44
AC41
AD40
AH47
AG46
AG49
AH49
AH45
AG45
AG42
AG41
M47
N47
U44
T45
T49
T50
T41
U40
W45
Y44
W41
Y40
AB50
AB51
Y48
W49
M45
N45
T38
U39
AD47
AC46
AC50
AC49
AD43
AC42
AG39
AH39
AE50
AE49
AH43
AH44
T46
U47
N50
N51
R51
R50
U43
T42
W42
Y43
Y47
W46
Y39
W38
AC38
AD39
M35
P33
E27
F27
G27
J27
K27
L27
OMIT
CRESTLINEFCBGA
12B1 67A7
12B1 67A7
69C8
69C8
8C6
8C6
8C6
8C6
8C6
8C6
8D6
68B6 71D3
8C6
8C6
8C6
8C6
8C6
8C6
8C6
8C6
8C6
68B6 71D3
8C6
8B6
8B6
8B6
68C6 71D3
68C6 71D3
8B6
8A6
8B6
8B6
8C6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8C6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8B6
8C6
68B6 71D3
68B6 71D3
68B6 71D3
68B6 71D3
68C6 71D3
68C6 71D3
67C6
67D8
8C6
67B6
67B6
67B3 71D3
67B3 71D3
8D6
8D6
67B2 71D3
67B2 71D3
8C6
67B2 71D3
8D6
8D6
8D6
67B2 71D3
67B2 71D3
67B2 71D3
8D6
8D6
8D6
8C6
69D8
69D8
69D8
69D7
69D7
69D7
69B8
69B8
SYNC_DATE=10/30/2006
14 76
01051-7455
NB PEG / Video InterfacesSYNC_MASTER=T9_MLB
=TV_B_RTN
=TV_B_DAC
LVDS_B_DATA_N<2>
LVDS_B_DATA_N<1>
LVDS_CTRL_DATA
LVDS_CTRL_CLK
TP_LVDS_VBG
PEG_D2R_P<9>
PEG_D2R_P<11>
PEG_D2R_P<10>
PP1V05_S0_NB_VCCPEG
PEG_D2R_N<1>
PEG_D2R_N<6>
TP_LVDS_VREFH
LVDS_A_CLK_N
LVDS_A_CLK_P
LVDS_B_CLK_P
LVDS_A_DATA_N<0>
LVDS_A_DATA_N<1>
LVDS_A_DATA_N<2>
TV_DCONSEL<1>
TV_DCONSEL<0>
LVDS_BKLT_EN
CRT_DDC_CLK
=CRT_HSYNC_R
=CRT_TVO_IREF
=CRT_VSYNC_R
=CRT_BLUE
=CRT_BLUE_L
=CRT_GREEN
=CRT_GREEN_L
=CRT_RED
=CRT_RED_L
=TV_A_DAC
=TV_C_DAC
=TV_A_RTN
=TV_C_RTN
LVDS_IBG
TP_LVDS_VREFL
LVDS_B_CLK_N
LVDS_A_DATA_P<1>
LVDS_A_DATA_P<0>
LVDS_A_DATA_P<2>
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<2>
LVDS_B_DATA_P<1>
CRT_DDC_DATA
PEG_COMP
PEG_D2R_N<0>
PEG_D2R_N<2>
PEG_D2R_N<3>
PEG_D2R_N<4>
PEG_D2R_N<5>
PEG_D2R_N<7>
PEG_D2R_N<8>
PEG_D2R_N<9>
PEG_D2R_N<10>
PEG_D2R_P<0>
PEG_D2R_P<1>
PEG_D2R_P<2>
PEG_D2R_P<3>
PEG_D2R_P<4>
PEG_D2R_P<5>
PEG_D2R_P<6>
PEG_D2R_P<7>
PEG_D2R_P<8>
PEG_D2R_P<12>
PEG_D2R_P<13>
PEG_D2R_P<15>
PEG_D2R_N<11>
PEG_D2R_N<12>
PEG_D2R_N<13>
PEG_D2R_N<14>
PEG_D2R_N<15>
PEG_D2R_P<14>
PEG_R2D_C_P<0>
PEG_R2D_C_P<1>
PEG_R2D_C_P<2>
PEG_R2D_C_P<3>
PEG_R2D_C_P<4>
PEG_R2D_C_P<5>
PEG_R2D_C_P<6>
PEG_R2D_C_P<7>
PEG_R2D_C_P<8>
PEG_R2D_C_P<9>
PEG_R2D_C_P<10>
PEG_R2D_C_P<11>
PEG_R2D_C_P<12>
PEG_R2D_C_P<13>
PEG_R2D_C_P<14>
PEG_R2D_C_P<15>
PEG_R2D_C_N<0>
PEG_R2D_C_N<1>
PEG_R2D_C_N<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<4>
PEG_R2D_C_N<5>
PEG_R2D_C_N<6>
PEG_R2D_C_N<7>
PEG_R2D_C_N<8>
PEG_R2D_C_N<9>
PEG_R2D_C_N<10>
PEG_R2D_C_N<11>
PEG_R2D_C_N<12>
PEG_R2D_C_N<13>
PEG_R2D_C_N<14>
PEG_R2D_C_N<15>
LVDS_BKLT_CTL
LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_VDD_EN
20D3 18B3
IN
IN
CLKREQ*
NC1
NC8
CL_CLK
CL_PWROK
CL_RST*
RSVD6
THERMTRIP*
PM_BM_BUSY*
RSVD4
RSVD3
RSVD7
SM_CKE1
SM_CK0*
SM_CKE0
SM_ODT0
SM_ODT2
SM_RCOMP
SM_RCOMP*
SM_VREF0
SM_VREF1
SM_RCOMP_VOL
SM_CS1*
SM_CS0*RSVD14
RSVD11
RSVD10
RSVD9
RSVD5
RSVD8
RSVD2
DPLL_REF_CLK*
DPLL_REF_SSCLK
PEG_CLK
DMI_RXN1
DMI_RXN0
DMI_RXN3
DMI_RXN2
DMI_RXP0
DMI_RXP1
DMI_RXP2
DMI_TXN0
DMI_RXP3
DMI_TXN2
DMI_TXN1
DMI_TXP0
DMI_TXN3
DMI_TXP1
DMI_TXP2
DMI_TXP3
PEG_CLK*
RSVD12
CL_DATA
CL_VREF
SDVO_CTRL_CLK
SDVO_CTRL_DATA
ICH_SYNC*
TEST1
TEST2
GFX_VID0
GFX_VID1
GFX_VID2
GFX_VR_EN
GFX_VID3
RSVD20
RSVD21
RSVD24
RSVD25
RSVD27
RSVD34
RSVD35
RSVD36
RSVD37
RSVD38
RSVD39
RSVD41
RSVD42
RSVD40
RSVD43
RSVD44
RSVD45
CFG0
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
CFG10
CFG11
CFG12
CFG13
CFG16
CFG15
CFG14
CFG17
CFG18
CFG19
CFG20
PM_DPRSTP*
PM_EXT_TS0*
PWROK
PM_EXT_TS1*
RSTIN*
DPRSLPVR
NC2
NC4
NC3
NC5
NC7
NC6
NC10
NC9
NC12
NC11
NC13
NC14
NC15
NC16
DPLL_REF_CLK
SM_RCOMP_VOH
SM_ODT3
SM_ODT1
RSVD13
SM_CS2*
SM_CS3*
SM_CK3
SM_CK4
SM_CK4*
SM_CKE3
RSVD1
SM_CKE4
DPLL_REF_SSCLK*
SM_CK3*
SM_CK1*
SM_CK1
SM_CK0
SA_MA14
RSVD22
RSVD23
RSVD26
SB_MA14
SM_CK2
SM_CK2*
SM_CK5
SM_CK5*
(2 OF 10)
RSVD
DDR MUXING
CLK
CFG
DMI
PM
GRAPHICS VID
ME
MISC
NC
OUT
OUT
OUT
OUT
OUT
BI
BI
IN
OUT
BI
BI
OUT
OUT
IN
IN
OUT
OUT
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
BI
OUT
BI
OUT
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
IPU
NB CFG<13:12> require ICT access
IPU
IPU
RESERVED
RESERVED
Low = DMIx2
NB_CFG<8>
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPD
IPD
IPD
IPU
RESERVED
NB_CFG<6>
NB_CFG<7> RESERVED
RESERVED
RESERVED
High = Normal
Low = Reversed
NB_CFG<10>
NB_CFG<9>PCIe Graphics
Lane Reversal
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
See Below
See Below
Low = Disabled
High = Enabled
10 = All-Z Mode Enabled
01 = XOR Mode Enabled
Low = Normal
High = Both active
NB_CFG<13:12>
Low = Only SDVO
High = Reversed
11 = Normal Operation
or PCIe x16
00 = RESERVED
NB_CFG<19>
NB_CFG<20>Concurrent
SDVO/PCIe x1
Reversal
DMI Lane
NB_CFG<13>
NB_CFG<12>
NB_CFG<11>
NB_CFG<16>
NB_CFG<14>
NB_CFG<17>
ODT
FSB Dynamic
NB_CFG<15>
NB_CFG<18>
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
If ME/AMT is not used, short CL_PWROK to PWROK.
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
NOTE: GMCH CL_PWROK input must be PWRGD signal for
DMI x2 Select
NB_CFG<5>
NB_CFG<4>
IPU
NB CFG<8:0> used for debug access
High = DMIx4
NB_CFG<3>
Clk used for PEG and DMI
27D1
20A4
C16161
2
402CERM
20%0.1uF
10V
C1615 1
2
402CERM
20%0.1uF
10V
U1400
P27
N27
R24
L23
J23
E23
E20
K23
M20
M24
L32
N33
N24
L35
C21
C23
F23
N23
G23
J20
C20
AM49
AK50
AT43
AN49
AM50
G39
AN47
AJ38
AN42
AN46
AM47
AJ39
AN41
AN45
AJ46
AJ41
AM40
AM44
AJ47
AJ42
AM39
AM43
B42
C42
H48
H47
G36
E35
A39
C38
B39
E36
G40
BJ51
E1
A5
C51
B50
A50
A49
BK2
BK51
BK50
BL50
BL49
BL3
BL2
BK1
BJ1
K44
K45
G41
L39
L36
J36
AW49
AV20
P36
AR37
AM36
AL36
AM37
D20
P37
H10
B51
BJ20
BK22
BF19
BH20
BK18
BJ18
R35
BH39
AW20
BK20
C48
D47
B44
N35
C44
A35
B37
B36
B34
C34
AR12
AR13
AM12
AN13
J12
BJ29
BE24
H35
K36
AV29
AW30
BB23
BA23
BF23
BG23
BA25
AW25
AV23
AW23
BC23
BD24
BE29
AY32
BD39
BG37
BG20
BK16
BG16
BE13
BH18
BJ15
BJ14
BE16
BL15
BK14
BK31
BL31
AR49
AW4
A37
R32
N20
CRESTLINEFCBGA
OMIT
21B6 60C6
21B6 60C6
21B6 60C6
21B6 60C6
8B2
24C3 74A3
24C3 74A3
8B2
24C3 74A3
68A6
68A6
28B4
24B5
R16911
2402
20K
MF-LF1/16W
5%
R16901
2402
0
MF-LF1/16W5%
24C3 59D8 70B3
8B2 44B8
R16311
2 402
10K
MF-LF
5%1/16W
C1625 1
2
0.01UF10%16VCERM402
C16241
2
603
2.2UF
6.3VCERM1
20%
R16241
2
1K
MF-LF
1%1/16W
402
R16221
2402
1%1/16WMF-LF
3.01K
C16221
2
603
6.3VCERM1
2.2UF20%
C1623 1
2
0.01UF10%16VCERM402
R16201
2
1K
402
1/16W1%
MF-LF
R16411
2402
392
MF-LF1/16W1%
R16401
2402MF-LF1/16W
1K1%
C1640 1
2
402
20%10VCERM
0.1uF
R16551
2402
5%3.9K
MF-LF1/16W
NBCFG_DMI_X2
R16591
2402
5%1/16WMF-LF
3.9K
NBCFG_PEG_REVERSE
R16661
2402
NBCFG_DYN_ODT_DISABLE
3.9K
1/16W5%
MF-LF
R16691
2402
3.9K
MF-LF1/16W5%
NBCFG_DMI_REVERSE
R16701
2402
5%1/16WMF-LF
3.9K
NBCFG_SDVO_AND_PCIE
60C6
30C4 32C6 72D3
31C4 32A5 72B3
29C8 70B3
29B8 70B3
29B8 70B3
8A6
8A6
8A6
8A6
15D7
24D5
8A6
R16001 2
0
5%1/16WMF-LF402
9C6 22C2 45B3 70B3
8B2 44B8
9B2 22C4 59C7 70B3
27B5 59C7
30D4 72D3
31A4 72B3
31D4 72B3
30A4 72D3
30D4 72D3
31A4 72B3
31D4 72B3
30A4 72D3
30C6 32D6 72D3
30C4 32D6 72D3
31C6 32D6 72B3
30B4 32D6 72D3
31C4 32D5 72B3
30B6 32D6 72D3
31B4 32D6 72B3
31B6 32D6 72B3
30B4 32D6 72D3
30B6 32D6 72D3
31B4 32D6 72B3
31B6 32D6 72B3
R16101
2
MF-LF1/16W
1%20
402
R16111
2
1/16W1%
MF-LF
20
402
20A5
29C3 75B3
29C3 75B3
8B2
8B2
8B2
8B2
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
23D2 71D3
R16301
2402MF-LF1/16W
5%10K
051-7455 01
7615
SYNC_MASTER=T9_MLB SYNC_DATE=10/30/2006
NB Misc Interfaces
GFX_VID<4>
DMI_N2S_P<0>
DMI_N2S_P<2>
CLINK_NB_CLK
CLINK_NB_DATA
=NB_CLINK_MPWROK
CLINK_NB_RESET_L
SDVO_CTRLCLK
TP_NB_RSVD<42>
TP_NB_RSVD<41>
TP_NB_RSVD<43>
NB_BSEL<1>
NB_CFG<3>
NB_CFG<9>
TP_NB_CFG<12>
TP_NB_CFG<15>
NB_CFG<16>
DMI_N2S_N<3>
DMI_N2S_P<1>
DMI_N2S_P<3>
GFX_VID<1>
=GFX_VR_EN
GFX_VID<3>
TP_LVDS_A_DATAP3
TP_NB_RSVD<34>
MEM_B_A<14>
TP_NB_RSVD<27>
TP_NB_RSVD<26>
TP_NB_RSVD<25>
NB_BSEL<0>
NB_CFG<5>
MEM_CKE<4>
TP_NB_RSVD<1> MEM_CLK_P<0>
MEM_CLK_N<4>
MEM_CLK_N<3>
MEM_CLK_P<4>
MEM_CLK_P<3>
TP_NB_RSVD<13>
TP_NB_NC<16>
TP_NB_NC<15>
TP_NB_NC<14>
TP_NB_NC<13>
TP_NB_NC<11>
TP_NB_NC<12>
TP_NB_NC<9>
TP_NB_NC<10>
TP_NB_NC<6>
TP_NB_NC<7>
TP_NB_NC<5>
TP_NB_NC<3>
TP_NB_NC<2>
PM_EXTTS_L<0>
NB_CFG<20>
NB_CFG<19>
TP_NB_CFG<18>
TP_NB_CFG<14>
TP_NB_CFG<10>
TP_NB_RSVD<23>
TP_NB_RSVD<22>
TP_NB_RSVD<21>
TP_NB_RSVD<20>
NB_TEST2
NB_TEST1
TP_NB_RSVD<2>
TP_NB_RSVD<8>
TP_NB_RSVD<9>
TP_NB_RSVD<10>
TP_NB_RSVD<11>
MEM_CS_L<0>
MEM_CS_L<1>
MEM_CKE<0>
MEM_CLK_N<1>
MEM_CLK_P<1>
MEM_CLK_N<0>
TP_NB_RSVD<7>
TP_NB_RSVD<3>
TP_NB_RSVD<4>
TP_NB_NC<8>
TP_NB_NC<1>
NB_CLK100M_PCIE_P
DMI_S2N_P<0>
DMI_N2S_N<0>
SDVO_CTRLDATA
NB_CLKREQ_L
NB_SB_SYNC_L
TP_MEM_CLKN2
TP_MEM_CLKP5
TP_MEM_CLKN5
PM_BMBUSY_L
CPU_DPRSTP_L
VR_PWRGOOD_DELAY
PM_THRMTRIP_L
MEM_CS_L<2>
MEM_ODT<2>
MEM_ODT<3>
MEM_CS_L<3>
MEM_ODT<0>
MEM_ODT<1>
TP_NB_RSVD<6>
TP_NB_RSVD<12>
TP_NB_NC<4>
DMI_S2N_P<3>
=PP0V9_S3M_MEM_NBVREFB
TP_NB_RSVD<5>
TP_NB_RSVD<24>
TP_MEM_CLKP2
TP_LVDS_A_DATAN3
TP_LVDS_B_DATAP3
MEM_A_A<14>
TP_NB_RSVD<35>
TP_NB_RSVD<36>
TP_LVDS_B_DATAN3
TP_NB_RSVD<45>
TP_NB_RSVD<14>
PM_DPRSLPVR
NB_RESET_L
PM_EXTTS_L<1>
NB_CFG<16>
=PP3V3_S0_NB_VCCHV
NB_CFG<19>
NB_CFG<20>
=PP3V3_S0_NB_VCCHV
TP_NB_CFG<11>
TP_NB_CFG<13>
=PP3V3_S0_NB_VCCHV
TP_NB_CFG<17>
PP1V25_S0M_NB_VCCAXD
NB_CLINK_VREF
NB_BSEL<2>
NB_CFG<6>
NB_CFG<7>
NB_CFG<8>
NB_CFG<5>
MEM_RCOMP_L
TP_NB_RSVD<44>
NB_CFG<4>
MEM_CKE<1>
MEM_CKE<3>
=PP0V9_S3M_MEM_NBVREFA
MEM_RCOMP_VOL
MEM_RCOMP
=PP1V8_S3M_MEM_NB
MEM_RCOMP_VOH
NB_CFG<9>
GFX_VID<0>
=NB_CLK96M_DOT_P
=NB_CLK96M_DOT_N
=NB_CLK100M_DPLLSS_P
=NB_CLK100M_DPLLSS_N
NB_CLK100M_PCIE_N
DMI_S2N_N<0>
DMI_S2N_N<1>
DMI_S2N_N<2>
DMI_S2N_N<3>
DMI_S2N_P<1>
DMI_S2N_P<2>
DMI_N2S_N<1>
DMI_N2S_N<2>
GFX_VID<2>
21B7
21B7
20A8
20A8
21B7
31D2
18B3
18B3
20A8
30D2
15C7
15C7
18B3
20C8
15B7
15B7
15C7
20A6
17D7
15D7
15D7
8D6
15B6
15C7
15C7
8B4
8B4
8B4
8B4
8D6
8D6
8D6
15B6
7D4
15B6
15B6
7D4
7D4
18C3
74A3
7A4
15B6
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
SA_DQ0
SA_DQ1
SA_DQ2
SA_DQ4
SA_DQ6
SA_DQ14
SA_CAS*
SA_BS2
SA_DQ63
SA_DQ62
SA_DQ61
SA_DQ60
SA_DQ59
SA_DQ58
SA_DQ57
SA_DQ56
SA_DQ55
SA_DQ54
SA_DQ53
SA_DQ52
SA_DQ51
SA_DQ50
SA_DQ49
SA_DQ48
SA_DQ47
SA_DQ46
SA_DQ44
SA_DQ43
SA_DQ42
SA_DQ41
SA_DQ40
SA_DQ39
SA_DQ38
SA_DQ37
SA_DQ36
SA_DQ34
SA_DQ35
SA_DQ33
SA_DQ32
SA_DQ31
SA_DQ30
SA_DQ28
SA_DQ29
SA_DQ27
SA_DQ26
SA_DQ25
SA_DQ24
SA_DQ23
SA_DQ22
SA_DQ21
SA_DQ20
SA_DQ19
SA_DQ18
SA_DQ17
SA_DQ16
SA_DQ15
SA_DQ13
SA_DQ11
SA_DQ12
SA_DQ10
SA_DQ9
SA_DQ8
SA_DQ7
SA_DQ5
SA_DQ3
SA_BS1
SA_BS0
SA_DQ45
SA_DM0
SA_DM1
SA_DM3
SA_DM2
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0
SA_DQS1
SA_DQS2
SA_DQS3
SA_DQS4
SA_DQS5
SA_DQS6
SA_DQS7
SA_DQS1*
SA_DQS0*
SA_DQS2*
SA_DQS4*
SA_DQS3*
SA_DQS5*
SA_DQS6*
SA_DQS7*
SA_MA0
SA_MA1
SA_MA2
SA_MA3
SA_MA4
SA_MA5
SA_MA6
SA_MA7
SA_MA9
SA_MA8
SA_MA10
SA_MA11
SA_MA12
SA_MA13
SA_RAS*
SA_RCVEN*
SA_WE*
DDR SYSTEM MEMORY A
(4 OF 10)SB_DQ2
SB_DQ1
SB_DQ5SB_DM0
SB_DQ0
SB_DQ4
SB_DQ6
SB_DQ7
SB_CAS*
SB_BS2
SB_BS0
SB_BS1
SB_DQ63
SB_DQ62
SB_DQ59
SB_DQ58
SB_DQ56
SB_DQ55
SB_DQ54
SB_DQ53
SB_DQ52
SB_DQ51
SB_DQ50
SB_DQ49
SB_DQ48
SB_DQ47
SB_DQ45
SB_DQ46
SB_DQ44
SB_DQ43
SB_DQ42
SB_DQ41
SB_DQ40
SB_DQ39
SB_DQ38
SB_DQ37
SB_DQ36
SB_DQ34
SB_DQ35
SB_DQ33
SB_DQ32
SB_DQ31
SB_DQ30
SB_DQ28
SB_DQ29
SB_DQ27
SB_DQ26
SB_DQ25
SB_DQ24
SB_DQ23
SB_DQ22
SB_DQ21
SB_DQ20
SB_DQ19
SB_DQ18
SB_DQ17
SB_DQ16
SB_DQ15
SB_DQ14
SB_DQ13
SB_DQ11
SB_DQ12
SB_DQ10
SB_DQ9
SB_DQ8
SB_DQ3
SB_DQ57
SB_DQ61
SB_DQ60
SB_WE*
SB_RCVEN*
SB_RAS*
SB_MA13
SB_MA12
SB_MA11
SB_MA10
SB_MA8
SB_MA9
SB_MA7
SB_MA6
SB_MA5
SB_MA4
SB_MA3
SB_MA2
SB_MA1
SB_MA0
SB_DQS7*
SB_DQS6*
SB_DQS5*
SB_DQS3*
SB_DQS4*
SB_DQS2*
SB_DQS0*
SB_DQS1*
SB_DQS7
SB_DQS6
SB_DQS5
SB_DQS4
SB_DQS3
SB_DQS2
SB_DQS1
SB_DQS0
SB_DM6
SB_DM7
SB_DM4
SB_DM5
SB_DM2
SB_DM3
SB_DM1
(5 OF 10)
DDR SYSTEM MEMORY B
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
30A6 72D3
30C6 72C3
30B6 72C3
30B4 72C3
30A4 72C3
30A6 72C3
30A4 72C3
30A6 72C3
30B6 72C3
30B4 72C3
30C4 72C3
30A6 72D3
30C6 72C3
30D4 72C3
31A6 72B3
31A4 72B3
31A6 72B3
31A4 72B3
31A6 72B3
31A6 72B3
31A4 72B3
31A4 72B3
30A6 72D3 31A6 72B3
31A6 72B3
31A4 72B3
31A6 72B3
31A4 72B3
31A4 72B3
31B6 72B3
31A6 72B3
31A4 72B3
31A4 72B3
30A4 72D3
31B6 72B3
31A6 72B3
31B4 72B3
31B4 72B3
31A4 72B3
31A6 72B3
31B6 72B3
31B6 72B3
31B4 72B3
31B4 72B3
30A4 72D3
31B6 72B3
31C6 72B3
31C6 72B3
31B6 72B3
31B4 72B3
31B4 72B3
31C4 72B3
31C6 72B3
31C4 72B3
31C6 72B3
30A6 72D3
31C4 72B3
31C4 72B3
31C4 72B3
31C6 72B3
31C4 72B3
31C6 72B3
31C4 72B3
31C6 72B3
31C6 72B3
31C4 72B3
30A6 72D3
31D4 72B3
31D4 72B3
31D4 72B3
31D6 72B3
31D4 72B3
31D6 72B3
31D6 72B3
31D6 72B3
31D6 72B3
30A4 72D3
31D4 72B3
31D4 72B3
31D6 72B3
31D4 72B3
31D6 72B3
31D4 72B3
31D6 72B3
31B6 32A6 72B3
31B4 32A6 72B3
31B4 32A5 72B3
30A6 72D3
31C6 32A5 72B3
31B6 32B5 72B3
31C4 32A5 72B3
31C6 32B5 72B3
31C6 32B5 72B3
31C4 32B5 72B3
31B6 32B5 72B3
31C4 32B5 72B3
31B4 32B5 72B3
31B6 32B5 72B3
30A4 72D3
31B4 32B5 72B3
31B6 32B5 72B3
31B4 32B5 72B3
31A4 72A3
31A6 72A3
31C4 72A3
31B6 72A3
31B4 72A3
31C6 72A3
31D6 72A3
30A4 72D3
31A6 72A3
31A4 72A3
31D6 72A3
31B6 72A3
31A4 72A3
31C4 72A3
31D6 72A3
31C6 72A3
31A6 72A3
31D6 72A3
30A6 72D3
31A6 72B3
31A4 72A3
31C6 72B3
31B4 72B3
31C4 72B3
31D4 72B3
31D4 72B3
31B6 32A6 72B3
31C6 32A6 72B3
31B6 32A6 72B3
30A4 72D3
31B4 32A6 72B3
U1400BB19
BK19
BF29
BL17
AT45
BD44
BD42
AW38
AW13
BG8
AY5
AN6
AR43
AW44
BG47
BJ45
BB47
BG50
BH49
BE45
AW43
BE44
BG42
BE40
BA45
BF44
BH45
BG40
BF40
AR40
AW40
AT39
AW36
AW41
AY41
AY46
AV38
AT38
AV13
AT13
AW11
AV11
AU15
AT11
BA13
BA11
AR41
BE10
BD10
BD8
AY9
BG10
AW9
BD7
BB9
BB5
AY7
AR45
AT5
AT7
AY6
BB7
AR5
AR8
AR9
AN3
AM8
AN10
AT42
AT9
AN9
AM9
AN11
AW47
BB45
BF48
AT46
AT47
BE48
BD47
BB43
BC41
BC37
BA37
BB16
BA16
BH6
BH7
BB2
BC1
AP3
AP2
BJ19
BD20
BC19
BE28
BG30
BJ16
BK27
BH28
BL24
BK28
BJ27
BJ25
BL28
BA28
BE18
AY20
BA19
OMIT
CRESTLINEFCBGA
U1400AY17
BG18
BG36
BE17
AR50
BD49
BK45
BL39
BH12
BJ7
BF3
AW2
AP49
AR51
BA49
BE50
BA51
AY49
BF50
BF49
BJ50
BJ44
BJ43
BL43
AW50
BK47
BK49
BK43
BK42
BJ41
BL41
BJ37
BJ36
BK41
BJ40
AW51
BL35
BK37
BK13
BE11
BK11
BC11
BC13
BE12
BC12
BG12
AN51
BJ10
BL9
BK5
BL5
BK9
BK10
BJ8
BJ6
BF4
BH5
AN50
BG1
BC2
BK3
BE4
BD3
BJ2
BA3
BB3
AR1
AT3
AV50
AY2
AY3
AU2
AT2
AV49
BA50
BB50
AT50
AU50
BD50
BC50
BK46
BL45
BK39
BK38
BJ12
BK12
BL7
BK7
BE2
BF2
AV2
AV3
BC18
BG28
BG17
BE37
BA39
BG13
BG25
AW17
BF25
BE25
BA29
BC28
AY28
BD37
AV16
AY18
BC17
OMIT
CRESTLINEFCBGA
30B4 72D3
30A6 72D3
30B6 72D3
30B6 72D3
30B4 72D3
30B6 72D3
30B6 72D3
30D4 72D3
30B4 72D3
30B6 72D3
30B4 72D3
30B4 72D3
30B6 72D3
30B4 72D3
30C6 72D3
30C4 72D3
30D4 72D3
30C4 72D3
30A6 72D3
30C6 72D3
30C4 72D3
30C6 72D3
30D6 72D3
30C6 72D3
30C4 72D3
30C6 72D3
30C4 72D3
30C6 72D3
30C6 72D3
30A4 72D3
30C4 72D3
30C4 72D3
30D4 72D3
30D4 72D3
30D6 72D3
30D4 72D3
30D4 72D3
30D6 72D3
30D6 72D3
30D6 72D3
30A4 72D3
30D6 72D3
30D4 72D3
30D4 72D3
30D4 72D3
30D6 72D3
30D6 72D3
30D6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
30C6 32C6 72D3
30A4 72D3
30B6 32B6 72D3
30D4 72C3
30B4 32C6 72D3
30B4 32B6 72D3
30B6 32B6 72D3
30C6 32C6 72D3
30C4 32C6 72D3
30B6 32C6 72D3
30C6 32C6 72D3
30A6 72D3
30C6 32C6 72D3
30C4 32C6 72D3
30C4 32C6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
30B6 32C6 72D3
30B4 32C6 72D3
30D6 72C3
30A4 72D3
30D6 72C3
30C4 72C3
30C6 72C3
30B6 72C3
30B4 72C3
30A4 72C3
30A6 72C3
30D6 72C3
30D6 72C3
30C4 72C3
16 76
01051-7455
NB DDR2 InterfacesSYNC_MASTER=T9_MLB SYNC_DATE=10/30/2006
MEM_A_DQ<35>
TP_MEM_A_RCVEN_L TP_MEM_B_RCVEN_L
MEM_B_DQ<39>
MEM_B_BS<0>
MEM_B_BS<1>
MEM_B_BS<2>
MEM_B_DM<0>
MEM_B_CAS_L
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>
MEM_B_DQ<4>
MEM_B_DQ<5>
MEM_B_DQ<6>
MEM_B_DQ<7>
MEM_B_DQ<8>MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>
MEM_B_DQS_P<1>
MEM_B_DQS_P<0>
MEM_B_DQS_P<4>
MEM_B_DQS_P<3>
MEM_B_DQS_P<2>
MEM_B_DQS_P<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<1>
MEM_B_DQS_P<7>
MEM_B_DQS_N<0>
MEM_B_DQS_N<3>
MEM_B_DQS_N<2>
MEM_B_DQS_N<4>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>
MEM_B_DQS_N<7>
MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<8>
MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>
MEM_B_A<12>
MEM_B_RAS_L
MEM_B_A<13>
MEM_B_WE_L
MEM_B_DQ<9>
MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>
MEM_B_DQ<21>
MEM_B_DQ<22>
MEM_B_DQ<23>
MEM_B_DQ<24>
MEM_B_DQ<25>
MEM_B_DQ<26>
MEM_B_DQ<27>
MEM_B_DQ<28>
MEM_B_DQ<29>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQ<32>
MEM_B_DQ<33>
MEM_B_DQ<34>
MEM_B_DQ<35>
MEM_B_DQ<36>
MEM_B_DQ<37>
MEM_B_DQ<38>
MEM_B_DQ<40>
MEM_B_DQ<41>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<46>
MEM_B_DQ<47>
MEM_B_DQ<48>
MEM_B_DQ<49>
MEM_B_DQ<50>
MEM_B_DQ<51>
MEM_B_DQ<52>
MEM_B_DQ<53>
MEM_B_DQ<54>
MEM_B_DQ<55>
MEM_B_DQ<56>
MEM_B_DQ<57>
MEM_B_DQ<58>
MEM_B_DQ<59>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<62>
MEM_B_DQ<63>
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>
MEM_A_DQ<4>
MEM_A_DQ<6>
MEM_A_CAS_L
MEM_A_BS<2>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<5>
MEM_A_DQ<3>
MEM_A_BS<1>
MEM_A_BS<0>
MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DQS_P<0>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2>
MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_P<5>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<1>
MEM_A_DQS_N<0>
MEM_A_DQS_N<2>
MEM_A_DQS_N<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>
MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<10>
MEM_A_A<11>
MEM_A_A<12>
MEM_A_A<13>
MEM_A_RAS_L
MEM_A_WE_L
MEM_A_DQ<9>
MEM_A_DQ<10>
MEM_A_DQ<11>
MEM_A_DQ<12>
MEM_A_DQ<13>
MEM_A_DQ<14>
MEM_A_DQ<15>
MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>
MEM_A_DQ<19>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>
MEM_A_DQ<24>
MEM_A_DQ<25>
MEM_A_DQ<26>
MEM_A_DQ<27>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<30>
MEM_A_DQ<31>
MEM_A_DQ<32>
MEM_A_DQ<33>
MEM_A_DQ<34>
MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>
MEM_A_DQ<39>
MEM_A_DQ<40>
MEM_A_DQ<41>
MEM_A_DQ<42>
MEM_A_DQ<43>
MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<62>
MEM_A_DQ<63>
VCC_SM20
VCC_AXG_NCTF42
VCC_SM9
VCC_SM10
VCC_SM17
VCC_SM16
VCC3
VCC_SM5
VCC_SM8
VCC_AXG_NCTF1
VCC_AXG_NCTF2
VCC_AXG_NCTF3
VCC_AXG_NCTF4
VCC_AXG_NCTF5
VCC_AXG_NCTF6
VCC_AXG_NCTF8
VCC_AXG_NCTF7
VCC_AXG_NCTF10
VCC_AXG_NCTF9
VCC_AXG_NCTF11
VCC_AXG_NCTF12
VCC_AXG_NCTF13
VCC_AXG_NCTF14
VCC_AXG_NCTF15
VCC_AXG_NCTF16
VCC_AXG_NCTF18
VCC_AXG_NCTF17
VCC_AXG_NCTF20
VCC_AXG_NCTF19
VCC_AXG_NCTF21
VCC_AXG_NCTF22
VCC_AXG_NCTF25
VCC_AXG_NCTF26
VCC_AXG_NCTF28
VCC_AXG_NCTF27
VCC_AXG_NCTF29
VCC_AXG_NCTF20
VCC_AXG_NCTF31
VCC_AXG_NCTF32
VCC_AXG_NCTF33
VCC_AXG_NCTF34
VCC_AXG_NCTF35
VCC_AXG_NCTF36
VCC_AXG_NCTF38
VCC_AXG_NCTF37
VCC_AXG_NCTF40
VCC_AXG_NCTF39
VCC_AXG_NCTF41
VCC_AXG_NCTF43
VCC_AXG_NCTF44
VCC_AXG_NCTF45
VCC_AXG_NCTF46
VCC_AXG_NCTF48
VCC_AXG_NCTF47
VCC_AXG_NCTF49
VCC_AXG_NCTF50
VCC_AXG_NCTF51
VCC_AXG_NCTF55
VCC_AXG_NCTF58
VCC_AXG_NCTF57
VCC_AXG_NCTF59
VCC_AXG_NCTF61
VCC_AXG_NCTF60
VCC_AXG_NCTF62
VCC_AXG_NCTF63
VCC_AXG_NCTF64
VCC_AXG_NCTF66
VCC_AXG_NCTF65
VCC_AXG_NCTF67
VCC_AXG_NCTF68
VCC_AXG_NCTF69
VCC_AXG_NCTF71
VCC_AXG_NCTF70
VCC_AXG_NCTF72
VCC_AXG_NCTF73
VCC_AXG_NCTF74
VCC_AXG_NCTF76
VCC_AXG_NCTF75
VCC_AXG_NCTF77
VCC_AXG_NCTF78
VCC_AXG_NCTF79
VCC_AXG_NCTF81
VCC_AXG_NCTF80
VCC_AXG_NCTF82
VCC_AXG_NCTF83
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
VCC_AXG_NCTF56
VCC_AXG_NCTF54
VCC_AXG_NCTF53
VCC_AXG_NCTF52
VCC_AXG1
VCC_AXG2
VCC_AXG3
VCC_AXG4
VCC_AXG5
VCC_AXG6
VCC_AXG7
VCC_AXG8
VCC_AXG9
VCC_AXG10
VCC_AXG11
VCC_AXG12
VCC_AXG13
VCC_AXG14
VCC_AXG15
VCC_AXG16
VCC_AXG17
VCC_AXG18
VCC_AXG19
VCC_AXG20
VCC_AXG21
VCC_AXG22
VCC_AXG23
VCC_AXG24
VCC_AXG25
VCC_AXG26
VCC_AXG27
VCC_AXG28
VCC_AXG29
VCC_AXG30
VCC_AXG31
VCC_AXG32
VCC_AXG33
VCC_AXG34
VCC_SM1
VCC_SM2
VCC_SM3
VCC_SM4
VCC_SM6
VCC_SM7
VCC_SM11
VCC_SM12
VCC_SM13
VCC_SM14
VCC_SM15
VCC_SM18
VCC_SM19
VCC_SM21
VCC_SM22
VCC_SM23
VCC_SM26
VCC_SM27
VCC_SM28
VCC_SM29
VCC_SM30
VCC_SM31
VCC_SM32
VCC_SM33
VCC_SM34
VCC_SM35
VCC_SM36
VCC_SM25
VCC_SM24
VCC1
VCC2
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC_AXG_NCTF24
VCC_AXG_NCTF23
VCC6
VCC5
VCC4
VCC GFX
VCC SM
VCC SM LF
(6 OF 10)
VCC CORE
POWER
VCC GFX NCTF
VCC_NCTF49
VCC_NCTF15
VCC_NCTF2
VCC_NCTF10
VCC_AXM7
VCC_AXM5
VCC_AXM4
VCC_AXM3
VCC_AXM2
VCC_AXM1
VSS_SCB6
VSS_SCB5
VSS_SCB4
VSS_SCB3
VSS_SCB2
VSS_SCB1
VCC_NCTF11
VCC_NCTF12
VCC_NCTF13
VCC_NCTF14
VSS_NCTF21
VSS_NCTF20
VSS_NCTF19
VSS_NCTF18
VSS_NCTF17
VSS_NCTF16
VSS_NCTF15
VSS_NCTF14
VSS_NCTF12
VSS_NCTF11
VSS_NCTF13
VSS_NCTF10
VSS_NCTF9
VSS_NCTF8
VSS_NCTF7
VSS_NCTF6
VSS_NCTF5
VSS_NCTF4
VSS_NCTF3
VSS_NCTF2
VSS_NCTF1
VCC_NCTF22
VCC_NCTF27
VCC_NCTF50
VCC_NCTF47
VCC_NCTF48
VCC_NCTF44
VCC_NCTF43
VCC_NCTF39
VCC_NCTF40
VCC_NCTF38
VCC_NCTF37
VCC_NCTF34
VCC_NCTF35
VCC_NCTF33
VCC_NCTF32
VCC_NCTF31
VCC_NCTF29
VCC_NCTF28
VCC_NCTF26
VCC_NCTF24
VCC_NCTF25
VCC_NCTF23
VCC_NCTF21
VCC_NCTF18
VCC_NCTF19
VCC_NCTF16
VCC_NCTF17
VCC_NCTF3
VCC_NCTF4
VCC_NCTF41
VCC_NCTF42
VCC_NCTF45
VCC_NCTF46VCC_AXM6
VCC_AXM_NCTF1
VCC_AXM_NCTF2
VCC_AXM_NCTF3
VCC_AXM_NCTF4
VCC_AXM_NCTF5
VCC_AXM_NCTF6
VCC_AXM_NCTF7
VCC_AXM_NCTF8
VCC_AXM_NCTF9
VCC_AXM_NCTF10
VCC_AXM_NCTF11
VCC_AXM_NCTF12
VCC_AXM_NCTF13
VCC_AXM_NCTF14
VCC_AXM_NCTF15
VCC_AXM_NCTF16
VCC_AXM_NCTF17
VCC_AXM_NCTF18
VCC_AXM_NCTF19
VCC_NCTF8
VCC_NCTF20
VCC_NCTF1
VCC_NCTF5
VCC_NCTF6
VCC_NCTF7
VCC_NCTF36
VCC_NCTF30
VCC_NCTF9
VCC AXM NCTF
VCC NCTF
VSS SCB
VCC AXM
VSS NCTF
(7 OF 10)
POWER
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
1395 mA (1 ch, 533MHz)
1700 mA (1 ch, 667MHz)
2700 mA (2 ch, 533MHz)
3300 mA (2 ch, 667MHz)
540 mA
1573 mA (Int Graphics)
1310 mA (Ext Graphics)
7700 mA (Int Graphics)
5 mA (standby)
impacting part performance.
These connections can break without
NCTF balls are Not Critical To Function
Current numbers from Crestline EDS, doc #21749.
U1400
AT35
AH31
AH29
AF32
R30
AT34
AH28
AC31
AC32
AK32
AJ31
AJ28
AH32
R20
AB21
AB24
AB29
AC20
AC21
AC23
AC24
AC26
AC28
AC29
T14
AD20
AD23
AD24
AD28
AF21
AF26
AA31
AH20
AH21
AH23
W13
AH24
AH26
AD31
AJ20
AN14
W14
Y12
AA20
AA23
AA26
AA28
T17
U17
U19
U20
U21
U23
U26
V16
V17
V19
V20
T18
V21
V23
V24
Y15
Y16
Y17
Y19
Y20
Y21
Y23
T19
Y24
Y26
Y28
Y29
AA16
AA17
AB16
AB19
AC16
AC17
T21
AC19
AD15
AD16
AD17
AF16
AF19
AH15
AH16
AH17
AH19
T22
AJ16
AJ17
AJ19
AK16
AK19
AL16
AL17
AL19
AL20
AL21
T23
AL23
AM15
AM16
AM19
AM20
AM21
AM23
AP15
AP16
AP17
T25
AP19
AP20
AP21
AP23
AP24
AR20
AR21
AR23
AR24
AR26
U15
V26
V28
V29
Y31
U16
AU32
BA35
BB33
BC32
BC33
BC35
BD32
BD35
BE32
BE33
BE35
AU33
BF33
BF34
BG32
BG33
BG35
BH32
BH34
BH35
BJ32
BJ33
AU35
BJ34
BK32
BK33
BK34
BK35
BL33
AU30
AV33
AW33
AW35
AY35
BA32
BA33
AW45
BC39
BE39
BD17
BD4
AW8
AT6
OMIT
FCBGA
CRESTLINE
U1400
AT33
AT31
AK29
AK24
AK23
AJ26
AJ23
AL24
AP29
AP31
AP32
AP33
AL29
AL31
AL32
AR31
AR32
AR33
AL26
AL28
AM26
AM28
AM29
AM31
AM32
AM33
AB33
AF36
AH33
AH35
AH36
AH37
AJ33
AJ35
AK33
AK35
AK36
AB36
AK37
AD33
AJ36
AM35
AL33
AL35
AA33
AA35
AA36
AP35
AB37
AP36
AR35
AR36
Y32
Y33
Y35
Y36
Y37
T30
T34
AC33
T35
U29
U31
U32
U33
U35
U36
V32
V33
V36
AC35
V37
AC36
AD35
AD36
AF33
T27
AD19
AD37
AF17
AF35
AK17
AM17
AM24
AP26
AP28
AR15
T37
AR19
AR28
U24
U28
V31
V35
AA19
AB17
AB35
A3
B2
C1
BL1
BL51
A51
OMIT
CRESTLINEFCBGA
C1806 1
2
402
0.1uF
10VCERM
20%
C1807 1
2
402
0.1uF
10VCERM
20%
C1804 1
2
402X5R
0.22UF
6.3V20%
C1805 1
2
402X5R
0.22UF
6.3V20%
C1802 1
2
402
10%
CERM
1uF
6.3V
C1803 1
2
402
10%0.47UF
6.3VCERM-X5R
C1801 1
2
402
10%
CERM
1uF
6.3V
17 76
01051-7455
NB Power 1SYNC_DATE=10/30/2006SYNC_MASTER=T9_MLB
=PPVCORE_S0_NB
=PP1V05_S0M_NB_VCCAXM
=PPVCORE_S0_NB_GFX
=PP1V8_S3M_MEM_NB
=PPVCORE_S0_NB
=PPVCORE_S0_NB_GFX
NB_VCCSM_LF6
NB_VCCSM_LF4
NB_VCCSM_LF3
NB_VCCSM_LF2
NB_VCCSM_LF1
NB_VCCSM_LF7
NB_VCCSM_LF5
=PP1V05_S0M_NB_VCCAXM
31D2
20D8
48B3
30D2
20D8
48B3
20B4
20D8
21C5
20C8
20B4
21C5
20D8
17D7
17C1
17B7
15D2
17D3
17D5
17B3
7C7
7C7
7B7
7A4
7C7
7B7
7C7
VCCA_CRT_DAC1
VTT7
VTT8
VCC_AXD_NCTF
VCCD_CRT
VCC_RXR_DMI1
VCC_RXR_DMI2
VTT1
VCCA_SM_CK2 VCC_TX_LVDS
VCC_HV2
VCC_PEG1
VCC_PEG2
VCC_PEG3
VCC_AXF2
VCC_AXD1
VCC_AXD2
VSSA_LVDS
VCCA_SM5
VCCA_PEG_PLL
VCCA_MPLL
VCCA_HPLL VTT16
VTT17
VTT15
VCCD_LVDS2
VCCD_LVDS1
VCCD_PEG_PLL
VCCD_HPLL
VCCD_QDAC
VCCD_TVDAC
VCCA_TVC_DAC1
VCCA_TVC_DAC2
VCCA_TVB_DAC2
VCCA_TVB_DAC1
VCCA_TVA_DAC2
VCCA_TVA_DAC1
VCCA_SM_CK1
VCCA_SM2
VCCA_SM1
VCCA_SM_NCTF2
VCCA_SM_NCTF1
VCCA_SM11
VCCA_SM10
VCCA_SM9
VCCA_SM8
VCCA_SM7
VCCA_SM4
VCCA_SM3
VSSA_PEG_BG
VCCA_PEG_BG
VCCA_LVDS
VCCA_DPLLB
VCCA_DPLLA
VSSA_DAC_BG
VCCA_DAC_BG
VCC_AXF3
VCC_HV1
VCC_PEG5
VTTLF1
VTTLF3
VTTLF2
VCC_PEG4
VCC_SM_CK3
VCC_SM_CK2
VCC_SM_CK1
VCC_SM_CK4
VCC_DMI
VCC_AXF1
VTT22
VCC_AXD6
VCC_AXD5
VCC_AXD4
VCC_AXD3
VTT19
VTT2
VTT6
VTT5
VTT11
VTT10
VTT9
VTT13
VTT12
VTT14
VTT18
VTT21
VTT20
VTT3
VTT4VCCA_CRT_DAC2
VCC_SYNC
CRT
AXD
PEG
HV
AXF
VTTLF
VTT
SM CK
DMI
TV/CRT
DLVDS
A SM
A CK
CRT
A LVDS
A PEG
PLL
(8 OF 10)
POWER
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
100 mA
100 mA
100 mA
200 mA
5 mA
50 mA
100 mA
10 mA
40 mA
40 mA
40 mA
60 mA
250 mA
150 mA
5 mA
S0 or S3M is acceptable
S0 or S3M is acceptable
TBD mA @ 1067MHz FSB (1.25V)
150 mA
770 mA @ 667MHz FSB (1.05V)
1260 mA
260 mA
0.4 mA
80 mA
30 mA
60 mA
100 mA
35 mA
850 mA @ 800MHz FSB (1.05V)
495 mA
515 mA
Current numbers from Crestline EDS, doc #21749.
640 mA (667MHz DDR)
550 mA (533MHz DDR)
C19111
2
0.47UF10%
CERM-X5R402
6.3V
C19131
2
0.47UF10%6.3VCERM-X5R402
C19121
2
0.47UF10%6.3VCERM-X5R402
U1400
AT23
AU28
AU24
AT29
AT25
AT30
AR29
B23
B21
A21
AJ50
C40
B40
AD51
W50
W51
V49
V50
AH50
AH51
BK24
BK23
BJ24
BJ23
J32
A43
A33
B33
A30
B49
H49
AL2
A41
AM2
K50
U51
AW18
AT18
AT17
AV19
AU19
AU18
AU17
AT22
AT21
AT19
BC29
BB29
AR17
AR16
C25
B25
C27
B27
B28
A28
M32
AN2
J41
H42
U48
N28
L29
B32
B41
K49
U13
U1
T13
T11
T10
T9
T7
T6
T5
T3
T2
U12
R3
R2
R1
U11
U9
U8
U7
U5
U3
U2
A7
F2
AH1
OMIT
FCBGA
CRESTLINE
051-7455 01
7618
NB Power 2SYNC_DATE=10/30/2006SYNC_MASTER=T9_MLB
NB_VTTLF_CAP2
=PP1V8_S0_NB_VCCD_LVDS
PP1V25_S0_NB_VCCA_DPLLA
PP1V25_S0M_NB_VCCA_HPLL
PP3V3_S0_NB_VCCA_TVDACA
=PP1V5_S0_NB_VCCD_CRT
PP1V5_S0_NB_VCCD_TVDAC
PP1V5_S0_NB_VCCD_QDAC
=PP1V25_S0M_NB_VCCD_HPLL
=GND_NB_VSSA_LVDS
PP3V3_S0_NB_VCCA_DAC_BG
PP1V25_S0M_NB_VCCA_MPLL
NB_VTTLF_CAP1
NB_VTTLF_CAP3
=PP1V25_S0_NB_VCCDMI
=GND_NB_VSSA_DAC_BG
=GND_NB_VSSA_PEG_BG
PP1V8_S0_NB_VCCTXLVDS
PP1V05_S0_NB_VCCPEG
=PP3V3_S0_NB_VCCHV
PP1V05_S0_NB_VCCRXRDMI
PP1V25_S0_NB_VCCAXF
PP1V25_S0M_NB_VCCAXD
PP3V3_S0_NB_VCCA_TVDACC
PP1V25_S0_NB_VCCA_DPLLB
PP3V3_S0_NB_VCCA_TVDACB
=PP1V25R1V05_S0_NB_VTT
PP1V8_S0_NB_VCCTXLVDS
PP3V3_S0_NB_VCCA_CRTDAC
=PP3V3_S0_NB_VCCSYNC
PP1V25_S0M_NB_VCCA_SM_CK
PP1V25_S0_NB_PEGPLL
PP1V8_S3M_NB_VCCSMCK
PP1V25_S0M_NB_VCCA_SM
=PP3V3_S0_NB_VCCA_PEG_BG
21B7 20A8 15C7
20A8
21C3
20D3
15B7
20A6
20C8
21C3
21B5
20A6
21B3
21A3
20D1
21D1
21C7
21D6
21C5
20D1
21B3
21B1
20C1
7C7
21B1
20A6
18C6
14D2
7D4
20C3
20D5
15A2
21C1
21A3
21C1
7C7
18B3
21D1
7C4
20B5
20B2
20A2
20B5
7C4
VSS198VSS99
VSS197VSS98
VSS196VSS97
VSS195VSS96
VSS194VSS95
VSS193VSS94
VSS192VSS93
VSS191VSS92
VSS190VSS91
VSS189VSS90
VSS188VSS89
VSS187VSS88
VSS186VSS87
VSS185VSS86
VSS184VSS85
VSS183VSS84
VSS182VSS83
VSS181VSS82
VSS180VSS81
VSS179VSS80
VSS178VSS79
VSS177VSS78
VSS176VSS77
VSS175VSS76
VSS174VSS75
VSS173VSS74
VSS172VSS73
VSS171VSS72
VSS170VSS71
VSS169VSS70
VSS168VSS69
VSS167VSS68
VSS166VSS67
VSS165VSS66
VSS164VSS65
VSS163VSS64
VSS162VSS63
VSS161VSS62
VSS160VSS61
VSS159VSS60
VSS158VSS59
VSS157VSS58
VSS156VSS57
VSS155VSS56
VSS154VSS55
VSS153VSS54
VSS152VSS53
VSS151VSS52
VSS150VSS51
VSS149VSS50
VSS148VSS49
VSS147VSS48
VSS146VSS47
VSS145VSS46
VSS144VSS45
VSS143VSS44
VSS142VSS43
VSS141VSS42
VSS140VSS41
VSS139VSS40
VSS138VSS39
VSS137VSS38
VSS136VSS37
VSS135VSS36
VSS134VSS35
VSS133VSS34
VSS132VSS33
VSS131VSS32
VSS130VSS31
VSS129VSS30
VSS128VSS29
VSS127VSS28
VSS126VSS27
VSS125VSS26
VSS124VSS25
VSS123VSS24
VSS122VSS23
VSS121VSS22
VSS120VSS21
VSS119VSS20
VSS118VSS19
VSS117
VSS116VSS17
VSS115VSS16
VSS114VSS15
VSS113VSS14
VSS112VSS13
VSS111VSS12
VSS110VSS11
VSS109VSS10
VSS108VSS9
VSS107VSS8
VSS106VSS7
VSS105VSS6
VSS104VSS5
VSS103VSS4
VSS102
VSS101
VSS100VSS1
VSS18
VSS2
VSS3
VSS
(9 OF 10)
VSS202
VSS289
VSS290
VSS291
VSS292
VSS295
VSS199 VSS287
VSS200 VSS288
VSS201
VSS203
VSS204
VSS293
VSS294
VSS208 VSS296
VSS209 VSS297
VSS210 VSS298
VSS211 VSS299
VSS212 VSS300
VSS213 VSS301
VSS214
VSS215
VSS216 VSS302
VSS217
VSS218
VSS219 VSS303
VSS220
VSS221
VSS222 VSS304
VSS223
VSS224
VSS225 VSS305
VSS226
VSS227
VSS228
VSS229 VSS306
VSS230 VSS307
VSS231 VSS308
VSS232 VSS309
VSS233 VSS310
VSS234 VSS311
VSS235 VSS312
VSS236 VSS313
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
VSS286
VSS207
VSS206
VSS205
(10 OF 10)
VSS
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TDE_SENSE
TDE_FORCE
TDB_FORCE
alias these nets directly to GND.
Mainly for investigation. If not used,
NOTE: TDB = _N
TDB_SENSE
Crestline Thermal Diode Pins
NOTE: TDE = _P
U1400
A13
AB26
AW24
AW29
AW32
AW5
AW7
AY10
AY24
AY37
AY42
AY43
AB28 AY45
AY47
AY50
B10
B20
B24
B29
B30
B35
B38
AB31
B43
B46
B5
B8
BA1
BA17
BA18
BA2
BA24
BB12
AC10
BB25
BB40
BB44
BB49
BB8
BC16
BC24
BC25
BC36
BC40
AC13
BC51
BD13
BD2
BD28
BD45
BD48
BD5
BE1
BE19
BE23
AC3
BE30
BE42
BE51
BE8
BF12
BF16
BF36
BG19
BG2
BG24
AC39
BG29
BG39
BG48
BG5
BG51
BH17
BH30
BH44
BH46
BH8
AC43
BJ11
BJ13
BJ38
BJ4
BJ42
BJ46
BK15
BK17
BK25
BK29
AC47
BK36
BK40
BK44
BK6
BK8
BL11
BL13
BL19
BL22
BL37
AD1
BL47
C12
C16
C19
C28
C29
C33
C36
C41
A15
AD21
AD26
AD29
AD3
AD41
AD45
AD49
AD5
AD50
AD8
A17
AE10
AE14
AE6
AF20
AF23
AF24
AF31
AG2
AG38
AG43
A24
AG47
AG50
AH3
AH40
AH41
AH7
AH9
AJ11
AJ13
AJ21
AA21
AJ24
AJ29
AJ32
AJ43
AJ45
AJ49
AK20
AK21
AK26
AK28
AA24
AK31
AK51
AL1
AM11
AM13
AM3
AM4
AM41
AM45
AN1
AA29
AN38
AN39
AN43
AN5
AN7
AP4
AP48
AP50
AR11
AR2
AB20
AR39
AR44
AR47
AR7
AT10
AT14
AT41
AT49
AU1
AU23
AB23
AU29
AU3
AU36
AU49
AU51
AV39
AV48
AW1
AW12
AW16
FCBGA
OMIT
CRESTLINE
U1400
C46
C50
C7
D13
D24
D3
D32
D39
D45
D49
E10
E16
E24
E28
E32
E47
F19
F36
F4
F40
F50
G1
G13
G16
G19
G24
G28
G29
G33
G42
G45
G48
G8
H24
H28
H4
H45
J11
J16
J2
J24
J28
J33
J35
J39
K12
K47
K8
L1
L17
L20
L24
L28
L3
L33
L49
M28
M42
M46
M49
M5
M50
M9
N11
N14
N17
N29
N32
N36
N39
N44
N49
N7
P19
P2
P23
P3
P50
R49
T39
T43
T47
U41
U45
U50
V2
V3
W11
W39
W43
W47
W5
W7
Y13
Y2
Y41
Y45
Y49
Y5
Y50
Y11
P29
T29
T31
T33
R28
AA32
AB32
AD32
AF28
AF29
AT27
AV25
H50
FCBGA
OMIT
CRESTLINE
051-7455 01
7619
NB GroundsSYNC_MASTER=T9_MLB SYNC_DATE=10/30/2006
=NB_TDB_SENSE
=NB_TDB_FORCE
=NB_TDE_FORCE
=NB_TDE_SENSE
8A2
8A2
8A2
8A2
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
this is "1 of 2" 1.8V bulk decoupling caps.
spec requires "3.9uH ferrite,1A,32mohm max".
5.6nH,0.9A,45mohm max.no bigger than 0603
WF: Matanzas has 270uF
and DDR2 taps." (C2125)
Memory I/O logic and DLL voltage.
WF: 220-ohm
Memory voltage supply.
??? mA
540 mA
These supplies are still needed even using external GPU
250mA,0.5ohm
250mA,0.5ohm
MPLL Analog Supply
GMCH Core Power
100 mA
450 mA
Host PLL Analog Supply
200 mA
LAYOUT NOTE: PLACE THOSE COMPONENT CLOSE TO GMCH
200 mA
5 mA
Current numbers from Crestline EDS Addendum, doc #20127.
50 mA
150 mA
850 mA
GMCH FSB I/O Rail
200 mA
100 mA100 mA
Memory clock logic voltage.
200 mA
250 mA
Host PLL Digital Supply
Layout Note: Route to caps, then GND
WF: Should be 1.0, 1%
100 mA??? mA
1200 mA
Layout Note:
be close to MCHon opposite side.
Analog PLL Voltage for PCI-E GPU
need to find "1uH,220mA,150mohm max"
I/O voltage Supply
350 mA
1450 mA
Layout Note:
??? mA
WF: "Place where LVDS
Place L and Cclose to MCH
GMCH ME Core Power
GMCH Memory I/O Rail
2400 mA
WF: Should be 1.0, 1%
NOTE: This follower is redundant if VCORE is always 1.05V.
on opposite side.be close to MCH10uF caps shouldLayout Note:
250 mA
RX and I/O Logic for DMI
10uF caps should
Analog,I/O logic,and Term Voltage for PCI-E Graphics
C2124 1
2CERM-X5R
10%0.47UF
6.3V
402
C2123 1
26.3VCERM1
603
2.2uF20%
C2121 1
2
4.7uF6.3VCERM
20%
603
C2100 1
2 3
470UF20%2.5VTANTD2T
C21121
2402X5R6.3V20%0.22uF
C21111
2402
6.3V20%
X5R
C2122 1
220%
4.7uF6.3VCERM603
C21311
2805CERM
22UF
PLACEMENT_NOTE=Place close to U1400
20%6.3V
C21321
2805CERM
22UF6.3V20%
PLACEMENT_NOTE=Place close to U1400
C21351
2 CERM
20%0.1UF10V
R21831
2
1/16WMF-LF402
1%0.51
R21901
2MF-LF1/16W
1%
402
1.1
1 2
C2190 1
2X5R
20%6.3V
10uF
1
2
C21741
2
10uF20%6.3VX5R603
C2173 1
220%
POLY2.5V
220UF
CASE-B2
L2173
1 2
91NH
1210
R21951
2402
1/16WMF-LF
1%1.1
L2195
1 2
1.0UH-0.23A
0603
C2195 1
26.3V20%
10uF
X5R603
C2196 1
2CERM
22UF
805
20%6.3V
C21711
2402
1UF10%6.3VCERM
C2170 1
2
10uF20%6.3VX5R603
C21511
1UF
402CERM
10%
C2150 1
2
10uF6.3VX5R603
20%
NOSTUFF
C21421
2805CERM
22UF20%6.3V
C21431
2
4.7UF
603
6.3V10%
X5R-CERM
C21441
2
1UF
CERM6.3V10%
402
R21411 2
MF-LF1/16W
0
5%
C21451
2805CERM
22UF6.3V20%
1 2
5%
0
C21471
2402-LF
NOSTUFF
20%2.2UF6.3VCERM
C21481
2402CERM10V20%0.1UF
R21861 2
402MF-LF1/16W1%
10
R21121
2
1%1/16W
402
1K
1
2
1/16WMF-LF
1%
402
1K
R21101
2
1%
MF-LF1/16W
1K
402
R21111
2
1/16WMF-LF
1%
402
1K
L2183
1 2
0402-LF
120-OHM-0.3A-EMI
C21131
220%0.1UF
CERM10V
402
C21141
2 CERM10V20%0.1UF
402
C21151
220%10VCERM402
1
2 CERM10V20%0.1UF
402
C21611
2402
20%10VCERM 2
402CERM10V20%
C21971
2
0.1UF
402CERM10V20%
C21911
2 CERM10V20%0.1UF
402
C21921
2
0.1UF10VCERM402
20%
C21821
2402
0.1UF
CERM10V20%
C21801
2
0.1UF
402CERM10V20%
C21101
2805CERM
22UF20%6.3V
R21091 2
MF-LF402
0
1/16W5%
D218612
1SS418
SOD-723
L2181
1 2
120-OHM-0.3A-EMI
0402-LF
C21041
2402
20%10V
0.1UF
CERM
C21771
2
10uF20%6.3VX5R603
C21031
2
PLACEMENT_NOTE=Place in GMCH cavity
6.3V20%
X5R402
0.22uFC21021
2402
PLACEMENT_NOTE=Place in GMCH cavity
X5R
20%0.22uF6.3V
C21841
2 10VCERM402
PLACEMENT_NOTE=Place C2184 by U1400.AM2
0.1UF20%
C2181 1
2CERM
22UF6.3V20%
805
C2183 1
2
22UF
CERM805
20%6.3V
C21011
2805CERM
22UF
PLACEMENT_NOTE=Place in GMCH cavity
6.3V20%
76
01
20
SYNC_DATE=06/15/2006SYNC_MASTER=WFERRY
NB Standard Decoupling
051-7455
PP1V25_S0M_NB_VCCA_SMMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.25V
=PPVCORE_S0_NB
=PP1V25_S0_NB_VCC
=PP0V9_S3M_MEM_NBVREFB
=PP3V3_S0_NB_VCCHV
=PP1V8_S3_NB_VCC
=PP3V3_S0_NB_FOLLOW
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.8V
PP1V8_S3_NB_VCCSMCK_RC
=PP1V8_S3_MEMVREF
PP1V25_S0M_NB_VCCA_MPLLMIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.25V
=PP1V25_S0M_NB_VCCD_HPLL
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 mmVOLTAGE=0.9V
MIN_LINE_WIDTH=0.4 MM
PP0V9_S3M_MEM_NBVREFB
=GND_NB_VSSA_PEG_BG
=PP1V25_S0_NB_VCCDMI
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.4 MMMAKE_BASE=TRUE
MIN_LINE_WIDTH=0.25 MM
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MM
PP1V25_S0_NB_PEGPLL
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM
VOLTAGE=1.05V
=PP1V25_S0_NB_PLLMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.25V
PP1V25_S0_NB_VCCAXF =PP1V25_S0_NB_VCCAXF
=PP1V05_S0_NB_PCIE
MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.8V
MIN_LINE_WIDTH=0.25 MMPP1V8_S3M_NB_VCCSMCK
MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.05V
=PP1V25_S0_NB_PLL
=PP1V25R1V05_S0_NB_VTT
=PPVCORE_S0_NB
PP1V25_S0M_NB_VCCA_HPLL
MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.25V
MIN_LINE_WIDTH=0.25 MM
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MM
PP1V25_S0M_NB_MPLL_RCMIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.25V
PP1V25_S0M_NB_VCCA_SM_CKMIN_LINE_WIDTH=0.4 MM
PP1V25_S0_NB_PEGPLL_RC
VOLTAGE=1.25V
=PP1V05_S0M_NB_VCCAXM
PLACEMENT_NOTE=Place in GMCH cavity
0.22uF 0.1UF
CRITICAL
=PP1V25_S0_NB_VCCA
402
R2145
1/16WMF-LF402
PP1V25_S0M_NB_VCCAXDMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.25V
6.3V2
=PP3V3_S0_NB_VCCA_PEG_BG
1
0.1UF 0.1UFC2165
R2113
=PP0V9_S3M_MEM_NBVREFA
VOLTAGE=0.9V
MF-LF
PP0V9_S3M_MEM_NBVREFA
=PP1V8_S3_MEMVREF
603
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MM
0603
FERR-220-OHM-2.5AL2190
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP3V3_S0_NBCORE_FOLLOW_R
PP1V05_S0_NB_VCCRXRDMI
PP1V05_S0_NB_VCCPEG
CRITICAL
CRITICALOMIT
PLACEMENT_NOTE=Place close to U1400
402
C2160
CRITICAL
CASE-C2POLY2.5V20%
330UFC2130
=PP1V8_S3M_MEM_NB
CRITICAL
20%
POLY
330UF2.0V
CASE-B2
2
1C2140
OMIT
OMIT
21B7
31D2
20D8
18B3
20B4
30D2
17D7
15C7
17D7
17C1
17D7
17D3
18C3
15B7
20A6 20A5
18C3
20B4
18B3
20D3
18D3
17D3
17B3
15D2
18C6
18C6 7C7
15A2 7C7
15C2
7D4
7A4
7D4
7B4 7B4
18D6
18A6
18C6
7C7
18C6
18B3
7C7
18C3 7C7
7C7
18B3
14D2
7C7
7C7
7C7
7C7
18D6
7C7
7A4
18B6
7C4
OUTEN NR/FBIN
GND
THRMLNC
EN
IN OUT
NR
PADGND
OUT
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
WF: Matanzas has 2x 330uF
NEED TO FIND A "1#GH, 500MA, 78MOHM" INDUCTORWF: Should be 1uH, 30%
260 mA
Layout Note: Route to cap, then GND
WARNING VOLTAGE DROP
VCCD_TVDAC also powers internal thermal sensors.
0011=1.21025V1000=1.08150V
VID<3:0>=1001=1.05575V
65 mA
WF: Check part properties
10 mA
6 mA
5 mA
Vout = 1.204V * (Ra + Rb)/Rb
110 mA
Layout Note:
80 mA80 mA
WF: Is this the best part to use?
These 2 caps should bewithin 6.35 mm of NB edge
80 mA
125 mA
80 mA
Layout Note:These 8 caps should be
Layout Note: Route to caps, then GND
within 6.35 mm of NB edge
40 mA
5 mA
40 mA
40 mA
80 mA
Layout Note:
Current numbers from Crestline EDS Addendum, doc #20127.
150 mA
60 mA
(1.7V - 5.5V)
NC
205 mA
Ra || Rb should be 19Kohms
7700 mA
WF: Check C2266 value, R2267 value
GMCH Graphics Core PowerThese 4 caps should bewithin 6.35 mm of NB edge
205 mA
NOTE: This filter is required even if using only external graphics.
C2289
2
1 3
CRITICAL
22000pF-1000mANFM1816V
C2282 1
2
0.01UF
CERM402
10%16V
R22051
2MF-LF
5%1001/16W
402
C22071
2402
0.1UF
CERM10V20%
R22811
2 402
1/16WMF-LF
5%0
C22811
21UF
NO STUFF
CERM4026.3V10%
C2280 1
2402CERM6.3V
1UF10%
C2292
2
1 3
CRITICAL
22000pF-1000mANFM1816V
C22911
2
0.1UF
402
20%10VCERM
C2294
2
1 3
22000pF-1000mA
CRITICAL
NFM1816V
C22931
2402
20%10VCERM
0.1UF
C22881
2402
20%10VCERM
0.1UF
C2296
2
1 3
CRITICAL
NFM18
22000pF-1000mA16V
C22951
2402
20%10VCERM
0.1UF
C2298
2
1 3
CRITICAL
22000pF-1000mANFM1816V
C22971
2402
20%10VCERM
0.1UF
C2290 1
2
10uF
603X5R
20%6.3V
L2290
1 2
120-OHM-0.3A-EMI
0402-LF
R22611 2
1/16W5%
MF-LF
0
402C22611
2
0.1UF
402CERM10V20%
R22621 2
1/16WMF-LF
5%
0
402C22621
220%10VCERM
0.1UF
C22231
2 CERM
0.001uF
402
50V20%
C22211
2
0.001uF
402CERM50V20%
C2201
2
1 3
22000pF-1000mA
CRITICAL
16VNFM18
C2206
2
1 3NFM1816V
22000pF-1000mA
CRITICAL
C22001
2402
20%10VCERM
0.1UF
C22051
2 X5R
10%1UF10V
402
L2220
1 2
1007
C2220 1
CASE-B2-SM
220UF20%
POLY
CRITICAL
C22171
2
PLACEMENT_NOTE=Place in GMCH cavity
20%
402
10VCERM
0.1UFC22161
2402
20%10VCERM
0.1UF
PLACEMENT_NOTE=Place in GMCH cavity
C22151
2402CERM-X5R6.3V10%0.47UF
PLACEMENT_NOTE=Place in GMCH cavity
C22131
2603X5R6.3V20%10uF
PLACEMENT_NOTE=Place in GMCH cavity
C22121
2 6.3V
805
PLACEMENT_NOTE=Place in GMCH cavity
20%22UF
CERM
C2210 1
2 3
CRITICAL
2.5V
D2TTANT
470UF20%
C22261
2
1UF10%6.3V
402CERM
R22851 2
NO STUFF
1%
MF-LF1/16W
402
10
L2288
1 2
120-OHM-0.3A-EMI
0402-LF
C22141
2402
6.3V10%
CERM
1UF
PLACEMENT_NOTE=Place in GMCH cavity
C2265 1
210%1UF
CERM6.3V
402
R22661
2 603FF
0.3005%1/10W
C22661
2603
10UF20%
X5R6.3V
C22301
2 10VCERM402
20%0.1UF
C22851
220%10UF
603X5R6.3V
U2265
3
2
145
CRITICAL
TPS731125SOT23-5
C22671
210%
CERM
0.01UF16V
402
D228512
1SS418
SOD-723
NO STUFF
U2280
4
3
6
5
2
1
7
CRITICAL
SONTPS79933
15B3 60C6
15B3 60C6
15B3 60C6
15B3 60C6
R22451
2
1/16WMF-LF
5%22K
402
R22501
2MF-LF402
22K5%1/16W
NO STUFF
R22441
2
1/16WMF-LF
5%22K
402
NO STUFF
R22431
2
22K5%
MF-LF1/16W
402
NO STUFF
R2249
2MF-LF1/16W5%22K
402
1
2
1/16WMF-LF402
22K5%
R22421
2402
1/16W
22K5%
MF-LF
1
2402
1/16WMF-LF
22K
NB Graphics Decoupling
01
76
SYNC_MASTER=WFERRY SYNC_DATE=06/15/2006
21
051-7455
VOLTAGE=1.5V
PP1V5_S0_NB_VCCD_QDACMIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MMPP1V5_S0_NB_QDAC
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.6MM
PP3V3_S0_NB_TVDAC
PP1V8_S0_NB_VCCTXLVDS
MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.8V
MIN_LINE_WIDTH=0.2 MM=PP3V3_S0_NB_VCCHV
=GND_NB_VSSA_DAC_BG
P3V3TVDAC_EN_RC
=PP1V8_S0_NB_DPLL
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V
PP3V3_S0_NB_VCCA_CRTDAC
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM
PP3V3_S0_NB_VCCA_TVDACA
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM
VOLTAGE=3.3V
PP3V3_S0_NB_VCCA_TVDACC
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MM
VOLTAGE=3.3V
PP3V3_S0_NB_VCCA_DAC_BG
PP3V3_S0_NB_TVDAC_F
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MMVOLTAGE=1.25V
PP1V25_S0_NB_VCCA_DPLLBMIN_LINE_WIDTH=0.3 MM
PP3V3_S0_NB_VCCA_TVDACBMIN_LINE_WIDTH=0.3 MM
VOLTAGE=3.3V
P3V3TVDAC_NOISE
MIN_LINE_WIDTH=0.4 MMPP3V3_S0_NB_TVDAC_FOLLOW
MIN_NECK_WIDTH=0.2 MMVOLTAGE=3.3V
PP1V25_S0_NB_DPLL_RF
P1V25S0NBDPLL_FB
PP1V5_S0_NB_VCCD_CRTMIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=1.5V
PP1V5_S0_NB_VCCD_TVDAC
VOLTAGE=1.5V
MIN_LINE_WIDTH=0.3 MMMIN_NECK_WIDTH=0.2 MM
PP1V5_S0_NB_VCCD_CRTMAKE_BASE=TRUE
=PP1V5_S0_NB_VCCD_CRT
=GND_NB_VSSA_LVDS
=PP3V3_S0_NB_VCCSYNC
VOLTAGE=1.25VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP1V25_S0_NB_DPLL
VOLTAGE=1.25V
PP1V25_S0_NB_VCCA_DPLLAMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.3 MM
=PPVCORE_S0_NB_GFX
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V
PP3V3_S0_NB_CRTDAC_F
GFX_VID<2>
GFX_VID<1>GFX_VID<0>
GFX_VID<3>
R2247 1R22485%
NO STUFF
=PP1V5_S0_NB_TVDAC
=PP1V8_S0_NB_VCCD_LVDS
402
MIN_NECK_WIDTH=0.2 MM
=PP1V5_S0_NB_FOLLOW
=PP5V_S0_NB_TVDAC
22.5V
1.0UH-0.5A-0.675A=PP1V8_S0_NB_LVDS
OMIT
20A8 18B3
48B3
15C7
17D5
18C6
15B7
18D6
17B7
7A7
7B7
18B6
18B3
7D4
18D6
7B7
18D6
18B6
18B6
18D6
18D6
18B6
21C5
18B6
21D6 18B6
18C6
18A6
7B7
7C4
18D6
7B7
7B7
SATA0RXP
SATA0RXN
SATALED*
RTCRST*
HDA_BIT_CLK
DDREQ
RTCX1
RTCX2
DCS1*
DCS3*
IDEIRQ
DDACK*
IORDY
DIOR*
DIOW*
DD11
DD12
DD4
DD2
DD14
DD0
DD15
DD1
DD13
DD5
DD10
DD8
DD3
DD9
LDRQ0*
FWH2/LAD2
FWH3/LAD3
FWH1/LAD1
LDRQ1*/GPIO23
FWH0/LAD0
FWH4/LFRAME*
HDA_SDIN0
HDA_SYNC
SATA1TXN
SATA1TXP
HDA_SDIN1
HDA_SDIN2
RCIN*
SATA0TXP
SATA0TXN
CPUPWRGD/GPIO49
SMI*
A20M*
SATA1RXP
SATA1RXN
SATARBIAS
SATARBIAS*
IGNNE*
DPRSTP*
INTVRMEN
A20GATE
SATA2RXN
SATA2RXP
THRMTRIP*
DPSLP*
INIT*
HDA_RST*
HDA_SDOUT
HDA_DOCK_EN*/GPIO33
SATA2TXN
SATA2TXP
FERR*
NMI
HDA_SDIN3
INTR
SATA_CLKP
SATA_CLKN
DA2
DD6
STPCLK*
TP8
DA0
DA1
HDA_DOCK_RST*/GPIO34
INTRUDER*
LAN_TXD0
LAN100_SLP
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
DD7
LAN_TXD2
LAN_TXD1
GLAN_DOCK*/GPIO13
GLAN_COMPI
GLAN_COMPO
GLAN_CLK
LAN/GLAN
IHDA
CPU
RTC
LPC
(1 OF 6)
SATA
IDE
OUT
IN
IN
IN
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
INT PU
INT PU
INT PU
INT PD
HDA
24.000MHZ CLOCK W/INTERNAL WEAK PD HDA_BIT_CLK
HDA_RST#
HDA_SDIN[0-2]
HDA_SDOUT
ACZ_SYNC
INTEGRATED PDs
INTEGRATED PD
INTEGRATED PD
INT PDINT PU
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PU
INT PU
INT PU
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S
U2300
AF13
AG26
AG29
AA4
AA1
AB3
Y6
Y5
V1
U2
T4
V6
V5
U1
V2
U6
V3
T1
V4
T5
AB2
T6
T3
R2
Y2
W5
W4
W3
AF26
AE26
AD24
E5
F5
G8
F6
C4
B24
D25
C25
AH21
AJ16
AE10
AG14
AE14
AJ17
AH17
AH15
AD13
AE13
AJ15
Y3
AF27
AE24
AC20
AD22
AF25
Y1
AD21
D22
C21
B21
C22
D21
E20
C20
G9
E6
AD23
AH14
AF23
AG25
AF24
AF6
AF5
AH5
AH6
AG3
AG4
AJ4
AJ3
AF2
AF1
AE4
AE3
AB7
AC6
AF10
AG2
AG1
AG28
AA24
AE27
AA23
OMIT
BGA
ICH8M27C8
27C8
27D5
27C5
6D2 44C8 46C6
6C2 44C8 46C4
6C2 44C8 46C4
6D2 44C8 46C6
6C2 44C8 46B6
9C8 70C3
R23041
2402
MF-LF1/16W
5%2.2K
NO STUFF
R23021
2402
1%24.9
MF-LF1/16W
R23011
2
1%332K
MF-LF402
1/16W
40C4 73D3
40D4 73D3
40D4 73D3
40D4 73D3
8D4
8D4
8D4
8D4
8D4
8D4
8D4
8D4
29C3 75B3
29C3 75B3
40D2
40D2
9B2 15B6 59C7 70B3
9B2 70B3
9C8 70C3
9B2 12B1 70C3
39C3 73D3
39B5 73D3
39B3 73D3
39B5 73D3
39B5 73D3
39C3 73D3
39C5 73D3
39C5 73D3
39C5 73D3
39C5 73D3
39C5 73D3
39C5 73D3
39C5 73D3
39C5 73D3
39C3 73D3
39C3 73D3
39C3 73D3
39C3 73D3
39C3 73D3
39C3 73D3
39C3 73D3
39C3 73D3
39B5 73D3
39B5 73D3
39B3 73D3
9B8 70B3
9B8 70C3
9B8 70B3
9C8 70B3
9D6 46B2 70B3
9B8 70C3
R23061
2
10K
MF-LF402
5%1/16W
9C6 15A6 45B3 70B3
R23081 2
PLACEMENT_NOTE=Place R2308 within 50mm of U23001%
MF-LF1/16W
24.9
402
8A6 73C3
R23001
2
1/16W1%
332K
402MF-LF
R23031
2
8.2K5%
1/16WMF-LF402
8A6 73C3
8A6 73C3
8A6 73B3
8A6 73C3
R23101
2402
MF-LF1/16W
5%8.2K
R23051
2
1%1/16WMF-LF402
54.9R23091
2
1%1/16WMF-LF402
54.9
PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)
R2313 1 2
402
33MF-LF1/16W5%R2314 1 2
5% 1/16W MF-LF
33402
R2315 1 21/16W
33MF-LF5% 402
R2316 1 2
5% 1/16W MF-LF 402
33
R23111
2
1/16W
402MF-LF
10K5%
39B3 73D3
39B5 73D3
01
22 76
051-7455
SYNC_MASTER=T9_MLB SYNC_DATE=10/30/2006
SB Enet, Disk, FSB, LPC
PP3V3_G3_SB_RTC
SB_RTC_X1
SB_RTC_X2
HDA_DOCK_EN_L
LAN_ENERGY_DET
=PP3V3_S0_SB_GPIO
PP1V5_S0_SB_VCC1_5_B
GLAN_COMP
SB_INTVRMEN
SB_LAN100_SLP
SB_SM_INTRUDER_L
SB_RTC_RST_L
TP_LAN_R2D<2>
LPC_AD<2>
LPC_AD<0>
LPC_AD<1>
LPC_AD<3>
LPC_FRAME_L
EXTGPU_PWR_EN
PM_THRMTRIP_LCPU_THERMTRIP_R
CPU_A20M_L
CPU_DPSLP_L
CPU_DPRSTP_L
CPU_PWRGD
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_STPCLK_L
IDE_PDD<0>
IDE_PDD<2>
IDE_PDD<1>
IDE_PDD<3>
IDE_PDD<4>
IDE_PDD<5>
IDE_PDD<7>
IDE_PDD<6>
IDE_PDD<8>
IDE_PDD<10>
IDE_PDD<9>
IDE_PDD<12>
IDE_PDD<11>
IDE_PDD<13>
IDE_PDD<15>
IDE_PDD<14>
IDE_PDA<0>
IDE_PDA<1>
IDE_PDA<2>
IDE_PDCS3_L
IDE_PDCS1_L
IDE_PDIOW_L
IDE_PDIOR_L
IDE_PDDACK_L
IDE_IRQ14
IDE_PDIORDY
IDE_PDDREQ
=PP1V05_S0_SB_CPU_IO
=PP3V3_S0_SB_GPIO
CPU_FERR_L
SB_A20GATE
TP_LPC_DRQ0_L
SB_RCIN_L
TP_SB_TP8
TP_LAN_D2R<2>
SATA_A_D2R_P
TP_SB_SATALED_L
SATA_A_R2D_C_P
SATA_A_R2D_C_N
SATA_B_D2R_P
SATA_B_D2R_N
TP_HDA_DOCK_RST_L
TP_LAN_R2D<0>
TP_LAN_RSTSYNC
TP_LAN_D2R<0>
TP_LAN_R2D<1>
SATA_B_R2D_C_N
SATA_B_R2D_C_P
SATA_C_D2R_P
SATA_C_D2R_N
SATA_C_R2D_C_N
SATA_C_R2D_C_P
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
SATA_RBIAS_P
SATA_RBIAS_N
HDA_BIT_CLK_R
HDA_SYNC_R
HDA_RST_L_R
HDA_SDOUT_R
HDA_SYNC
HDA_BIT_CLK
HDA_RST_L
HDA_SDOUT
SATA_A_D2R_N
TP_HDA_SDIN1
TP_ENET_GLAN_CLK
TP_LAN_D2R<1>
HDA_SDIN0
TP_HDA_SDIN3
TP_HDA_SDIN2
24D8
26C6
24D8
27D4
24B3
26A4
26C4
24B3
26A5
22D2
25D6
25C3
22D7
25D6
7D4
23C2
74B3
7D7
7D4
73C3
73C3
73C3
73B3
8A6
8A6
8A6
SPI_CS1*
PETN1
PERP1
OC4*/GPIO43
OC5*/GPIO29
OC6*/GPIO30
OC7*/GPIO31
OC8*
OC9*
SPI_MOSI
OC0*
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
PERN5
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
DMI_CLKN
DMI_CLKP
PETP1
USBP9N
USBP9P
PERN2
USBP7N
USBP7P
USBP8N
USBP8P
PETN2
USBP6N
USBP6P
PERP3
USBP4N
USBP4P
USBP5N
USBP5P
PETN3
PETP3
USBP3N
USBP3P
PERN4
PERP4
USBP1N
USBP1P
USBP2N
USBP2P
PETN4
PETP4
USBP0N
USBP0P
PERP5
SPI_MISO
USBRBIAS
USBRBIAS*
PETP5
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
SPI_CLK
SPI_CS0*
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI_IRCOMP
DMI_ZCOMP
PERN1
PERP2
PETP2
PERN3
PETN5
PCI_EXPRESS
DIRECT MEDIA INTERFACE
SPI
USB
(2 OF 6)
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
OUT
OUT
IN
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
OUT
OUT
IN
IN
OUT
OUT
BI
BI
BI
BI
AD4
AD5
AD9
PIRQF*/GPIO3
PIRQE*/GPIO2
AD13
PME*
PCIRST*
GNT2*/GPIO53
C/BE2*
PIRQG*/GPIO4
SERR*
PIRQA*
AD1
REQ1*/GPIO50
C/BE3*
AD11
C/BE1*
AD25
AD26
AD0
AD2
DEVSEL*
AD18
AD21
PAR
GNT0*
AD7
GNT1*/GPIO51
C/BE0*
STOP*
AD20
AD16
GNT3*/GPIO55
TRDY*
IRDY*
AD22
PIRQC*
REQ2*/GPIO52
AD19
PCICLK
PLOCK*
AD15
PIRQB*
PIRQH*/GPIO5
PLTRST*
AD3
AD6
AD8
FRAME*
AD14
AD12
AD10
REQ3*/GPIO54
PIRQD*
AD17
PERR*
REQ0*
AD31
AD27
AD28
AD30
AD29
AD24
AD23
(3 OF 6)
INTERRUPT I/F
PCI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
BI
BI
BI
BI
BI
BI
OUT
BI
BI
BI
BI
BI
BI
BI
OUT
IN
BI
BI
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
PCIe Mini Card
rises, or PCIe ports 5 & 6 will be disabled.
NOTE: GNT[0-3]# have internal 20K pull-ups
Provide a pull-down on this GPIO if not used.
R2415 pull-down on GNT0#
Nineveh-GLCI
Yukon-PCIE
enabled only when PCIRST# = 0 and PWROK = 1
If used, ensure GNT2# is not low when PWROK
INT PU
INT PU
FireWire INT*
SPI
I/F
LPC
NOTE:
0
GNT0#
1
INT PU
INT PU
INT PU
SB BOOT BIOS SELECT
GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
high for x2)
pull HDA_SYNC
(x2-capable,
Ethernet
(AirPort)
FireWire
ExpressCard
Spares
INT PD
INT PD
INT PD
EHCI1
INT PU
INT PU
INT PU
INT PU
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PDEHCI0
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
INT PD
External C
Camera
AirPort (PCIe Mini-Card)
ExpressCard
External B
Geyser Trackpad/Keyboard
External A
External D / WWAN
Bluetooth
IR
NOTE: USBP[0-9]P/N have internal 15K pull-downs.
selects SPI ROM by default.
R24081
2
5%10K
402
1/16WMF-LF
R24071
2
1/16WMF-LF402
10K5%
R24001
2
10K
402
5%1/16WMF-LF
R24091
2
1/16W
402MF-LF
5%10K
R24011
2
MF-LF402
5%10K
1/16W
R24021
2402
5%1/16WMF-LF
10KR24041
2402
1/16WMF-LF
10K5%
R24031
2
10K
MF-LF402
1/16W5%
U2300 V27
V26
U29
U28
Y27
Y26
W29
W28
AB26
AB25
AA29
AA28
AD27
AD26
AC29
AC28
T26
T25
Y24
Y23
AJ19
AG16
AG15
AE15
AF15
AG17
AD12
AJ18
AD14
AH18
P27
M27
K27
H27
F27
D27
P26
M26
K26
H26
F26
D26
N29
L29
J29
G29
E29
C29
N28
L28
J28
G28
E28
C28
C23
B23
E22
F21
D23
G3
G2
H5
H4
H2
H1
J3
J2
K5
K4
K2
K1
L3
L2
M5
M4
M2
M1
N3
N2
F3
F2
BGA
ICH8M
OMIT
15B3 71D3
15B3 71D3
15C3 71D3
15B3 71D3
15B3 71D3
15B3 71D3
15C3 71D3
15B3 71D3
15B3 71D3
15B3 71D3
15B3 71D3
15B3 71D3
15B3 71D3
15B3 71D3
15B3 71D3
15B3 71D3
29C3 75B3
29C3 75B3
R24131 2
1% 402MF-LF1/16W
24.9
8C1 73B3
8C1 73B3
8C1 73B3
8C1 73B3
8C1
8C1
8C1 73B3
8C1 73B3
8C1 8C2 73B3
8C1 8C2 73B3
8C1 73B3
8C1 73B3
8B1 8B2 73B3
8C1 8C2 73B3
8B1 73B3
8B1 73B3
8B1 73B3
8B1 73B3
8B1 73B3
8B1 73B3
R24141 222.6
MF-LF402
1%1/16W
33B6
33B6
33B6
33B6
34C8
34C8
34C8
34C8
52C7 73A3
52C7 73A3
52C3 73A3
52C3 73A3
U2300D20
E19
A12
E16
A14
G16
A15
B6
C11
A9
D11
B12
D19
C12
D10
C7
F13
E11
E13
E12
D8
A6
E8
A20
D6
A3
D17
A21
A19
C19
A18
B16 C17
E15
F16
E17
D16
A17
D7
C18
F18
C10
C8
D9
B10
G6
A7
F9
B5
C5
A10
F8
G11
F12
B3
B7
AG24
G7
A4
E18
B19
A11
F10
C16
C9
OMIT
BGA
ICH8M37C5 74D3
37C5 74D3
37C5 74D3
37C5 74D3
37C5 74D3
37C5 74D3
37C5 74D3
37C5 74D3
37C5 74D3
37C5 74D3
37C5 74D3
37C5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B6 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
23A4 74C3
23A4 74C3
23A4 74C3
23A4 37A5 74C3
23A4 74D3
23A4 37A5 74D3
23A4 74D3
37B5 74D3
37B5 74D3
37B5 74D3
37B5 74D3
23A4 37A5 74D3
37B5 74D3
37A6
23A4 37A5 74D3
23A4 37A5 74D3
23A4 74D3
23A4 37A5 74D3
23A4 37A5 74D3
23A4 37A5 74D3
23A4 37A5 74D3
27D4 67C6
29A5 29B3 75B3
23A4 74C3
R24051
2
5%
402MF-LF1/16W
10K
R24061
2
1/16W5%
MF-LF
100K
402
NOSTUFF
R24151
2
MF-LF
1K
1/16W5%
402
R2423 1 2 8.2KR2424 1 2 8.2KR2425 1 2 8.2KR2426 1 2 8.2KR2427 1 2 8.2KR2428 1 2 8.2KR2430 1 2 8.2KR2429 1 2 8.2K
R2432 1 2 8.2KR2431 1 2 8.2KR2433 1 2 8.2K
R2437 1 2 8.2K
R2439 1 2 8.2K
R2438 1 2 8.2K
R2436 1 2 8.2K
R2440 1 2 8.2K23A4 74C3
R2441 1 2 8.2K
8C1
8B1
23A4 39C8
68A4 68B8
37A5 74D3
39A8 73D3
6C2 46B6
R2442 1 2 8.2K
39B8
33B6
SYNC_DATE=10/30/2006
051-74557623
01
SYNC_MASTER=T9_MLB
SB PCI, PCIe, DMI, USB
SB_GPIO42
=PP3V3_S5_SB_USB
EXTGPU_LVDS_EN
MAKE_BASE=TRUEPCI_FW_GNT_L
TP_SB_GPIO55
TP_SB_GPIO51
ODD_RST_5VTOL_L
SB_GPIO30
USB_EXTA_OC_L
USB_EXTB_OC_L
EXCARD_OC_L
SB_GPIO40
USB_EXTD_OC_L
USB_EXTC_OC_L
ODD_PWR_EN_L
INT_PIRQF_L
INT_PIRQE_L
PCI_FRAME_L
PCI_TRDY_L
PCI_STOP_L
PCI_LOCK_L
PCI_PERR_L
PCI_RST_L
PCI_PAR
PCI_FW_REQ_L
TP_SB_GPIO53
PCI_C_BE_L<0>
PCI_C_BE_L<2>
PCIE_ENET_R2D_C_P
PCIE_ENET_D2R_P
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
TP_SPI_CE_R_L<1>
PCI_DEVSEL_L
PM_LATRIGGER_L
TP_PCIE_A_R2D_C_P
PCI_AD<14>
PCI_AD<4>
PCI_AD<5>
PCI_AD<9>
PCI_AD<13>
INT_PIRQA_L
PCI_AD<1>
PCI_AD<11>
PCI_AD<25>
PCI_AD<26>
PCI_AD<0>
PCI_AD<2>
PCI_AD<18>
PCI_AD<21>
PCI_AD<7>
PCI_AD<20>
PCI_AD<16>
PCI_AD<22>
INT_PIRQC_L
PCI_AD<19>
PCI_AD<15>
INT_PIRQB_L
PCI_AD<3>
PCI_AD<6>
PCI_AD<8>
PCI_AD<12>
PCI_AD<10>
INT_PIRQD_L
PCI_AD<17>
PCI_AD<31>
PCI_AD<27>
PCI_AD<28>
PCI_AD<30>
PCI_AD<29>
PCI_AD<24>
PCI_AD<23>
BOOT_LPC_SPI_LPCI_REQ1_L
PCI_C_BE_L<3>
PCI_SERR_L
PCI_REQ1_L
PCI_TRDY_L
INT_PIRQE_L
INT_PIRQD_L
INT_PIRQB_L
INT_PIRQA_L
PCI_REQ2_L
PCI_STOP_L
PCI_IRDY_L
PCI_FRAME_L
PCI_FW_REQ_L
PCI_LOCK_L
INT_PIRQF_L
INT_PIRQC_L
ODD_PWR_EN_L
PCI_SERR_L
PCI_DEVSEL_L
PCI_PERR_L
=PP3V3_S0_SB_PCI
PP1V5_S0_SB_VCC1_5_B
USB_RBIAS
DMI_IRCOMP_R
TP_PCIE_A_R2D_C_N
TP_PCIE_A_D2R_P
SPI_SI_R
PCIE_MINI_D2R_N
TP_PCIE_B_D2R_N
TP_PCIE_B_R2D_C_N
TP_PCIE_EXCARD_D2R_P
TP_PCIE_EXCARD_R2D_C_N
TP_PCIE_EXCARD_R2D_C_P
TP_PCIE_FW_D2R_N
TP_PCIE_FW_D2R_P
TP_PCIE_FW_R2D_C_N
TP_PCIE_FW_R2D_C_P
PCIE_MINI_D2R_P
PCIE_ENET_D2R_N
SPI_SCLK_R
SPI_CE_R_L<0>
TP_PCIE_A_D2R_N
TP_PCIE_B_D2R_P
TP_PCIE_B_R2D_C_P
TP_PCIE_EXCARD_D2R_N
USB_EXTC_P
USB_EXCARD_P
USB_EXTC_N
USB_EXCARD_N
USB_EXTB_P
USB_EXTB_N
USB_BT_P
USB_TPAD_P
USB_BT_N
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_CAMERA_N
USB_CAMERA_P
USB_EXTD_P
USB_EXTD_N
USB_MINI_P
USB_MINI_N
USB_EXTA_P
USB_EXTA_N
SB_CLK100M_DMI_P
SB_CLK100M_DMI_N
DMI_S2N_P<3>
DMI_S2N_N<3>
DMI_N2S_P<3>
DMI_N2S_N<3>
DMI_S2N_P<2>
DMI_S2N_N<2>
DMI_N2S_P<2>
DMI_N2S_N<2>
DMI_S2N_P<1>
DMI_S2N_N<1>
DMI_N2S_P<1>
DMI_N2S_N<1>
DMI_S2N_P<0>
DMI_S2N_N<0>
DMI_N2S_P<0>
DMI_N2S_N<0>
PCI_IRDY_L
PCIE_ENET_R2D_C_N
SPI_SO
PCI_C_BE_L<1>
PLT_RST_L
PCI_REQ2_L
PCI_CLK33M_SB
TP_PCI_PME_L
DVI_HOTPLUG_DET
26C6
74D3
74C3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
26A4
74D3
37A5
74C3
37A5
74C3
74C3
74D3
37A5
37A5
37A5
37A5
74D3
74C3
74C3
39C8
37A5
37A5
37A5
25D6
7D1
8D4
23B6
23A6
23A6
23A8
23A8
23A8
23B6
23A6
23A6
23A6
23B6
23A6
23A6
23A8
23A6
23A6
23A6
23A6
7C4
22D7
73B3
8D4
8D4
8D4
8C4
8C4
8C4
8C4
8C4
8C4
8C4
8C4
8D4
8D4
8C4
8C4
OUT
OUT
BI
IN
BI
IN
IN
SMBALERT*/GPIO11
STP_PCI*/GPIO15
BMBUSY*/GPIO0
SYS_RESET*
SUS_STAT*/LPCPD*
QRT_STATE0/GPIO27
THRM*
SMLINK0
GPIO12
SPKR
SDATAOUT1/GPIO48
QRT_STATE1/GPIO28
SLP_S5*
GPIO20
GPIO8
WAKE*
CL_CLK1
BATLOW*
PWROK
SLOAD/GPIO38
SATA2GP/GPIO36
SERIRQ
RI*
CL_DATA1
SLP_S4*
EC_ME_ALERT/GPIO14
TACH0/GPIO17
CLK14
SCLOCK/GPIO22
SATA3GP/GPIO37
SATACLKREQ*/GPIO35
STP_CPU*/GPIO25
WOL_EN/GPIO9
LINKALERT*
SLP_S3*
RSMRST*
TACH3/GPIO7
CLKRUN*/GPIO32
GPIO18
LAN_RST*
CL_VREF1
S4_STATE*/GPIO26
TACH1/GPIO1
TACH2/GPIO6
SATA1GP/GPIO19
SDATAOUT0/GPIO39
SATA0GP/GPIO21
MCH_SYNC*
DPRSLPVR/GPIO16
VRMPWRGD
TP3
TP7
CL_RST*
ME_EC_ALERT/GPIO10
SLP_M*
MEM_LED/GPIO24
PWRBTN*
SUSCLK
CL_VREF0
CK_PWRGD
CLPWROK
CL_DATA0
CL_CLK0
CLK48
SMBCLK
SMBDATA
SMLINK1
MISC
SYS GPIO
SMB
CLOCKS
POWER MGT
CONTROLLER LINKGPIO
SATA
GPIO
(4 OF 6)
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
BI
BI
OUT
IN
IN
IN
IN
IN
OUT
OUT
IN
BI
BI
BI
BI
OUT
BI
BI
BI
BI
IN
IN
OUT
OUT
OUT
IN
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
LAYOUT NOTE:
PLACE R2511-16 WHERE PHYSICALLY ACCESSIBLE
See note below
have been up for at least 1ms.
PM_LAN_ENABLE must remain deasseted
until VccCL3_3, VccLAN3_3 and VccLAN1_05
INT PU
NOTE: ICH CLPWROK input must be PWRGD signal for
PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,
PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.
If ME/AMT is not used, short CLPWROK to PWROK.
INT PU
INT PU
INT PU
INT PD
INT PD
INT PU
for XOR chain testing.
Test access required
INT PU
NOTE: DPRSLPVR HAS INT 20K PD ENABLED
INT PU
AT BOOT/RESET FOR STRAPPING FUNCTION
28C4 29C2
28C4 29C2
6C2 37A5 44C5 46B6
33C5 34B8
6C2 44C8 46B4
44B8
44C5
R25141
2
MF-LF1/16W5%100K
402
R25151
2
1/16W
10K5%
MF-LF402
R25161
2
1/16W5%
ARB_ONLY
MF-LF
0
402
R25111
2
MF-LF
10K
1/16W5%
402
R25121
2
05%1/16WMF-LF402
NOSTUFF
R25021
2
1/16W5%
10K
MF-LF402
R25041
2402
10K5%
MF-LF1/16W
R25001
2
1K5%1/16WMF-LF402
R25071
2402
8.2K5%
1/16WMF-LF
R25061
2
10K
402
5%1/16WMF-LF
R25051
2402
1/16W
8.2K5%
MF-LF
U2300
AE21
AG12
E1
F23
AE18
F22
AF19
AJ23
D24
AH23
AG9
G5
AH11
E3
AJ14
AF22
AC19
AH12
AE11
AE16
AH20
AG21
AJ13 AJ24
AJ27
C2
AE23
AH25
AD16
AF17
AG27
AH27
AJ12
AJ10
AF11
AG11
AG13
AG10
AJ11
AD10
AF12
AF9
AJ25
AG23
AF21
AD18AG22
AJ26
AD19
AC17
AE19
AD9
AG18
AE20
F4 D3
AD15
AG8
AJ8
AJ9
AH9
AC13
AJ21
AJ22
AJ20
AE17
AG19
OMIT
BGA
ICH8M
29A5 29D6 75B3
29A5 29D6 75B3
45A8
33C7 35C7 44C5 45A6 58B7 62B8
R25101
2402
1/16W5%1K
NO_REBOOT_MODE
MF-LF
44C5 45C3
15A6 59D8 70B3
27A6
24A5 44B8
44C8
44C8
47D8 73A3
47D8 73A3
6C2 44C5 46B4
27C5 44B8
15B6
8B4
24A5 37A5
15A3
33B7 44C5 65A6 65C4
28A4
8B4
15A3 74A3
74A3
15A3 74A3
74A3
R25261
2402
3.24K1%1/16WMF-LF
R25271
2402
4531%1/16WMF-LF
C2500 1
2
402
16V10%
0.1uF
X5R
R25291
2402
1/16W1%
MF-LF
453
R25281
2402
3.24K1%1/16WMF-LF
C2501 1
2
402
16V10%
X5R
0.1uF
15A3 74A3
24A7
R25231
2
NOSTUFF
100K5%
1/16W
402MF-LF
47A8 73A3
47A8 73A3
74A3
24A5
R25361 2
1/16W
10K
MF-LF
1%
402 R25441 2
5%
MF-LF1/16W
8.2K
402R25451 2
MF-LF
10K
1/16W1%
402
R25311 2
10K
1/16WMF-LF
1%
402
R25301 2
10K
1/16WMF-LF
1%
402
R25251
2
10K
MF-LF1/16W5%
402
6C2 24A7 46B4
24A5
8B4 24B5
8B4
R25342
1
MF-LF1/16W5%10K
402
R25521
2402
MF-LF1/16W
10K5%
R25501
2
10K
MF-LF
5%1/16W
402
R25531
2402MF-LF1/16W5%8.2K
R25511
2
1/16W
8.2K5%
MF-LF402
44D8
R25981 2
1%
MF-LF1/16W
10K
402R25461 2
1%
MF-LF1/16W
10K
402
R25322
1
10K
MF-LF402
5%1/16W
R25332
1402
1/16W5%
MF-LF
10K
R25352
1
1/16WMF-LF
10K
402
5%
69A6
R25472
1
1/16W5%
MF-LF
10K
402
R25241
2
100K
402
5%1/16WMF-LF
R25971 2
10K
1/16WMF-LF
1%
402R25961 2
10K
1/16WMF-LF
1%
402
01
24 76
051-7455
SYNC_MASTER=T9_MLB SYNC_DATE=10/30/2006
SB Pwr Mgt, GPIO, Clink
FWH_MFG_MODE
ARB_DETECT_L
LINDACARD_GPIO
=PP3V3_S5_SB_GPIO
PM_BATLOW_L
ARB_DETECT_L
SB_CLINK_VREF1
PM_CLKRUN_L
PM_STPCPU_L
PCIE_WAKE_L
VR_PWRGD_CLKEN
SMC_WAKE_SCI_L
SB_SDATAOUT<0>
TP_SB_TP3
SB_GPIO36
SB_CRT_TVOUT_MUX_L
RSVD_EXTGPU_LVDS_EN
PM_STPPCI_L
=PP3V3_S5_SB
PM_LAN_ENABLE
PM_RSMRST_L
=SB_CLINK_MPWROK
CLINK_NB_CLK
PM_RI_L
CLINK_NB_RESET_L
=PP3V3_S5_SB_CLINK1
SB_CLK48M_USBCTLR
SUS_CLK_SB
CLINK_WLAN_RESET_L
PM_PWRBTN_L
SMC_RUNTIME_SCI_L
SMB_ME_CLK
SMB_CLK
PCI_PME_FW_L
LAN_PHYPC
EXTGPU_RST_L
SB_GPIO18
TP_SB_GPIO20
SB_SDATAOUT<1>
PM_DPRSLPVR
CLK_PWRGD
TP_SB_GPIO6
PM_RI_L
SB_GPIO10_CL1
LAN_PHYPC
SB_GPIO14_CL2
=PP3V3_S0MWOL_SB_CLINK0
SATA_B_PWR_EN_L
FWH_MFG_MODE
TP_SB_TP7
SMB_ME_DATA
PM_SYSRST_L
TP_PM_SLP_S4_L
PM_SLP_S5_L
PM_S4_STATE_L
PM_BATLOW_L
CLINK_NB_DATA
PM_BMBUSY_L
LINDACARD_GPIO
SB_SATA_CLKREQ_L
PM_SUS_STAT_L
PM_THRM_L
SB_SCLOCK
SB_CLK14P3M_TIMER
PM_SLP_S3_L
WOL_EN
SB_GPIO14_CL2
SB_GPIO10_CL1
SB_CLINK_VREF0
CLINK_WLAN_DATA
SATA_B_DET_L
NB_SB_SYNC_L
SB_SPKR
CLINK_WLAN_CLK
TP_PM_SLP_M_L
INT_SERIRQ
SB_SLOAD
PM_SB_PWROK
SMB_DATA
=PP3V3_S0_SB_GPIO
PCI_PME_FW_L
SATA_B_PWR_EN_L
TP_SB_GPIO6
=PP3V3_S0_SB_GPIO
EXTGPU_RST_L
=PP3V3_S5_SB
35C7
24B3
24D8
35C7
46B4
26D8
22D7
22D7
26D8
24D5
44B8
24A8
22D2
37A5
22D2
24C5
24A3
24C5
24B3
6C2
7D1
24C3
74A3
7D1
7C1
24B5
24D5
24B3
24C5
24B3
7C4
24A5
24A7
35B7
24A5
24A5
74A3
7D4
24C5
24C5
24C5
7D4
8B4
7D1
VSS
VSS_NCTF
VSS
(5 OF 6)
VCC1_5_B
V5REF_SUS
VCCDMIPLL
VCC_DMI
VCC3_3
VCC1_05
V5REF
VCCCL1_5
VCCGLANPLL
VCC3_3
VCC1_5_A
VCC3_3
VCCHDA
VCCSUS1_5
VCCSUS3_3
V_CPU_IO
VCC3_3
VCCSUSHDA
VCC1_5_A
VCC3_3
VCCSATAPLL
VCCGLAN3_3
VCCSUS3_3
VCCLAN3_3
VCCCL1_05
VCCSUS1_05
VCCSUS1_5
VCCSUS3_3
VCCA3GP
VCCGLAN1_5
VCCCL3_3
VCCLAN1_05
VCC1_5_A24
VCC1_5_A
VCCRTC
VCC1_5_A
VCCUSBPLL
VCC1_5_A
VCC1_5_A
VCC1_5_A
GLAN POWER
USB CORE
ATX
ARX
(6 OF 6)
VCCPSUS
IDE
CORE
VCCP
CORE
PCI
VCCPUSB
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
6 uA S0-G3
1 mA
1 mA S0-S5
657 mA
Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.
Current figures provided assume 1.5V.
depending on VIO of HD Audio interface.
VccHDA and VccSusHDA can be 1.5V or 3.3V
NOTE:
1130 mA
23 mA
50 mA
1 mA
(VCC3_3 total)
442 mA
117 mA S0,
11 mA S0,
44 mA S3-S5
1 mA S3-S5
(VCCSUS3_3 total)
32 mA
1080 mA
47 mA
(VCC1_5_A total)
63 mA M1 & WOL
19 mA S0,
10 mA
23 mA
80 mA
1 mA51 mA M1 & WOL
19 mA S0,
C2600 1
2
1uF
6.3VCERM
10%
402
C26011
2
402CERM10V20%0.1uF
U2300A23
A5
AC26
L13
L15
L26
L27
L4
L5
M12
M13
M14
M15AC27
M16
M17
M23
M28
M29
M3
N1
N11
N12
N13
AD17
N14
N15
N16
N17
N18
N26
N27
N4
N5
N6
AD20
P12
P13
P14
P15
P16
P17
P23
P28
P29
R11
AD28
R12
R13
R14
R15
R16
R17
R18
R28
R4
T12
AD29
T13
T14
T15
T16
T17
T2
U12
U13
U14
U15
AD3
U16
U17
U23
U26
U27
U3
U5
V13
V15
V28
AD4
V29
W2
W26
W27
Y28
Y29
Y4
AB4
AB23
AB5
AD6
AB6
AD5
U4
W24
AE1
AA2
AE12
AE2
AE22
AD1
AE25
AE5
AE6
AE9
AF14
AF16
AA7
AF18
AF3
AF4
AG5
AG6
AH10
AH13
AH16
AH19
AH2
A25
AF28
AH22
AH24
AH26
AH3
AH4
AH8
AJ5
B11
B14
AB1
B17
B2
B20
B22
B8
C24
C26
C27
C6
D12
AB24
D15
D18
D2
D4
E21
E24
E4
E9
F15
E23
AC11
F28
F29
F7
G1
E2
G10
G13
G19
G23
G25
AC14
G26
G27
H25
H28
H29
H3
H6
J1
J25
J26
AC25
J27
J4
J5
K23
K28
K29
K3
K6
K7
L1
A1
A2
B1
B29
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
ICH8MBGA
OMIT
U2300
A16
T7
G4
AC23
AC24
A13
B13
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
C13
U18
V17
V14
V11
U11
V18
V16
V12
C14
D14
E14
F14
G14
L11
L12
AE7
AF7
AC10
AC9
AA5
AA6
G12
G17
H7
AC7
AD7
F1
AG7
L6
L7
M6
M7
W23
AH7
AJ7
AC1
AC2
AC3
AC4
AC5
AA25
AA26
E27
F24
F25
G24
H23
H24
J23
J24
K24
K25
AA27
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
AB27
R24
R25
R26
R27
T23
T24
T27
T28
T29
U24
AB28
W25
V24
U25
Y25
V25
V23
AB29
D28
D29
E25
E26
AF29
AD2
W6
W7
Y7
A8
B15
B18
B4
B9
C15
D13
AC8
D5
E10
E7
F11
AD8
AE8
AF8
AA3
U7
V7
W1
AE28
AE29
G22
A22
F20
G21
R29
B27
A27
B28
B26
A26
B25
A24
AC12
F17
G18
F19
G20
AD25
AJ6
J6
AF20
AC16
J7
C3
AC18
P1
P2
P3
P4
P5
R1
R3
R5
R6
AC21
AC22
AG20
AH28
P6
P7
C1
N7
AD11
D1
BGA
ICH8M
OMIT
SYNC_MASTER=T9_MLB
051-74557625
01
SYNC_DATE=10/30/2006
SB Power & Ground
=PP1V05_S0_SB_CPU_IO
=PP1V25_S0_SB_DMI
PP1V5_S0_SB_VCCDMIPLL
=PP3V3_S0_SB_VCC3_3_DMI
=PP3V3_S0_SB_VCC3_3_SATA
=PP3V3_S0_SB_VCC3_3_VCCPCORE
PP5V_S0_SB_V5REF
VCCCL1_5V
=PPVCORE_S0_SB
=PP3V3_S0_SB_VCC3_3_IDE
PP1V5_S0_SB_VCC1_5_B
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S0MWOL_SB_VCCLAN3_3
=PP1V5_S0_SB_VCC1_5_A
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP3V3_S0MWOL_SB_VCCCL3_3
=PP1V5_S0_SB_VCCGLAN1_5
PP5V_S5_SB_V5REF_SUS
PP1V5_S0_SB_VCCGLANPLL
=PP3V3R1V5_S0_SB_VCCHDA
TP_VCCSUS1_5_INTERNAL_REG1
=PP3V3_S5_SB_3V3_VCCSUSHDA
PP1V5_S0_SB_VCCSATAPLL
=PP3V3_S0_SB_VCCGLAN3_3
TP_VCCCL1_05_INTERNAL_REG
TP_VCCSUS1_05_INTERNAL_REG1
TP_VCCSUS1_5_INTERNAL_REG2
TP_VCCSUS1_05_INTERNAL_REG2
TP_VCCLAN1_05_INTERNAL_REG2
TP_VCCLAN1_05_INTERNAL_REG1
PP3V3_G3_SB_RTC
=PP1V5_S0_SB_VCCUSBPLL
=PP3V3_S0_SB_VCC3_3_PCI
26C6
26C4
26C6
26A4
26D2
27D4
22D2
26A6
26A8
26B8
26A6
26D2
26B4
23C2
26D5
26C6
26B6
26D2
26D3
26C2
26C2
26B2
26C4
26B2
26A5
26B6
26B4
7D7
7C7
26A6
7D4
7D4
7D4
26D7
7D7
7D4
22D7
7B7
7B7
7D1
7D1
7C4
7B7
7B6
7C4
26A4
26C7
26B7
7C4
7D1
26D5
7D4
22D7
7B7
7D4
NC
NC
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
ICH VCC1_5_A/ATX BYPASS
PLACE < 2.54MM OF SB ON SECONDARY ORPLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
ON SECONDARY SIDE OR 3.56MM ON PRIMARYDISTRIBUTED BETWEEN AA25..V23
M70 DOES NOT USE GIGABIT IN SB, SO NO NEED FOR PLL FILTERING
L2703 NEED CHANGE TO 1UH PART
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AC1..AC5
DISTRIBUTE IN PCI SECTION OF SB
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARYOR 3.56MM ON PRIMARY NEAR PIN AC12
(ICH CPU I/O 1.05V PWR)
PLACE NEAR PINS AC23,AC24 OF SB
ICH IDE/VCC3_3 BYPASS
ON SECONDARY SIDE OR 3.56MM ON PRIMARY
PLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR3.56MM ON PRIMARY NEAR PIN AH11
3.56MM ON PRIMARY NEAR PIN AJ6
L2702 MAY HAVE CHANGE TO 1.0UH PART
PLACEMENT NOTE:PLACE < 2.54MM OF SB ON SECONDARYOR 3.56MM ON PRIMARY NEAR PIN AD2
PLACEMENT NOTE:PLACE CAPS < 2.54MM OF SB ONSECONDARY SIDE OR 3.56MM ON PRIMARY
(ICH IO BUFFER 3.3V PWR)ICH VCC3_3 BYPASS
PLACE CAP UNDER SB NEAR PINS F19 AND G20
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
ICH VCCSUS3_3 BYPASS(ICH SUSPEND 3.3V PWR)
PLACE < 2.54MM OF SB ON SECONDARYOR 3.56MM ON PRIMARY NEAR PIN AD11
OR 3.56MM ON PRIMARY NEAR PIN AE29
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEHOLDER
AC18..AH28
(ICH SUSPEND 3.3V PWR)
PLACEMENT NOTE:
PLACE CAPS NEAR PINS
ICH VCC1_5A BYPASS
PLACEMENT NOTE:
ICH VCCDMIPLL BYPASS
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
P6..R6
ICH VCCSUS3_3 BYPASS
OR 3.56MM ON PRIMARY NEAR PIN AF29
PLACEMENT NOTE:
ICH VCC1_5_A/ARX BYPASS
PLACE C2715 NEAR PIN D1 OF SB
PLACE CAP NEAR PINS
PLACEMENT NOTE:
PLACE CAP < 2.54MM OF SB ON SECONDARY
PLACEMENT NOTE:
(ICH LOGIC&IO 1.5V PWR)
(ICH LOGIC&IO[ARX] 1.5V PWR)
3.56MM ON PRIMARY NEAR PINS F20,G21 PLACE < 2.54MM OF SB ON SECONDARY ORPLACEMENT NOTE:
PLACE < 2.54MM OF SB ON SECONDARY OR
ICH USB/VCCSUS3_3 BYPASS(ICH SUSPEND USB 3.3V PWR)
3.56MM ON PRIMARY NEAR PINS F1..M7
ICH VCC3_3/VCCHDA BYPASS(ICH INTEL HDA CORE 3.3V PWR)
ICH USB CORE/VCC1_5_A BYPASS(ICH USB CORE 1.5V PWR)
AC10..AD7 OF SBPLACE CAP NEAR PINS
PLACEMENT NOTE:
(ICH INTEL HDA CORE 3.3V/1.5V PWR)ICH VCCHDA BYPASS
(ICH IDE I/O 3.3V PWR)
(ICH IO BUFFER 3.3V PWR)
(ICH USB PLL 1.5V PWR)ICH VCCUSBPLL BYPASS
ICH VCC3_3 BYPASS
PLACE < 2.54MM OF SB ON SECONDARY
PLACE CAPS NEAR PIN AD25 OF SB
PLACE CAP NEAR PIN B27..A26
NEAR PINS A8 ... F11
(ICH LAN I/F BUFFER 3.3V PWR)ICH VCC_PAUX/VCCLAN3_3 BYPASS
ICH VCCRTC BYPASS(ICH RTC 3.3V PWR)
ICH V_CPU_IO BYPASS
PLACEMENT NOTE:FOR 270UF
(ICH DMI PLL 1.5V PWR)
(ICH LOGIC&IO[ATX] 1.5V PWR)
PLACE CAPS NEAR PIN C2..AH28
(ICH PCI I/O 3.3V PWR)ICH PCI/VCC3_3 BYPASS
3.56MM ON PRIMARY NEAR PINS AA3...Y7 PLACE < 2.54MM OF SB ON SECONDARY OR
PLACE CAPS < 2.54MM OF SB ON SECONDARY
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:PLACE C2709 NEAR PIN B27 OF SB
PLACEMENT NOTE:PLACE C2700 & C2705-07 < 2.54MM OF SB
OR 3.56MM ON PRIMARY NEAR PIN A24
ICH V5REF BYPASS(ICH REFERENCE FOR 5V TOLERANCE ON CORE WELL INPUT) ICH CORE/VCC1_05 BYPASS
(ICH CORE 1.05V PWR)PLACEMENT NOTE:PLACE CAPS AT EDGE OF SB
PLACE < 2.54MM OF SB ON SECONDARY OR3.56MM ON PRIMARY NEAR PINS AE7..AJ7
PLACE C2703 < 2.54MM OF PIN A16..T7 OF SBPLACEMENT NOTE:
ICH V5REF_SUS BYPASS(ICH REFERENCE FOR 5V TOLERANCE ON RESUME WELL LOGIC)
PLACEMENT NOTE:PLACE C2704 < 2.54MM OF PIN G4 OF SBON SECONDARY SIDE OR 3.56MM ON PRIMARY
ICH VCCA3GP(VCC1_5_B BYPASS(ICH IO,LOGIC 1.5V PWR)
L2700 MAY HAVE CHANGE TO 0.5UH PART
1
2 2.5VPOLY
20%
CASE-B2
C27101
2
0.1UF
X5R
10%16V
402
C27121
2 X5R
0.1UF10%16V
402
R27001 2
4021/16WMF-LF
5%
1
C27241
2603
6.3V
4.7UF
CERM
20%
L2703
1 2
1.0UH-0.5A-0.675A
1007
C27351
2603
6.3V20%
X5R
10UF
1
210%16V
402X5R
1
2 6.3V10%
402CERM
C27401
210%
X5R
0.1UF16V
402
C27421
2
NOSTUFF
20%
603X5R
10UF6.3V
C27321
2
2.2uF
603
20%6.3VCERM1
C27361
2
4.7uF20%6.3VCERM603
C27331
26.3V
603CERM
20%4.7uF
C27411
210%0.1UF
X5R16V
402
L2702
1 2
10UH-100MA
0805
C27391
2805CERM
22UF20%6.3V
C27041
2
0.1UF
X5R
10%
402
16V
C27381
2 16V
0.1UF
X5R
10%
402
C27371
210%
X5R
0.1UF16V
402
C27201
2 X5R402
16V10%0.1UF
C27431
210%
X5R16V
402
0.1UF
C27151
2 16V
0.1UF
X5R
10%
402
C27091
210%
X5R
0.1UF16V
402
C27181
2 16VX5R
10%
402
0.1UFC27021
210%
X5R16V
402
0.1UF
C27191
2 16V
0.1UF
X5R
10%
402
C27211
2 X5R
0.1UF16V
402
10%
C27231
210%0.1UF16VX5R402
C27221
210%
X5R
0.1UF16V
402
C27251
2 16V
0.1UF
X5R
10%
402
C27261
2
NOSTUFF
16V10%0.1UF
402X5R
C27271
210%
X5R
0.1UF16V
402
C27281
210%
X5R
0.1UF16V
402
C27131
2
0.1UF10%16VX5R402
3
2 HN2S02JESOT-363
D27021
5
2
R2701
12
5%
10
402MF-LF1/16W
2
1
2 CERM
20%6.3V
805
C27061
2 CERM
20%22UF
805
6.3V
C27071
2
2.2UF
603
6.3VCERM1
20%
C27011
2402
10%16VCERM
0.01UFC27081
220%
603X5R
10UF6.3V
C271710%1UF6.3VCERM402
C27141
2
1UF6.3V
402CERM
10%
C27161
2 2.5V
CASE-C2POLY
20%330UF
CRITICAL
R2702
1
2
100MF-LF
5%402
C27291
2 X5R
10%0.1UF16V
402
C2730 1
210%
X5R
0.1UF16V
402
C27341
2 X5R
0.1UF10%16V
402
C27311
2
0.1UF10%16VX5R402
051-745576
SYNC_MASTER=WFERRY
SB Decoupling
01
26
SYNC_DATE=06/01/2006
=PP1V5_S0_SB_VCC1_5_A_ATX
PP1V5_S0_SB_VCCDMIPLL_FVOLTAGE=1.5V
MIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
PP1V5_S0_SB_VCCGLANPLLMIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
VOLTAGE=1.5V
=PP3V3_S0_SB_VCC3_3_SATA
MIN_NECK_WIDTH=0.25MM
VOLTAGE=5V
PP1V5_S0_SB_VCC1_5_BMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
VOLTAGE=1.5V
=PP1V05_S0_SB_CPU_IO
=PP1V5_S0_SB_VCCGLAN1_5
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.3MM
VOLTAGE=5V
=PP3V3_S0_SB
=PP1V5_S0_SB
=PP5V_S5_SB
=PP5V_S0_SB
=PP3V3_S0_SB_VCC3_3_VCCPCORE
PP3V3_G3_SB_RTC
=PP1V25_S0_SB_DMI
=PP1V5_S0_SB
=PP3V3_S0_SB_VCC3_3_DMI
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_3V3_VCCSUSHDA
=PP3V3_S0MWOL_SB_VCCCL3_3
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP3V3R1V5_S0_SB_VCCHDA
=PP1V5_S0_SB_VCCUSBPLL
PP1V5_S0_SB_VCCDMIPLL
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
VOLTAGE=1.5V
=PP1V5_S0_SB_VCC1_5_A
MAKE_BASE=TRUE
PP1V5_S0_SB_VCC1_5_B
=PP3V3_S0_SB_VCC3_3_VCCPCORE
=PP3V3_S5_SB_VCCSUS3_3
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.5VMIN_LINE_WIDTH=0.5MM
PP1V5_S0_SB_VCCSATAPLL
=PPVCORE_S0_SB
=PP3V3_S0MWOL_SB_VCCLAN3_3
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S5_SB
=PP1V5_S0_SB_VCC1_5_A_ARXD2702
1/16W
OMITC27111UF
PP5V_S0_SB_V5REF
4
C27030.1UF
HN2S02JESOT-363
PP5V_S5_SB_V5REF_SUS
MIN_LINE_WIDTH=0.3MM
0805-1FERR-330-OHM-1.5A
L2700
NOSTUFFC270522UF220UF
C2700
1
=PP1V5_S0_SB
OMIT
CRITICAL
26A4
26C6
35C7
26D6
25D6
25C3
26D6
26A6
27D4
26C8
26B6
25D6
26C6
26D2
24A8
25B6
26A8
25C3
23C2
22D2
39C8
26C8
25C3
25D6
25C3
26A8
25C3
25A3
25A3
25B3
25A6
25B6
25B3
25A6
25B6
23C2
25C3
25A3
25D3
25A3
25B3
25C3
24A3
25B6
7B7
7B7
25A6
7D4
25D6
22D7
7D7
25A6
25D6
7D4
7B7
7C1
7A7
7D4
22D7
7C7
7B7
7D4
7D1
7D1
7D1
7C4
7B6
7C4
7B7
25C3
7B7
22D7
7D4
7D1
7D7
7C4
7D4
7D4
7D1
7B7
GND
Y
A
B
VCC
OUT
OUT
NC
NC
Y
B
A
IN
OUT
IN
IN
Y
B
A
IN
OUT
IN
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
518S0519
RTC Battery Connector
It may take a few days before this is done through2-input NAND gate-APN:311S0304Pulled a new APN for U2803(0.6mm max
CPU VCORE PSI
MIN_LINE_WIDTH=0.3MM
it provides a set of pads
Initial resistor values are based on CRB,
This part is never stuffed, Silk: "SYS RST"
NC
Buffered
Linda Card represents 3 loads
Unbuffered
but may change after characterization.
NC
on the board to short or
VOLTAGE=3V
VOLTAGE=3VMIN_LINE_WIDTH=0.3MM
Platform Reset Connections
This will allow us to sequence this part under wireless card
to solder a reset button. In CLOSE=12.5pFChange Y2800 to 197S019 -7.0mmx1.5mmx1.4mm
197S0219
SB RTC Crystal Circuit
C28091 2
402
10PF
CERM50V5%
C2807 1
2402
0.1UF20%10VCERM
C2811 1
210V20%CERM
0.1UF
402
J2800
3
4
1
2
M-RT-SM78171-0002
CRITICAL
R28011 2
402
5%MF-LF1/16W
0
R28021 20
4021/16W5%
MF-LF
U2803 2
1
3
5
4
SONTC7SH00FEF
CRITICAL
R28031
2
100K5%
402MF-LF1/16W
R28861 21005%
1/16WMF-LF402
C28101
2402
1UF6.3V10%CERM
C28051
2
1UF6.3VCERM402
10%
R28001 220K
1/16W402
5%MF-LF
D2800
1 5
2
SOT-363HN2S02JE
R28061
2MF-LF402
5%1M1/16W
D2800
3 4
2
SOT-363HN2S02JE
R28871 2
1/16WMF-LF
05%
402R28851 2
1/16WMF-LF402
05%
R28831 2
5%
402MF-LF1/16W
100
R28811 2
1/16W5%
0
MF-LF402
U28802
1
3
5
4
TC7SZ08AFEFSOT665
CRITICAL
R28801
2
100K1/16W5%
402MF-LF
C2880 1
2CERM402
20%10V
0.1UF
R28971
2MF-LF
4021/16W10K5%
I59
R28981
2
OMIT
1/16WMF-LF
5%
402
100K
R28111
2MF-LF4021/16W5%1.8K
U28012
1
3
5
4
TC7SZ08AFEFSOT665
CRITICAL
R28121
2MF-LF1/16W
10K5%
402
R28071
2
1K5%1/16WMF-LF402
R289612
5%MF-LF402
1K
1/16W
C28081 2
402
10PF
CERM50V5%
Y2800 1
47X1.5X1.4-SM
CRITICAL
32.768K
R28101 2
MF-LF402
5%1/16W
0
R28091
2
1/16W402
5%10M
MF-LF
051-745576
01
SYNC_MASTER=NBSB Misc
SYNC_DATE=07/26/2005
27
MAKE_BASE=TRUEVR_PWRGD_CK505_L
=PP3V3_S0_SB_PM =PP3V3_S0_SB_PM
CK410_PD_VTT_PWRGD_L
PLT_RST_LMAKE_BASE=TRUE
PLT_RST_BUF_L
IMVP6_PSI_L
VR_PWRGOOD_DELAY
PP3V3_G3C_SB_RTC_DMAKE_BASE=TRUE
SB_RTC_X1
ENET_RESET_L
XDP_DBRESET_L_R
SMC_LRESET_L
TMDS_RST_L
SB_SM_INTRUDER_L
XDP_DBRESET_L
=PP3V3_S0_RSTBUF
=PP3V3_S5_SB_PM
PP3V3_G3_SB_RTC=PP3V42_G3H_SB_RTC
PPVBATT_G3C_RTC
PPVBATT_G3C_RTC_R SB_RTC_RST_L
PM_SYSRST_LMAKE_BASE=TRUE
VR_PWRGD_CK505
DEBUG_RESET_L
AIRPORT_RST_L
NB_RESET_L
CPU_PSI_LMAKE_BASE=TRUE
ALL_SYS_PWRGDPM_SB_PWROK
CLINK_MPWROK
SB_RTC_X2
SB_RTC_X1_R
26A5
58A3
27B6 27B8
67C6
59C7
12B4
25D6
44B8
46B6
44D8
8B3
59C7
7D4 7D4
23A6
59C7
15B6
22D8
34B8
44C8
68B5
22D8
9C6
7D4
7D1
22D7 7B1
22D8
24D5
8B3
6C2
33C3
15B6
9A2
6B2
24C3
8B1
22D8
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
IN
BIIN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
INVSS_PCI
CLKREQ_7*
CLKREQ_8*
GPU_STOP*
REF_0/FS_C/TEST_SEL
48M/FS_A
DOT_96/27M
DOT_96*/27M_SS
SRC_8*
SRC_8
PCI_5/FCT_SEL
PCIF_0/ITP_EN
VDD_PCI
VDD_48
THRM_PAD
SRC_4*
CLKREQ_3*
SRC_3
SRC_0/LCD_CLK
SRC_0*/LCD_CLK*
CPU_1_MCH*
CPU_1_MCH
CPU_ITP*/SRC_10*
CPU_ITP/SRC_10
VSS_SRC
VSS_REF
VSS_CPU
VSS_48
SDA
PCIF_1
PCI_4
PCI_3
PCI_2
PCI_1
VSS_A
XTAL_OUT
CLKREQ_6*
CLKREQ_5*
CLKREQ_4*
CLKREQ_1*
SCL
CPU_0
SRC_1
SRC_2*
SRC_2
SRC_4
SRC_5*
SRC_5
SRC_7*
SRC_7
SRC_6*
SRC_6
VDD_REF
CPU_0*
SRC_3*
CPU_STOP*
PCI_STOP*
XTAL_IN
VDD_A
FS_B/TEST_MODE
VDD_CPU
SRC_1*
CKPWRGD/PD*
VDD_SRC
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
SELIGO RECOMMEND TO REMOVE L2903,R2900,C2907,C2910
STUFF C2907,C2910,C2916,C2911,C2914
(PCI SLOT)
(ICH8M PCI 33MHZ)
(PULL UP PIN 68 TO ENABLE ITP HOST CLK)
(PORT80 LPC 33MHZ)
(ICH SM BUS)
(FW PCI 33MHZ)(TPM LPC 33MHZ)(SMC LPC 33MHZ)
STUFF R2905 FOR CK410M MODE
(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
(FROM ICH8M)(ICH8M USB 48MHZ)(ICH8M,SIO,LPC REF. 14.318MHZ)
(DB400 SRC )
(SLOT D - 4 LANE PCI-E FOR EXPRESSCARD)
(ICH SATA 100 MHZ)(FROM ICH8M GPIO35)
(GMCH G_CLKIN 100 MHZ )(FROM GMCH CLK_REQ*)U2900 HAS INTERNAL PU ON PGMODE
(WIRELESS PCI-E 100 MHZ )
SPREAD
DOT96C
PIN 7
(ICH8M DMI 100 MHZ )
(INT PU)
(NO INT PU)
(NO INT PD)(INT PU)
(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)(EACH POWER PIN PLACED ONE 0.1UF)
(SLOT E )
475 OHM FOR CK410MCOMPATIBILITY
(FROM ICH8M GPIO15 STPPCI* )(FROM ICH8M GPIO25 STPCPU* )
(CPU HOST 133/167MHZ)
(GMCH HOST 133/167MHZ)
(ITP HOST 133/167MHZ)
0 = VTT_PWRGD#/PD1 = CKPWRGD/PD#
0
1
(SLOT F - GPU PCI-E 100 MHZ )
(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)
SRCT0
PIN 11
100MC_SST
* FOR EXT. GRAPHIC SYSTEM
* FOR INT. GRAPHIC SYSTEM
FCTSEL1
SPREAD27M NON 27M
SRCC0
100MT_SST
(INT PU)
(INT PU)
(INT PU)
PIN 10
(INT PU)
(INT PD)
PIN 6
DOT96T
ORIGINAL DESIGN:
USE 2.2OHM FOR R2900,R2901 AND 1OHM FOR R2902
USE 155S0302 FOR L2902(R2906) AND L2903(R2907)
R2901,L2902,C2916,C2911,C2914 and R2902
NEED TO CHECK CAP VALUE
C29101
2
10UF
603
20%
X5R6.3V
NOSTUFF
C29151
2402
16V
0.1UF
X5R
10%
24C8 29C2
24C8 29C2
6C7 29D6 75D3
6C7 29D6 75D3
6C7 29D6 75D3
6C7 29D6 75D3
6C7 29D6 75D3
6C7 29D6 75D3
6C7 29C6 75C3
6C7 29C6 75D3
8C4
8C4
6C7 29C6 75C3
6C7 29C6 75C3
6C7 29C6 75C3
6C7 29B6 75C3
6C7 29C6 75C3
6C7 29C6 75C3
C29901
2402
50VCERM
18PF5%
C29891
2402
50VCERM
18PF5%
29B6 75D3
8C4 75D3
29A6 75D3
8C4 75D3
47D6
47D6
C29071
2 X5R603
6.3V20%10UF
NOSTUFF
29B8
29B2 75D3
C29111
2 6.3V10%
402CERM
1UF
NOSTUFF
C2901 1
26.3V
603
20%
X5R
10UFC29021
2402X5R16V
0.1UF10%
L2901
1 2
0402-LF
FERR-120-OHM-1.5A
C2900 1
2CERM
1UF
402
10%6.3V
R29011 2
1/16WMF-LF
5%
0
402
R29021 2
5%
MF-LF1/16W
0
402
C29141
2 6.3V20%
603X5R
10UF
NOSTUFF
R29001 2
1/16WMF-LF
5%
0
402
29C2
29C2
33C5
R29031
2402
1/16WMF-LF
5%10K
6C7 29B6 75D3
29B6 75D3
8B3
8C4
8C4
8C4
8C4
6C7 29C6 75C3
6C7 29C6 75C3
15A3
Y29011 2
14.31818
5X3.2-SM
CRITICAL
R29051
2
4751/16W
NOSTUFF
1%
MF-LF402
C29161
2 X5R603
6.3V20%10UF
NOSTUFF
C29031
2 X5R
10%0.1UF16V
402
C29041
2
0.1UF
X5R402
16V10%
C29051
210%0.1UF
X5R16V
402
C29061
2402
16V
0.1UF10%
X5R
C29081
2
0.1UF10%
X5R16V
402
C29121
2
0.1UF10%
X5R16V
402
C29131
2402
16V
0.1UF
X5R
10%
C29091
210%
X5R
0.1UF16V
402
U2900
4
2
9
59
20
60
25
40
34
4544
4241
3736
55
67
8
53
5758636465
56
681
54
4748
1011
1314
1516
1819
2122
2324
2627
2930
3332
69
3
38
43
6167
49
12172835
5
39
46
6266
52
31
5150
SLG2AP101QFN
CRITICAL
8C4 34B8
6B7 29B6 75C3
6B7 29B6 75C3
6C7 29B6 75D3
29D8 75D3
29D8 75D3
6C7 29B6 75D3
24C3
R29061 2
5%
MF-LF1/16W
0
402
R29071 2
5%
MF-LF1/16W
0
402
28 76
SYNC_DATE=06/06/2006SYNC_MASTER=DSIMON
Clock (CK505)
01051-7455
=PP3V3_S0_CK505
MIN_LINE_WIDTH=0.5mmVOLTAGE=3.3VMIN_NECK_WIDTH=0.2mm
PP3V3_S0_CK505_VDDA_R
MIN_LINE_WIDTH=0.5mmPP3V3_S0_CK505_VDD_PCI
MIN_NECK_WIDTH=0.2mmVOLTAGE=3.3V
=PP3V3_S0_CK505
CK505_PCIF0_CLK
=PP3V3_S0_CK505
CK505_XTAL_INCK505_XTAL_OUT
CK505_PGMODE
CK505_PCI5_FCTSEL1
=SMBUS_CK505_SDA
CK505_PCIF1_CLK
=SMBUS_CK505_SCL
SB_CLK100M_SATA_OE_L
CK505_LVDS_PCK505_LVDS_N
CK505_REF1CK505_CLK14P3M_TIMER
MIN_NECK_WIDTH=0.2mmVOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mmPP3V3_S0_CK505_VDD48
CK505_SRC4_N
CK505_CPU1_NCK505_CPU1_P
CK505_CPU2_ITP_SRC10_NCK505_CPU2_ITP_SRC10_P
CK505_PCI4_CLKCK505_PCI3_CLKCK505_PCI2_CLKCK505_PCI1_CLK
CK505_SRC_CLKREQ1_L
CK505_CPU0_P
TP_CK505_SRC1_P
CK505_SRC2_N
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
PP3V3_S0_CK505_VDD_REF
PM_STPPCI_L
PP3V3_S0_CK505_VDDAVOLTAGE=3.3V
MIN_NECK_WIDTH=0.2mmMIN_LINE_WIDTH=0.5mm
CK505_FSB_TEST_MODE
TP_CK505_SRC1_N
CK505_CPU0_N
PM_STPCPU_L
CK505_SRC2_P
TP_CK505_SRC3_PCK505_SRC_CLKREQ3_L
CK505_SRC4_P
NB_CLKREQ_L
TP_CK505_SRC7_N
CK505_SRC_CLKREQ6_LCK505_SRC6_PCK505_SRC6_N
CK505_SRC5_N
CLK_PWRGD
CK505_DOT96_27M_N
CK505_SRC8_N
CK505_DOT96_27M_P
CK505_USB48_FSA
CK505_SRC8_P=ENET_CLKREQ_L
VOLTAGE=3.3V
PP3V3_S0_CK505_VDD_CPU_SRCMIN_LINE_WIDTH=0.5mmMIN_NECK_WIDTH=0.2mm
CK505_PGMODETP_CK505_SRC7_P
CK505_SRC5_P
TP_CK505_SRC3_N
29D2
29D2
29D2
29B2
29B2
29B2
28D3
28D8
28D8
28C8
28C8
28D3
7C4
7C4
7C4
28A4
28B5
IN
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUTIN
IN
OUTIN
OUT
OUT
BI
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUTIN
OUT
OUT
OUT
IN
OUT
OUT
OUTIN
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
(FROM CPU FS_A)
(Int GFX DOT 96MHZ)
(TO FIREWIRE PCI 33MHZ)
(TO ICH8M PCI 33MHZ)
(PORT80 LPC 33MHZ)
(TO SMC PCI 33MHZ)
(Int Gfx LVDS 100MHz)
(ITP HOST 133/167MHZ)
(GMCH HOST 133/167MHZ)
(ICH8M DMI 100MHZ)
Place close to CLK GenFor reducing noise coupling to wireless frequencies
(FOR YUKON 100MHZ)
(CPU HOST 133/167MHZ)
(TO MCH FS_B)
(ICH8M 14.318MHZ)
(TO MCH FS_C)
01
0
FS_A
0
FS_B
0
01
1
1
0
0
11
01
(TO ICH8M USB 48MHZ)
(TO MCH FS_A)
1
1
0
10 0 1
(FROM CPU FS_C)
CPU
266M133M166M
200M
400M
100M333M
CLKREQ Controls
CLK Termination
Resrvd
0
1
FS_C
*
(FROM CPU FS_B)
NOSTUFF R3082, R3086, R3090FOR MANUAL CPU FREQUENCY
CPU speed is currently set to 200MHz
(ICH8M SATA 100MHZ)
(GMCH PEG/DMI 100MHZ)
(WIRELESS PCI-E MINI 100MHZ)
6C7 28C4 75D3
6C7 28C4 75D3
6C7 28C4 75D3
6C7 28C4 75D3
6C7 28A4 75D3
6C7 28A4 75D3
15C3 75B3
15C3 75B3
6C7 28B4 75C3
6C7 28B4 75C3
23D2 75B3
6C7 28B4 75C3
6C7 28B4 75C3
28B6 75D3
28B6 75D3
6C7 28B6 75D3
29A5 37A5 75B3
29A5 44C8 75B3
23A6 29A5 75B3
33C5 75A3
33C5 75B3 6C7 28B4 75C3
6C7 28B4 75C3
6C2 46C4 75C3
28B8 75D3
23C2 75B3
R30671
2402MF-LF
NOSTUFF
10K5%1/16W
R30831
2402
5%
MF-LF1/16W
1K
R30841
2402
1/16WMF-LF
5%1K
28C6
28B6 75D3
22B6 75B3
22B6 75B3
6C7 28B4 75C3
6C7 28B4 75C3
R30801
2
NOSTUFF
1K
402
1/16WMF-LF
5%
R30821 2
402
1/16W5%
0
MF-LF
9B4 70B3
9A4 70B3
R30861 2
402
1/16WMF-LF
0
5%
R30871
2
1K5%
402MF-LF1/16W
NOSTUFF
13B3 75C3
13B3 75C3
9B6 75C3
24D3 29A5 75B3
R30321 2
1/16WMF-LF
33
5%
402
28A4 75D3
R30331 2
402
1/16WMF-LF
5%
2.2K
9B6 75C3
R30811 2
402MF-LF
1K
5%1/16W
15C6 70B3
R30851 2
402
1/16WMF-LF
5%
1K15C6 70B3
9A4 70B3
R30901 2
5%
402MF-LF
0
1/16W
R30881
2402
5%
NOSTUFF
MF-LF1/16W
1K
R30911
2MF-LF
402
1/16W
1K5%
12B3
R30891 2
1/16WMF-LF
1K
5%
402
15B6 70B3
24D3 29A5 75B3
R30341 2
MF-LF1/16W
33
402
5%
28A4 75D3
12B3
8B1 75B3
8A1 75B3
6C7 28B4 75D3
6C7 28B4 75C3
8B1 75B3
8B1 75B3
R30001 2
402
0
5%1/16WMF-LF
R30351 2
402
1/16WMF-LF
10K
5%
R30011 2
402
0
MF-LF1/16W5%
R30021 2
402
0
5%1/16WMF-LF
R30031 2
402
0
1/16W5%
MF-LFR30041 2
402
0
5%1/16WMF-LF
R30051 2
402
0
MF-LF1/16W5%
R30061 2
402
0
5%
MF-LF1/16W R3007
1 2
402
0
MF-LF1/16W5%
R30101 2
402
0
5%
MF-LF1/16W R3011
1 2
402
0
1/16WMF-LF
5%
R30141 2
402
0
MF-LF1/16W5% R3015
1 2
402
0
MF-LF1/16W5%
R30161 2
402
0
5%1/16WMF-LF
R30171 2
402
0
MF-LF
5%1/16WR3018
1 2
402
0
5%1/16WMF-LF
R30191 2
402
0
5%
MF-LF1/16W
R30241 2
402
0
MF-LF1/16W5% R3025
1 2
402
0
1/16WMF-LF
5%
R30261 2
1/16W5%
33
402MF-LF R3027
1 2
1/16W
33
402
5%
MF-LFR30281 2
MF-LF1/16W5%
33
402
R30301 2
33
1/16W5%
MF-LF402
R30461 2
4021/16WMF-LF
5%10K
R30471 2
10K 5%
MF-LF1/16W 402
R30501 2
10K 5%
MF-LF1/16W
NOSTUFF
402
R30511 2
4021/16W
5%10KNOSTUFF
MF-LF
R30661
2
5%
MF-LF1/16W
402
10K
C30001
2
3.3PF
NOSTUFF
CERM50V0.25%
402
C30011
2402
NOSTUFF
3.3PF0.25%50VCERM
C30021
2
NOSTUFF
402
50V0.25%3.3PFCERM
C30031
2
NOSTUFF
0.25%3.3PF
402CERM50V
34C8
34C8
R30231 2
402
0
1/16W5%
MF-LF
R30221 2
402
0
5%1/16WMF-LF
6B7 28A4 75C3
6B7 28A4 75C3
C30041
2 50V0.25%3.3PF
NOSTUFF
402CERM
6C7 28C4 75D3
6C7 28C4 75D3
051-745529
SYNC_DATE=06/06/2006
Clock Termination
01
76
SYNC_MASTER=DSIMON-WF
SB_CLK48M_USBCTLR
CK505_CPU0_N
NB_CLK96M_DOT_P
CK505_DOT96_27M_N
SB_CLK100M_SATA_P
NB_CLK100M_DPLLSS_N
NB_CLK100M_DPLLSS_P
SB_CLK100M_DMI_P
NB_CLK100M_PCIE_P
PCIE_CLK100M_MINI_P
PCIE_CLK100M_ENET_P
CK505_SRC6_N
CK505_SRC8_P
CK505_SRC6_P
CK505_SRC5_P
CK505_SRC2_P
CK505_SRC5_N
CK505_LVDS_N
CK505_SRC2_N
CK505_SRC4_P
CK505_SRC4_N
CK505_SRC8_N
CK505_LVDS_P
FSB_CLK_CPU_P
CPU_XDP_CLK_P
FSB_CLK_NB_PCK505_CPU1_P
CK505_CPU0_P
CK505_CPU1_N
CK505_CPU2_ITP_SRC10_P
CK505_CPU2_ITP_SRC10_N
FSB_CLK_CPU_N
PCI_CLK33M_LPCPLUS
NB_CLK96M_DOT_N
CK505_PCIF0_CLK
CK505_PCIF1_CLK
CK505_DOT96_27M_P
PCI_CLK33M_SB
PCI_CLK33M_FW
FSB_CLK_NB_N
PCI_CLK33M_SMC
CK505_FSB_TEST_MODE
SB_CLK100M_DMI_N
CK505_CLK14P3M_TIMER
CK505_USB48_FSA
CPU_BSEL<0>
CPU_BSEL<2>
NB_BSEL<1>
CK505_FSA
NB_BSEL<0>
=PP1V25R1V05_S0_FSB_NB
CK505_FSC
SB_CLK14P3M_TIMER
NB_BSEL<2>
CPU_XDP_CLK_N
=PP3V3_S0_CK505
=PP3V3_S0_CK505
CK505_FSC
CK505_FSA
=PP1V25R1V05_S0_FSB_NB
=PP1V25R1V05_S0_FSB_NB
CK505_PCI5_FCTSEL1
PCIE_CLK100M_MINI_N
PCIE_CLK100M_ENET_N
SB_CLK100M_SATA_N
CK505_SRC_CLKREQ1_L
PM_STPCPU_L
PM_STPPCI_L
CK505_SRC_CLKREQ3_L
NB_CLK100M_PCIE_N
CK505_PCI1_CLK
CK505_PCI3_CLK
CPU_BSEL<1>
PCI_CLK33M_FW
PCI_CLK33M_SMC
SB_CLK14P3M_TIMER
SB_CLK48M_USBCTLR
PCI_CLK33M_SB
29D2
29B2
29C6
28D8
28D8
29C6
29B6
28D3
28D3
29B6
29C6
75B3
75B3
75B3
75B3
75B3
75B3
13B7
75B3
28C8
28C8
75B3
75B3
13B7
13B7
28C4
28C4
37A5
44C8
29D6
29D6
29B3
29C8
7C7
29A8
7C4
7C4
29D6
29D6
7C7
7C7
28B4
24C8
24C8
28B4
29B3
29A3
24D3
24D3
23A6
VSS10
VSS2
DQ5
SA1
SA0
VSS58
DQ63
DQ62
VSS56
DQS7
DQS7*
VSS54
DQ60
VSS52
DQ54
VSS50
VSS48
CK1*
CK1
VSS46
DQ53
DQ52
VSS44
VSS42
DQS5
DQS5*
VSS39
DQ45
DQ44
VSS37
DQ39
DQ38
VSS35
DM4
VSS34
DQ37
DQ36
VSS32
NC3
VDD11
NC/A13
ODT0
VDD9
S0*
RAS*
BA1
VDD7
A0
A2
A4
VDD5
A6
A7
A11
VDD3
NC/A14
NC/A15
VDD1
NC/CKE1
VSS30
DQ31
DQ30
VSS28
DQS3
DQS3*
VSS26
DQ29
DQ28
VSS24
DQ23
DQ22
VSS22
DM2
NC0
VSS19
DQ21
DQ20
VSS17
VSS15
DQ15
DQ14
VSS13
CK0*
CK0
VSS11
DQ13
VSS7
DQ7
VSS5
DM0
DQ4
VSS0
DM1
DQ12
DQ6
DQ47
DQ46
DQ61
DQ55
DM6
VDDSPD
SCL
SDA
VSS57
DQ59
DQ58
VSS55
DM7
VSS53
DQ56
VSS51
DQ50
VSS49
DQS6*
VSS47
NC_TEST
VSS45
DQ49
DQ48
VSS43
VSS41
DM5
VSS40
DQ41
VSS38
DQ35
VSS36
DQS4
DQS4*
VSS33
DQ33
DQ32
VSS31
NC/ODT1
VDD10
NC/S1*
CAS*
VDD8
WE*
BA0
A10/AP
VDD6
A1
A3
A5
VDD4
A8
A9
A12
VDD2
BA2
NC2
VDD0
CKE0
VSS29
DQ27
DQ26
VSS27
NC1
DM3
VSS25
DQ25
DQ24
VSS23
DQ19
DQ18
VSS21
DQS2
DQS2*
VSS18
DQ17
DQ16
VSS16
VSS14
DQ11
DQ10
VSS12
DQS1
DQS1*
DQ9
DQ8
VSS8
DQ3
DQ2
VSS6
DQS0
DQS0*
VSS4
VSS1
VREF
DQ0
DQ1
DQ34
DQ40
DQ42
DQ43
DQS6
DQ51
DQ57
KEY
VSS9
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
ADDR=0xA0(WR)/0xA1(RD)
NC
DDR2 Bypass CapsNC
NC
DIP DIMM CONN
One 0.1uF per connector
DDR2 VRef
Yellow uses 10K divider and TLV2463
(See Capell Valley pg 47)
Page Notes
NC
516-0135
NC
NC
when they get cheaper.
- =PP1V8_S3_MEM
- =I2C_MEM_SDA- =I2C_MEM_SCL
- =PPSPD_S0_MEM (2.5V - 3.3V)
(NONE)BOM options provided by this page:
Power aliases required by this page:
(For return current)
Signal aliases required by this page:
to drive MCH and DIMM connectors.
The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,
C31091
220%6.3V4.7uF
603CERM
10V
C31101
2
0.1UF
CERM
20%
402
C31001
2
0.1UF20%10VCERM402
C31211
2
0.1UFCERM10V20%
402
C31201
2402
4VX5R20%2.2UF
C31221
2 4V
402
20%2.2UFX5R
C31301
2
2.2UF20%6.3VCERM402-LF
C31321
2
2.2UF20%
CERM6.3V
402-LF
C31311
2
2.2UF20%
CERM6.3V
402-LF
J3101
102101
105
9089
10099
9897
94
92
93
91
107
106
85
113
30
32
164
166
79
10
26
52
67
130
147
170
185
5
7
35
37
20
22
36
38
43
45
55
57
17
44
46
56
58
61
63
73
75
62
64
19
74
76
123
125
135
137
124
126
134
136
4
141
143
151
153
140
142
152
154
157
159
6
173
175
158
160
174
176
179
181
189
191
14
180
182
192
194
16
23
25
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
201
202
116
86
84
80
119
115
50
69
83
120
163
114
108
110
198
200
197
195
81 82
117 118
87 88
95 96
103 104
111 112
199
1 2
3
27 28
33 34
39 40
41 42
47 48
8
53 54
59 60
65 66
71 72
77 78
121 122
127 128
132
133
138
139
144
9
145
149 150
155 156
161 162
165
168
171
12
172
177 178
183 184
187
190
193
196
15
18
21
24
109
DDR2-SODIMM-STD
CRITICAL
F-RT-TH3
OMIT
20%
C31111
2 10VCERM
0.1UF
402
C31121
2
0.1UF10V20%
402CERM
C31131
220%10VCERM
0.1UF
402
C31141
2
0.1UF
CERM10V20%
402
C31151
220%10VCERM
0.1UF
402
C31161
2
2.2UF20%6.3VCERM402-LF
C31171
2
2.2UF20%6.3VCERM402-LF
R31031 210K
5%1/16WMF-LF402
R31021 2
402MF-LF1/16W5%
10K
R31001
2
1/16W1%1K
MF-LF402
R31011
2
1%1K1/16WMF-LF402
SYNC_MASTER=MEMORY
DDR2 SO-DIMM Connector A
01
30
SYNC_DATE=06/20/2005
76
051-7455
MEM_ODT<1>
MEM_A_BS<0>MEM_A_A<10>
MEM_A_DQ<47>MEM_A_DQ<45>
MEM_A_DQ<60>
MEM_A_SA1
MEM_CS_L<0>
MEM_A_A<6>
MEM_A_DQ<61>
MEM_CS_L<1>MEM_A_CAS_L
MEM_A_A<5>
MEM_A_BS<2>
MEM_A_DQ<14>MEM_A_DQ<12>
MEM_A_DQS_P<0>
MEM_VREF_A
MEM_A_SA0
MEM_A_SA1MEM_A_SA0
MEM_A_DQ<62>
MEM_A_DM<7>
MEM_A_DQS_P<5>
MEM_A_DQ<48>MEM_A_DQ<53>
MEM_A_DQS_N<6>MEM_A_DQS_P<6>
MEM_A_DQ<50>
MEM_A_DQ<57>
=PP1V8_S3_MEM
MEM_A_A<14>
MEM_A_DQS_N<2>
MEM_A_DQ<21>MEM_A_DQ<18>
MEM_A_DQ<31>
=PPSPD_S0_MEM
MEM_A_DM<6>
MEM_A_DQ<49>MEM_A_DQ<52>
MEM_A_DQ<63>MEM_A_DQ<59>
MEM_A_DQS_P<7>MEM_A_DQS_N<7>
MEM_A_DQ<56>
MEM_A_DQ<43>
MEM_A_DQ<42>MEM_A_DQ<41>
MEM_A_DQ<36>
MEM_A_DQ<39>MEM_A_DQ<38>
MEM_A_WE_L
MEM_A_A<1>MEM_A_A<3>
MEM_A_A<8>MEM_A_A<9>MEM_A_A<12>
=GND_CHASSIS_DIPDIMM_CENTER
MEM_A_DQ<6>
MEM_A_DQ<11>
MEM_A_DQ<29>
MEM_A_DQ<2>
MEM_A_DQ<8>
MEM_A_DQS_N<1>
MEM_A_DQ<9>
MEM_A_DQS_P<2>
MEM_A_DQ<26>
MEM_A_DQ<13>
MEM_A_DQS_P<1>
MEM_A_DQ<10>
=PP1V8_S3M_MEM_NB
MEM_CKE<0>
MEM_A_A<13>
MEM_A_RAS_L
MEM_A_DQ<30>
MEM_VREF_AMIN_LINE_WIDTH=0.25 mmMIN_NECK_WIDTH=0.25 mm
VOLTAGE=0.9V
MEM_A_DQ<17>
MEM_A_DQ<54>
MEM_CLK_N<1>
MEM_A_DQS_N<5>
MEM_A_DQ<40>MEM_A_DQ<44>
MEM_A_DQ<35>MEM_A_DQ<32>
MEM_A_DM<4>
MEM_A_DQ<34>MEM_A_DQ<37>
MEM_A_DQ<58>
MEM_A_DQ<28>
MEM_A_DM<1>
MEM_A_DQ<46>
=I2C_SODIMMA_SDA
MEM_A_DQ<55>MEM_A_DQ<51>
MEM_A_DM<5>
MEM_A_DQ<33>
MEM_A_DQS_P<4>MEM_A_DQS_N<4>
MEM_A_DM<2>
MEM_A_DQ<19>
MEM_A_DQ<27>
MEM_A_DQS_P<3>MEM_A_DQS_N<3>
=GND_CHASSIS_DIPDIMM_LEFT
MEM_A_A<4>
DIMM_OVERTEMPA_L
MEM_CLK_P<1>
MEM_A_A<15>
MEM_ODT<0>
MEM_A_DQ<24>
=I2C_SODIMMA_SCL
MEM_A_DQ<23>
MEM_A_DM<3>
MEM_A_DQ<15>
MEM_A_DM<0>
MEM_A_DQ<25>
MEM_A_A<7>MEM_A_A<11>
MEM_CKE<1>
MEM_A_DQ<20>
MEM_A_DQ<22>MEM_A_DQ<16>
MEM_A_DQS_N<0>
MEM_CLK_N<0>MEM_CLK_P<0>
MEM_A_DQ<3>
MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_BS<1>
MEM_A_A<0>MEM_A_A<2>
MEM_A_DQ<7>
=PP1V8_S3_MEM
MEM_A_DQ<5>MEM_A_DQ<4>
=PP1V8_S3_MEM
31D6 31D6
31D6
31D4
31D2
31D4
31D4
31B2
20C8
31B2
31B2
72D3
72D3
72D3
72D3
72D3
72D3
72D3
72D3
72D3
30D4
72D3
31A7
72D3
72D3
72D3
72D3
72D3
72D3
17D7
72D3
72D3
72D3
72D3
72D3
72D3
72D3
72D3
72D3
72D3
72D3
30D6
30D6
32D6
32C6
32C6
72D3
72D3
72D3
32D6
32C6
72D3
32D6
32B6
32C6
32C6
72D3
72D3
72C3
72D3
72C3
72C3
72D3
72D3
72C3
72C3
72D3
72D3
30B2
32C6
72C3
72D3
72D3
72D3
31A3
72C3
72D3
72D3
72D3
72D3
72C3
72C3
72D3
72D3
72D3
72D3
72D3
72D3
72D3
32B6
32C6
32C6
32C6
32C6
32C6
72D3
72D3
72D3
72D3
72D3
72C3
72D3
72C3
72D3
72D3
72C3
72D3
15D2
32D6
32C6
32B6
72D3
72D3
72D3
72D3
72C3
72D3
72D3
72D3
72D3
72C3
72D3
72D3
72D3
72D3
72C3
72D3
72D3
72D3
72C3
72D3
72C3
72C3
72C3
72D3
72D3
72C3
72C3
32C6
72D3
32D6
72D3
72D3
72C3
72D3
72C3
72D3
32C6
32C6
32D6
72D3
72D3
72D3
72C3
72D3
72D3
72D3
72D3
72D3
32C6
32C6
32C6
72D3
30B2
72D3
72D3
30D4
15C3
16D5
16B5
16B8
16B8
16A8
30A4
15D3
16B5
16A8
15D3
16D5
16B5
16D5
16C8
16C8
16C5
30D1
30A4
30A4
30A4
16A8
16C5
16C5
16B8
16B8
16C5
16C5
16B8
16B8
7B4
15C6
16C5
16C8
16C8
16C8
7C4
16C5
16B8
16B8
16A8
16B8
16C5
16C5
16B8
16B8
16B8
16B8
16B8
16B8
16B8
16B5
16C5
16B5
16B5
16B5
16B5
16D8
16C8
16C8
16D8
16C8
16C5
16C8
16C5
16C8
16C8
16C5
16C8
7A4
15D3
16B5
16B5
16C8
30D7
16C8
16B8
15D3
16C5
16B8
16B8
16B8
16C8
16C5
16B8
16B8
16B8
16C8
16D5
16B8
47D6
16B8
16B8
16C5
16C8
16C5
16C5
16C5
16C8
16C8
16C5
16C5
8D8
16B5
8B1
15D3
8B4
15C3
16C8
47D6
16C8
16C5
16C8
16D5
16C8
16B5
16B5
15D3
16C8
16C8
16C8
16C5
15D3
15D3
16D8
16D8
16D8
16D5
16C5
16B5
16D8
7B4
16D8
16D8
7B4
VSS10
VSS2
DQ5
SA1
SA0
VSS58
DQ63
DQ62
VSS56
DQS7
DQS7*
VSS54
DQ60
VSS52
DQ54
VSS50
VSS48
CK1*
CK1
VSS46
DQ53
DQ52
VSS44
VSS42
DQS5
DQS5*
VSS39
DQ45
DQ44
VSS37
DQ39
DQ38
VSS35
DM4
VSS34
DQ37
DQ36
VSS32
NC3
VDD11
NC/A13
ODT0
VDD9
S0*
RAS*
BA1
VDD7
A0
A2
A4
VDD5
A6
A7
A11
VDD3
NC/A14
NC/A15
VDD1
NC/CKE1
VSS30
DQ31
DQ30
VSS28
DQS3
DQS3*
VSS26
DQ29
DQ28
VSS24
DQ23
DQ22
VSS22
DM2
NC0
VSS19
DQ21
DQ20
VSS17
VSS15
DQ15
DQ14
VSS13
CK0*
CK0
VSS11
DQ13
VSS7
DQ7
VSS5
DM0
DQ4
VSS0
DM1
DQ12
DQ6
DQ47
DQ46
DQ61
DQ55
DM6
VDDSPD
SCL
SDA
VSS57
DQ59
DQ58
VSS55
DM7
VSS53
DQ56
VSS51
DQ50
VSS49
DQS6*
VSS47
NC_TEST
VSS45
DQ49
DQ48
VSS43
VSS41
DM5
VSS40
DQ41
VSS38
DQ35
VSS36
DQS4
DQS4*
VSS33
DQ33
DQ32
VSS31
NC/ODT1
VDD10
NC/S1*
CAS*
VDD8
WE*
BA0
A10/AP
VDD6
A1
A3
A5
VDD4
A8
A9
A12
VDD2
BA2
NC2
VDD0
CKE0
VSS29
DQ27
DQ26
VSS27
NC1
DM3
VSS25
DQ25
DQ24
VSS23
DQ19
DQ18
VSS21
DQS2
DQS2*
VSS18
DQ17
DQ16
VSS16
VSS14
DQ11
DQ10
VSS12
DQS1
DQS1*
DQ9
DQ8
VSS8
DQ3
DQ2
VSS6
DQS0
DQS0*
VSS4
VSS1
VREF
DQ0
DQ1
DQ34
DQ40
DQ42
DQ43
DQS6
DQ51
DQ57
KEY
VSS9
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
The 4.7uF and 1.0uF caps can be changed to 5x 2.2uF caps,
Resistor prevents pwr-gnd short
NC
when they get cheaper.
516-0135
NC
NC
NC
BOM options provided by this page:
- =I2C_MEM_SDA
Signal aliases required by this page:
- =PP1V8_S3_MEM
(See Capell Valley pg 47)to drive MCH and DIMM connectors.
DDR2 Bypass Caps
- =I2C_MEM_SCL
by another page.The reference voltage must be providedNOTE: This page does not supply VREF.
(NONE)
Power aliases required by this page:
- =PPSPD_S0_MEM (2.5V - 3.3V)
Page Notes
Yellow uses 10K divider and TLV2463
DDR2 VREF (FOR CONNECTOR B)One 0.1uF per connector
NCNC
(For return current)
ADDR=0xA4(WR)/0xA5(RD)
DIP DIMM CONN
20%6.3VCERM
C32091
2
4.7uF
603
C32001
2402CERM10V20%0.1UF
R32011
2402MF-LF1/16W1%1K
R32021
2402MF-LF1/16W
1K1%
C32101
2402
20%10VCERM
0.1UF
C32201
2
2.2UF20%4VX5R402
C32311
2402-LF
6.3VCERM
2.2UF20%
C32301
2402-LF
2.2UF
CERM6.3V20%
C32321
2402-LF
6.3V20%2.2UF
CERM
C32211
2402CERM10V20%0.1UF
C32221
2 X5R402
2.2UF20%4V
R32001
2 402MF-LF1/16W5%10K
J3201
102101
105
9089
10099
9897
94
92
93
91
107
106
85
113
30
32
164
166
79
10
26
52
67
130
147
170
185
5
7
35
37
20
22
36
38
43
45
55
57
17
44
46
56
58
61
63
73
75
62
64
19
74
76
123
125
135
137
124
126
134
136
4
141
143
151
153
140
142
152
154
157
159
6
173
175
158
160
174
176
179
181
189
191
14
180
182
192
194
16
23
25
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
201
202
116
86
84
80
119
115
50
69
83
120
163
114
108
110
198
200
197
195
81 82
117 118
87 88
95 96
103 104
111 112
199
1 2
3
27 28
33 34
39 40
41 42
47 48
8
53 54
59 60
65 66
71 72
77 78
121 122
127 128
132
133
138
139
144
9
145
149 150
155 156
161 162
165
168
171
12
172
177 178
183 184
187
190
193
196
15
18
21
24
109
OMIT
DDR2-SODIMM-STD
F-RT-TH3
CRITICAL
C32111
2
0.1UF
CERM
20%
402
10V
C32121
2 10V20%0.1UF
402CERM
C32131
2
0.1UF
CERM10V20%
402
C32141
2
0.1UF20%
CERM402
10V
C32151
2
0.1UF20%
CERM10V
402
C32161
2402-LFCERM6.3V2.2UF20%
C32171
2402-LF
6.3VCERM
2.2UF20%
R32031 2
402
10K5%
1/16WMF-LF
051-7455
SYNC_DATE=06/20/2005SYNC_MASTER=MEMORY
01
31 76
DDR2 SO-DIMM Connector B
=PP1V8_S3_MEM
MEM_B_CAS_L
=PP1V8_S3_MEM
MEM_B_WE_LMEM_B_BS<0>
MEM_B_DQ<18>MEM_B_DQ<22>
MEM_B_DQ<8>
MEM_B_DQS_N<1>
MEM_B_DQ<12>
=PPSPD_S0_MEM
MEM_B_DQS_N<5>
MEM_B_DQ<53>
MEM_B_DQS_P<5>
MEM_B_DQ<54>
MEM_B_DQ<59>MEM_B_DQ<58>
MEM_B_DQS_N<7>
MEM_B_DQ<62>MEM_B_DQ<60>
MEM_B_DQ<51>
MEM_B_DQS_P<7>
MEM_B_SA0
MEM_B_DQ<29>
MEM_B_DM<5>
MEM_B_DQ<40>
MEM_B_DQ<34>
MEM_B_DM<4>
MEM_B_DQ<33>
MEM_B_RAS_L
MEM_B_DQS_P<2>
MEM_B_DQ<47>
MEM_B_DQ<39>
MEM_B_DQ<32>
MEM_B_A<8>
MEM_B_A<12>
MEM_CKE<3>
MEM_B_DQ<31>
MEM_B_DM<3>
MEM_B_DQ<35>
MEM_B_DQ<45>
MEM_B_DQ<4>MEM_B_DQ<1>
MEM_VREF_B
MEM_B_DQ<9>
DIMM_OVERTEMPB_L
MEM_B_A<4>
MEM_B_DQ<42>MEM_B_DQ<43>
MEM_B_A<14>
MEM_B_DQ<52>
MEM_B_DM<2>
MEM_B_DQ<28>
MEM_B_DQS_N<3>
MEM_B_DQ<26>
=PPSPD_S0_MEM
MEM_B_DQ<27>
=PP1V8_S3M_MEM_NB
MEM_VREF_BVOLTAGE=0.9V
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=0.25 mm
MEM_B_A<2>
=I2C_SODIMMB_SCL=I2C_SODIMMB_SDA
MEM_B_DQ<63>MEM_B_DQ<61>
MEM_B_DM<7>
MEM_B_DQ<56>
MEM_B_DQ<50>
MEM_B_DQS_N<6>
MEM_B_DQ<48>
MEM_B_DQS_P<4>MEM_B_DQS_N<4>
MEM_B_DQ<38>
MEM_ODT<3>
MEM_CS_L<3>
MEM_B_A<10>
MEM_B_A<1>
MEM_B_A<9>
MEM_B_BS<2>
MEM_B_DQ<30>
MEM_B_DQ<44>
MEM_B_DQS_P<6>
MEM_B_DQ<55>
MEM_B_DQ<57>
=GND_CHASSIS_DIPDIMM_CENTER
MEM_B_DQ<17>
MEM_B_DQS_P<1>
MEM_B_DQ<20>
MEM_B_DM<0>
MEM_B_DQ<15>
MEM_B_DM<1>
MEM_CLK_P<3>MEM_CLK_N<3>
MEM_B_DQ<14>
MEM_B_DQ<21>
MEM_B_DQ<19>
MEM_B_DQ<25>
MEM_B_DQS_P<3>
MEM_B_DQ<24>
MEM_B_DQS_N<2>
MEM_B_BS<1>
MEM_CS_L<2>
MEM_B_DQ<10>
MEM_B_DQ<13>
MEM_B_DQS_P<0>MEM_B_DQS_N<0>
MEM_B_A<15>
MEM_B_DQ<23>
MEM_B_DQ<16>
MEM_CKE<4>
MEM_B_A<11>MEM_B_A<7>MEM_B_A<6>
MEM_ODT<2>MEM_B_A<13>
MEM_B_DQ<36>MEM_B_DQ<37>
MEM_B_DQ<49>
MEM_B_DM<6>
=GND_CHASSIS_DIPDIMM_RIGHT
MEM_B_DQ<11>
MEM_B_DQ<2>MEM_B_DQ<6>
MEM_B_DQ<0>
=PP1V8_S3_MEM
MEM_B_DQ<5>
MEM_B_A<5>MEM_B_A<3>
MEM_B_A<0>
MEM_B_DQ<41>MEM_B_DQ<46>
MEM_CLK_P<4>MEM_CLK_N<4>
J3201_SA1MEM_B_SA0
MEM_B_DQ<7>MEM_B_DQ<3>
31D6
31D4 31D6
31D4
31B2
30D2
31B2
30D6
30D6
20C8
30D6
30D4
72B3
30D4
72B3
72B3
31A7
72B3
72B3
72B3
72B3
72B3
72B3
31A3
17D7
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
30D4
72B3
72B3
72B3
30B2
32A6
30B2
32A6
32A6
72B3
72B3
72B3
72A3
72B3
30A7
72A3
72B3
72A3
72B3
72B3
72B3
72A3
72B3
72B3
72B3
72A3
72B3
72B3
72B3
72B3
72B3
72B3
32A6
72A3
72B3
72B3
72B3
32B5
32A5
32D6
72B3
72B3
72B3
72B3
72B3
72B3
72B3
32B5
72B3
72B3
32A5
72B3
72B3
72B3
72A3
72B3
30A7
72B3
15D2
32B5
72B3
72B3
72A3
72B3
72B3
72A3
72B3
72A3
72A3
72B3
32D6
32D6
32B5
32B5
32B5
32A6
72B3
72B3
72A3
72B3
72B3
72B3
72A3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72B3
72A3
72B3
72A3
32A6
32D6
72B3
72B3
72A3
72A3
72B3
72B3
32D5
32A5
32B5
32B5
32D6
32A5
72B3
72B3
72B3
72A3
72B3
72B3
72B3
72B3
30B2
72B3
32B5
32B5
32B5
72B3
72B3
72B3
72B3
72B3
72B3
7B4
16D1
7B4
16B1
16D1
16C4
16C4
16C4
16C1
16C4
7C4
16C1
16B4
16C1
16B4
16B4
16B4
16C1
16A4
16A4
16B4
16C1
31A4
16C4
16C1
16B4
16B4
16C1
16C4
16B1
16C1
16B4
16B4
16C4
16B1
16B1
15D3
16C4
16C1
16B4
16B4
16D4
16D4
31D1
16C4
8B1
16B1
16B4
16B4
15C6
16B4
16C1
16C4
16C1
16C4
7C4
16C4
7A4
31D7
16B1
47C6
47C6
16A4
16A4
16C1
16B4
16B4
16C1
16B4
16C1
16C1
16B4
15C3
15C3
16B1
16C1
16B1
16D1
16C4
16B4
16C1
16B4
16B4
16C4
16C1
16C4
16D1
16C4
16D1
15D3
15D3
16C4
16C4
16C4
16C4
16C1
16C4
16C1
16D1
15D3
16C4
16C4
16C1
16C1
8B4
16C4
16C4
15D3
16B1
16B1
16B1
15C3
16B1
16B4
16B4
16B4
16C1
16C4
16D4
16D4
16D4
7B4
16D4
16B1
16B1
16C1
16B4
16B4
15D3
15D3
31A3
16D4
16D4
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
BOMOPTION shown at the top of each group applies to every part below it
TO PP0V9_S0_MEM_TERM LAYOUT NOTE:PLACE ONE CAP CLOSE TO EVERY TWO PULLUP RESISTORS TERMINATED
One cap for each side of every RPAK, one cap for every two discrete resistors
R3301 1 2561/16WMF-LF4025%
R3309 1 21/16W
56402MF-LF5%
R3311 1 256402MF-LF5% 1/16W
R3325 1 24025% 1/16W
56MF-LF
R3335 1 25% 402
561/16WMF-LF
0
2
1
16D1 31B6 72B3
16B1 31B4 72B3
16D1 31B4 31B6 31C6 72B3
16B1 31B6 72B3
RP3300 3 656SM-LF1/16W5%
RP3300 4 556SM-LF5% 1/16W
RP3300 1 8SM-LF
565% 1/16W
RP3300 2 75% SM-LF
561/16W
RP3301 2 756SM-LF1/16W5%
RP3301 1 81/16WSM-LF
565%
RP3301 4 55%
56SM-LF1/16W
RP3301 3 656SM-LF5% 1/16W
RP3302 4 5SM-LF
561/16W5%
RP3302 1 8SM-LF1/16W
565%
RP3302 3 65% 1/16W
56SM-LF
RP3302 2 75% 1/16W
56SM-LF
RP3303 1 85% SM-LF
561/16W
RP3303 2 7565% SM-LF1/16W
RP3303 3 65%
561/16WSM-LF
RP3303 4 5SM-LF5%
561/16W
RP3304 1 8SM-LF5%
561/16W
RP3304 3 6561/16W5% SM-LF
RP3304 4 5565% SM-LF1/16W
RP3305 1 8SM-LF5% 1/16W
56
RP3305 2 75% SM-LF
561/16W
RP3305 3 6565% 1/16WSM-LF
RP3305 4 5565% SM-LF1/16W
RP3306 2 7561/16W5% SM-LF
RP3306 3 65%
56SM-LF1/16W
RP3307 4 5SM-LF5%
561/16W
RP3307 3 656SM-LF5% 1/16W
RP3307 2 7SM-LF
565% 1/16W
RP3307 1 856SM-LF5% 1/16W
RP3308 4 556SM-LF5% 1/16W
RP3308 3 6SM-LF
565% 1/16W
RP3308 2 7SM-LF
565% 1/16W
RP3308 1 856SM-LF5% 1/16W
RP3309 1 8561/16W5% SM-LF
RP3309 2 7565% SM-LF1/16W
RP3309 3 656SM-LF5% 1/16W
RP3309 4 5SM-LF
565% 1/16W
RP3310 3 6SM-LF
561/16W5%
RP3310 2 7SM-LF5% 1/16W
56
RP3310 1 8565% SM-LF1/16W
RP3310 4 5565% SM-LF1/16W
RP3311 1 8SM-LF5%
561/16W
RP3311 2 7SM-LF
561/16W5%
RP3311 4 55%
561/16WSM-LF
RP3306 4 556SM-LF5% 1/16W
RP3311 3 6SM-LF
561/16W5%
16C1 31B4 72B3
16B1 31B6 72B3
16B1 31B4 72B3
16B1 31B6 72B3
16B1 31B4 72B3
16B1 31B6 72B3
16B1 31C4 72B3
16B1 31C4 72B3
16B1 31C6 72B3
16B1 31C6 72B3
16C1 31B6 72B3
16B1 31C4 72B3
16B1 31C6 72B3
16B1 31B4 72B3
C33001
2402
20%10VCERM
0.1UFC33011
2
0.1UF
CERM10V20%
402
C33021
2402
20%10VCERM
0.1UFC33031
2
0.1UF
CERM10V20%
402
C33041
2402
20%10VCERM
0.1UFC33051
2
0.1UF
CERM10V20%
402
C33061
2402
20%10VCERM
0.1UFC33071
2402
0.1UF
CERM10V20%
C33081
210V
402CERM
0.1UF20%
C33091
2
0.1UF
CERM10V20%
402
C33101
2402
20%10VCERM
0.1UFC33111
2
0.1UF
CERM10V20%
402
C33121
220%0.1UF10VCERM402
C33131
2
0.1UF
CERM10V20%
402
C33141
2402
20%10V
0.1UF
CERM
C33151
2
0.1UF
CERM10V20%
402
C33161
2
0.1UF
402
20%10VCERM
C33171
2
0.1UF
CERM10V20%
402
C33181
2402
20%10VCERM
0.1UFC33191
2
0.1UF
CERM10V20%
402
C33201
2402
20%10VCERM
0.1UFC33211
2
0.1UF
CERM10V20%
402
C33221
2402
20%10VCERM
0.1UFC33231
2
0.1UF
CERM10V20%
402
C33241
2402
20%10VCERM
0.1UFC33251
2402
20%10VCERM
0.1UF
15D3 30C4 72D3
15D3 31C6 72B3
15D3 31C4 72B3
14RP3304 2 7
1/16W5%56
SM-LF
RP3306 1 8561/16W5% SM-LF
R3327 1 256MF-LF5% 1/16W 402
0
1
1
0
2
0
1
2
3
4
5
6
7
10
11
9
8
13
12
15C3 15D3 30B4 30B6 31B4 31B6 72B3 72D3
15D3 30C6 72D3
15C6 16B5 16C5 30B4 30B6 30C4 30C6 72D3
16D5 30B4 30B6 30C6 72D3
16B5 30B4 72D3
16D5 30B6 72D3
16B5 30B6 72D3
2
3
0
1
2
3
15C3 30B4 30B6 31B4 31B6 72B3 72D3
01
76
Memory Active Termination
32
051-7455
MEM_B_BS<2..0>
MEM_CS_L<3..0>
MEM_A_A<14..0>
MEM_ODT<3..0>
MEM_A_BS<2..0>
MEM_B_A<2>MEM_B_A<10>MEM_B_A<4>MEM_B_A<5>MEM_B_A<6>MEM_B_A<7>MEM_B_A<8>MEM_B_A<9>MEM_B_A<1>
=PP0V9_S3M_MEM_TERM
MEM_CKE<4>MEM_CKE<3>MEM_CKE<1>MEM_CKE<0>
MEM_B_A<0>MEM_B_A<3>
MEM_A_CAS_L
MEM_B_CAS_LMEM_B_WE_L
MEM_B_RAS_L
MEM_A_WE_L
MEM_A_RAS_L
MEM_B_A<11>MEM_B_A<12>
MEM_B_A<14>MEM_B_A<13>
7D7
OUT
D
SG
D
SG
D
SG
D
SG
IN
IN
OUT
OUT
IO
IO
IN
IN
OUT
IO
IO
IN
KEY
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
* Enclosure: 516S0406
ICH8 GPIO42
PLACE CAPS < 250 MILS FROM (U2100) SB
Plexi: 516S0363
CONNECT TO M35 MODULE
SB HAS INTERNAL 15K PULL-DOWNS
AIRPORT CONN
C34061
2
0.1UF
402
20%
CERM10V
C34081
2 CERM
0.1UF10V20%
402
C34071
2402
10V
0.1UF20%
CERM
R340312
NOSTUFF
5%8051/8W
0MF-LF
Q3402 6
2 1
SOT563SSM6N15FE
Q3402 3
5 4
SOT563SSM6N15FE
R3404
12
1/16W
MF-LF
402
100K
5%
R34051210K
5%1/16WMF-LF402
C34111
2
0.033UF16VX5R402
10%
Q3401
1
2
5
6
3
4
CRITICAL
SM-LFFDC638P
Q3403 6
2 1
SOT563SSM6N15FE
Q3403 3
5 4
SOT563SSM6N15FE
C3412
1 2
CERM
NOSTUFF
0.01UF
10%
16V402
R3406
12
100K
402
MF-LF
1/16W
5%
C34101
2 10VCERM402
20%0.1UF
C34091
2
10UF20%
X5R6.3V
603
C34001 2
10V4020.1UF
20%CERM
C34041
2
0.1UF
CERM10V20%
402
CK505_SRC_CLKREQ6_L
R34011 2
0MF-LF402
5%1/16W
R34021 2
0
402MF-LF
1/16W5%
J3400
53
54
1
10
11 12
13 14
15 16
17 18
19
2
20
21 22
23 24
25 26
27 28
29
3
30
31 32
33 34
35 36
37 38
39
4
40
41 42
43 44
45 46
47 48
49
5
50
51 52
6
7 8
9
AS0B22-S45N-7F
CRITICAL
F-ST-SM
C3401
1 2 0.1UF
10VCERM 40220%
C34051
2
0.1UF20%10V
402CERM
01
33 76
051-7455
PP3V3_S3_AP_AUX
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.2MM
=PP1V5_S0_AIRPORT
PM_WLAN_EN_L_SS
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.2MM
=PP3V3_S3_AIRPORT_AUX
AIRPORT_RST_L
=PP3V3_S0_AIRPORT
PCIE_E_D2R_P
PCIE_WAKE_L
PCIE_CLK100M_MINI_NPCIE_CLK100M_MINI_P
SMB_AIRPORT_CONN_CLKPCIE_E_R2D_NPCIE_E_R2D_P
PCIE_E_D2R_N
=USB2_AIRPORT_P
SMB_AIRPORT_CONN_DATA
=USB2_AIRPORT_N
=SMB_AIRPORT_CLK
=SMB_AIRPORT_DATAPCIE_E_R2D_C_P
PM_S4_STATE_L
PCIE_E_R2D_C_N
MAKE_BASE=TRUE
WOW_EN
MAKE_BASE=TRUEPCIE_E_R2D_C_P
PCIE_E_D2R_PMAKE_BASE=TRUE
=PP3V3_S5_AIRPORT_AUX
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N
PCIE_MINI_R2D_C_N
=PP3V3_S5_AIRPORT_AUX
PM_SLP_S3_L
PCIE_MINI_R2D_C_PPCIE_E_R2D_C_N
MAKE_BASE=TRUE
MAKE_BASE=TRUEPCIE_E_D2R_N
SB_GPIO42
PM_WLAN_EN_L
=PP3V3_S5_AIRPORT_AUX
SMC_ADAPTER_EN
WOW_EN
PM_WLAN_EN_L1
PM_WLAN_EN_L2
62B8
57C4
58B7
45B3
65C4
45A6
44D5
65A6
33D7
33D6
44C5
33D7
38C6
74C3
34B8
75A3
75B3
74B3
74C3
44C5
74C3
74C3
74C3
33D6
33C7
35C7
74C3
74B3
33C7
35C7
28B4
7B7
7A4
27D1
7D4
33B5
24C8
29B3
29C3
33B5
8C2
8C2
47C3
47C3 33B5
24D3
33B5
33C7
33B6
33B5
7C1
23C5
23D5
23C5
7C1
24D3
23C5
33B6
33C5
23C8
7C1
6C1
33B5
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
IN
IN
IN
OUT
OUT
IN
IN
THRML_PAD
VDDO_TTL1
VMAIN_AVLBL
SWITCH_VAUX
VAUX_AVLBL
LED_DUPLEX*
RSVD_43
RSVD_29
RSVD_25
RSVD_24
NC_64
CTRL12
NC_57
NC_52
NC_51
NC_32
RSET
SWITCH_VCC
AVDDH
AVDD0
AVDD3
VDDO_TTL3
LOM_DISABLE*
VDD0
VDD1
VDD3
VDD4
TX_P
CTRL18
TESTMODE
VDD2
VDD5
VDD7
CLKREQ*
WAKE*
PERST*
MDIP0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
XTALI
MDIN3
XTALO
REFCLKP
REFCLKN
RX_N
RX_P
SPI_DO
SPI_CLK
SPI_CS
VPD_DATA
VPD_CLK
TX_N
MDIN0
AVDD1
LED_LINK1000*
VDD6
VDDO_TTL2
VDDO_TTL0
LED_ACT*
LED_LINK10/100*
AVDD2
SPI_DI
ANALOGPCI EXPRESS
SPI
LED
TWSIMEDIA
MAIN CLK
TEST/RSVD
IN
OUT
OUT
E2
WC*
NC0NC1
VCC
VSS
SCL
SDA
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
DESCRIPTION REFERENCE DES BOM OPTIONQTYPART NUMBER CRITICAL
- =PP1V8R2V5_ENET_PHY
100 Mbps: 203 mA1000 Mbps: 426 mA 1000 Mbps: 290 mA
10 Mbps: 70 mA100 Mbps: 70 mA1000 Mbps: 80 mA
Yukon Ultra (1.8V)
No link: 0 mA10 Mbps: 30 mA
Yukon EC: Alias to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF & 1x 0.001uF capsYukon Ultra: Alias to GND
Yukon EC: Pin 42 should be NC (or TP) net.
100 Mbps: 4 mA10 Mbps: 4 mA
YUKON_ULTRA - Selects Yukon Ultra RSET.YUKON_EC - Selects Yukon EC RSET value.BOM options provided by this page:
- =ENET_CLKREQ_L (NC/TP for Yukon EC)Signal aliases required by this page:
No link: 4 mA
16pF
too small, make R3765 smallerIf characterization shows eye height is
- Use YUKON_EC and YUKON_ULTRA BOMOPTIONs to select stuffed part
NOTE: See bottom of page for
Yukon Ultra schematic support. instructions for dual Yukon EC /
on this page. Proper part numbers
- =ENET_VMAIN_AVLBL
must be called out elsewhere.
NOTE: Yukon IC and EEPROM are OMITted
(EC:2.5V)No link: 82 mA
1000 Mbps: 218 mA100 Mbps: 126 mA10 Mbps: 108 mA
Must be high in S0 state (can use PP3V3_S0 as input)
- =YUKON_EC_PP2V5_ENET
100 Mbps: 150 mA
Yukon EC
VPD ROM
NC
EC:AVDD 2.5V
NCNCNC
NCNC
NC
EC:CTRL25
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPD)
NCNCNCNC
NCNCNC
NC
(2.5V / GND)
(EC / Ultra)
- =PP1V2_ENET_PHY
Yukon Ultra
1000 Mbps: 150 mA
Yukon EC (2.5V)
No link: 60 mA
10 Mbps: 130 mA10 Mbps: 179 mA
- Connect =ENET_CLKREQ_L to clock generator via 0-ohm resistor (BOMOPTION: YUKON_ULTRA)
100 Mbps: 40 mA
1000 Mbps: 4 mA
Page Notes
NC
Yukon Ultra
No link: 130 mANo link: 171 mA
Yukon EC(2.5V / 1.8V)
- =PP3V3_ENET_PHYPower aliases required by this page:
EC:NO CONNECT
NC
- Use 0-ohm resistors or variable supply to provide 1.8V or 2.5V to =PP1V8R2V5_ENET_PHY- Alias =YUKON_EC_PP2V5_ENET to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF and 1x 0.001uF caps
To support Yukon EC and Ultra on the same board:
NC
C37511
2 CERM50V5%15PF
402
R37401
2
49.91%
SIGNAL_MODEL=EMPTY
1/16WMF-LF402
R37411
2
SIGNAL_MODEL=EMPTY
1/16WMF-LF
1%49.9
402
36B7 74B3
36B7 74B3
36C7 74B3
36C7 74B3
36B7 74B3
36C7 74B3
36C7 74B3
36C7 74B3
23C5
23C5
C37401
2
10%
402CERM50V
0.001UFC37421
2
10%
402CERM50V
0.001UFC37441
2
10%
402CERM50V
0.001UFC37461
2
10%
402CERM50V
0.001UF
R37421
2
SIGNAL_MODEL=EMPTY
1/16WMF-LF
49.91%
402
R37431
2
SIGNAL_MODEL=EMPTY
1/16WMF-LF
1%49.9
402
R37471
2
49.9
SIGNAL_MODEL=EMPTY
402MF-LF1/16W
1%
R37461
2
49.91%
SIGNAL_MODEL=EMPTY
1/16WMF-LF402
R37451
2
49.91%
SIGNAL_MODEL=EMPTY
1/16WMF-LF402
R37441
2
49.91%
SIGNAL_MODEL=EMPTY
1/16WMF-LF402
C3735 1 2
10% X5R0.1UF 16V 402
C3736 1 2
10% X5R0.1UF 16V 402
C3730 1 210% X5R0.1UF 16V 402
PLACEMENT_NOTE=Place C3730 close to southbridge.
C3731 1 2
PLACEMENT_NOTE=Place C3731 close to southbridge.
X5R10%0.1UF 16V 402
23C5
23C5
27C1
24C8 33C5
8C4 28A4
29B3
29B3
U3700
19
22
23
28
8
42
3
4
59
63
62
60
10
18
21
27
31
17
20
26
30
32
51
52
57
64
5
56
55
16
24
25
29
43
53
54
37
36
35
34
9
11
46
65
50
49
12
2 7 13
33
39
44
48
58
1 40
45
61
47
38
41
6
15
14
88E8058
CRITICAL
QFN8A3
R37651
2
YUKON_ULTRA
4.99K1%1/16WMF-LF402
C3720 1
2603
4.7UF20%6.3VCERM
C3710 1
220%6.3V
4.7UF
603CERM
C37011
2 X5R
10%0.1UF16V
402
C3700 1
2CERM6.3V20%
4.7UF
603
C37061
210%
402CERM50V
0.001UF
U3780
3
1
2
6
5
8
4
7
CRITICAL
OMIT
M24C08SO8
C37801
2
0.1UF10%
X5R16V
402
R37801
2
5%4.7K1/16WMF-LF402
R37811
2
5%4.7K1/16WMF-LF402
R37601
2
5%4.7K1/16WMF-LF402
L3720
1 2
FERR-120-OHM-1.5A
0402-LF
C37021
2 16V
0.1UF
X5R
10%
402
C37031
2 X5R
10%0.1UF16V
402
C37041
2 16V
0.1UF10%
X5R402
C37051
2 16V
0.1UF10%
X5R402
C37071
2402
10%
CERM50V
0.001UFC37081
2402
10%
CERM50V
0.001UF
C37111
2 16V
0.1UF10%
X5R402
C37121
2 X5R
10%0.1UF16V
402
C37131
2 X5R
10%0.1UF16V
402
C37141
2402
10%
CERM50V
0.001UFC37151
210%
402CERM50V
0.001UF
C37211
2 X5R
10%0.1UF16V
402
C37221
2 16V
0.1UF10%
X5R402
C37231
2 16V
0.1UF10%
X5R402
C37241
210%
402CERM50V
0.001UF
Y3750
24
13
CRITICAL
25.0000MSM-3.2X2.5MM
C3750 1
2CERM50V5%
15PF
402
Ethernet (Yukon)
76
01
SYNC_MASTER=USB SYNC_DATE=10/07/2006
34
051-7455
114S0285 1 YUKON_ECR3760RES,4.87K,1%,1/16W,0402,LF
ENET_MDI_N<2>
ENET_MDI_P<1>
ENET_RESET_L
PCIE_WAKE_L
PCIE_CLK100M_ENET_NPCIE_CLK100M_ENET_P
PCIE_ENET_R2D_NPCIE_ENET_R2D_P
PCIE_ENET_D2R_C_NPCIE_ENET_D2R_C_P
=YUKON_EC_PP2V5_ENET
PP1V8R2V5_ENET_PHY_AVDDMIN_LINE_WIDTH=0.4 mm
VOLTAGE=1.8VMIN_NECK_WIDTH=0.22 mm
=PP3V3_ENET_PHY
=PP1V2_ENET_PHY
=ENET_CLKREQ_L
=PP1V8R2V5_ENET_PHY
PCIE_ENET_D2R_P
YUKON_VPD_DATA
TP_YUKON_CTRL18TP_YUKON_CTRL12
YUKON_RSET
ENET_LOM_DIS_L
ENET_MDI0 ENET_MDI1 ENET_MDI2
YUKON_VPD_CLK
PCIE_ENET_D2R_N
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N=ENET_VMAIN_AVLBL
ENET_MDI_N<0>ENET_MDI_P<0>
ENET_MDI3
ENET_CLK25M_XTALO
ENET_MDI_P<3>ENET_MDI_N<3>
ENET_MDI_P<2>
ENET_MDI_N<1>
ENET_CLK25M_XTALI
8A4
7B5
7B5
7B3
GND
OUT1IN1
IN0
EN FB
PAD
OUT0
NC0
NC2
NC1
THRML
D
SG
D
SG
THRM_PAD NC
IN1
EN
IN2
OUT1
OUT2
NR/FB
GND
D
SG
D
SG
G
DS
IN
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
Vout = 1.2246V * (1 + R3821 / R3822)
1.2V ENET LDO
S0 on AC
0.085ohm1.8A
Powered by S3
"ENET" = "S0" || AC
1.9V ENET LDO
NC
High (3.3V)
Low (0V)
S5 on anything
High (3.3V)
Low (0V)
AC
Power
S0 on Battery
S3 on Battery
S3 on AC
High (3.3V)
High (3.3V)
Low (0V)
Yukon Power
N/A
Low (0V)
Power
Low (0V)
Low (0V)
N/A
PM_ENET_EN_L
N/AN/A
Name
Logic S0
High (3.3V) Power
Power
PM_SLP_S3_L
High (3.3V)
Low (0V)
High (3.3V)
High (3.3V)
PM_ENET_EN
No Power
ENET Enable Generation
Low (0V)
SMC_ADAPTER_EN
3.3V ENET FET
4.7UF20%6.3V
C3832
CERM603
2
1
R38301
2402
1%5.11K1/16WMF-LF
2
3.65K1%1/16WMF-LF402
1R3831
1 7
6
23
4510
89
11
SOP
MAX8516
U3830CRITICAL
6.3V4.7UF20%
C3831
CERM603
2
1C38301
2 CERM6.3V22UF
805
20%
Q3801 3
5 4
SSM6N15FESOT563Q3801 6
2 1
SOT563SSM6N15FE
U3820
8
6
12
7
5
34
9
LREG_TPS79501DRBSON
CRITICALR38211
2402MF-LF1/16W1%16.9K
R38221
2
1%1/16WMF-LF402
30.1K
C38231
2 6.3V10UF20%X5R603
C38201
2402CERM6.3V10%1UF
C38221
2CERM5%402
50V27PF
R38231
2
5%
402
15K
MF-LF1/16W
R38241
2
1/16W
402MF-LF
33K5%
R38321
2MF-LF1/16W
100K5%
402
Q3802 6
2 1
SSM6N15FESOT563
R38021
2
100K
MF-LF402
1/16W5%
Q3802 3
5 4
SSM6N15FESOT563
R38101 2
402
10K
1/16W5%
MF-LF
C3810
12
NOSTUFF
10%16V
0.01UF
CERM402
Q3810
3
1
2
NTR4101PSOT-23
CRITICAL
C38111
2 16V
0.033UF10%
X5R402
R38011
2402
1/16W5%100K
MF-LF
24D3 33C7 44C5 45A6 58B7 62B8
6C1 33C7 38C6 44D5 45B3 57C4
35
SYNC_DATE=10/07/2006SYNC_MASTER=USB
051-7455 01
76
Yukon Power Control
PP1V2_S3_FB
=PP1V8_ENET_P1V8ENETFET
SMC_ADAPTER_EN
P3V3ENET_SS
=PP3V3_S3_ENETPWRCTLPP3V3_ENET_FET
PP1V2_ENET_EN
PM_ENET_EN_L
PP3V3_ENET_FET
=PP1V9_ENET_REG
=PP1V2_ENET_REG
PP1V2_ENET_EN
PP1V9_S3_FB
=PP3V3_ENET_P3V3ENETFET
PP1V9_ENET_EN
=PP1V9_ENET_REG
=PP3V3_S5_SB
PM_SLP_S3_L
PM_ENET_EN_L
PM_ENET_WOL_EN_L
WOL_EN
26D8 24A8
35D4
35D4
35D1
35B2
24A3
7B4
7A4
7B6
35B3
35C6
7B6
7B4
7B6
35B2
7A4 7B4
7D1
35A3
24B3
SYM_VER-1
IO
IO
IO
IO
IO
IO
IO
IO
OUT
RX
TX
RX
TX
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
514-0443
PLACE ONE PAIR OF CAPS AT EACH PIN 3 AND 6 OF TRANSFORMERS
ETHERNET CONNECTOR
PLACE C3911 AND C3912ON EACH SIDE OF J3900
R39111 2
1/16W 402MF-LF5%0
R39101 2
05%1/16W MF-LF402
R39091 2
MF-LF0
5%1/16W 402R39081 2
4020
1/16W5% MF-LF
R39071 2 0
MF-LF1/16W 4025%R39061 2 0
4025%1/16W MF-LF
R39051 2 0
5%1/16W MF-LF402R39041 2
05%1/16W MF-LF402
OMITCRITICAL
F-RT-THRJ45-M71
8
7
6
5
4
3
2
1
9
10
J3900
C39021
2 X5R16V
402
10%0.1UF
C39001
2 X5R
10%0.1UF16V
402
C39011
210%16VX5R
0.1UF
402
C39031
2
0.1UF10%
X5R16V
402
R39001 2
MF-LF75
1% 1/16W 402
R39011 2
1/16W75
1% MF-LF402
R39021 2
1/16W MF-LF75
1% 402
R39031 2
1/16W 40275
1% MF-LF
C39041
2 CERM50V
0.001UF
402
10%
C39051
2
0.001UF50VCERM402
10%
C39061
2 CERM50V
0.001UF
402
10%
C39071
2 CERM50V
0.001UF
402
10%
C39101
2
CRITICAL
1000PF
CERM2KV10%
1206
C39111
2 CERM50V0.001UF
402
10%
C39121
2 CERM50V0.001UF
402
10%
L3950
1 2
FERR-120-OHM-1.5A
0402-LF
T39021
10
11
12
2
3
4
5
6 7
8
9TLA-6T213LF
CRITICAL
SM
T39011
10
11
12
2
3
4
5
6 7
8
9TLA-6T213LF
SM
CRITICAL
CONN,8P RJ-45 JACK,TH,BLACK,LF CRITICAL514-0475 J3900 FANCY1
CONN,8P RJ-45 JACK,TH,MG3,LF CRITICAL514-0443 NORMAL1 J3900
76
051-7455 01
36
SYNC_MASTER=USB SYNC_DATE=09/14/2006
ETHERNET CONNECTOR
=GND_CHASSIS_RJ45
=PP1V8_S0_YUKON
ENET_MDI_P<0>
ENET_MDI_N<0>
ENET_MDI_N<2>
ENET_MDI_P<3>
ENET_MDI_N<3>
ENET_MDI_R_P<0>
ENET_MDI_R_N<0>
ENET_CENTER_TAP<2>
ENET_CENTER_TAP<3>
ENET_MDI_P<1>
ENET_MDI_N<1>
ENET_CENTER_TAP<1>
ENET_MDI_R_P<3>
ENET_MDI_R_P<1>
ENET_MDI_R_N<3>
ENET_MDI_P<2>
ENET_MDI_R_N<2>
ENET_MDI_R_P<2>
ENET_MDI_R_N<1>
PP1V8_S0_YUKON_AVDD
ENET_CENTER_TAP<0>
MIN_NECK_WIDTH=0.25MMENET_BOB_SMITH_CAPMIN_LINE_WIDTH=0.6MM
ENET_MDI_TRAN_P<3>
ENET_MDI_TRAN_N<3>
ENET_MDI_TRAN_N<1>
ENET_MDI_TRAN_P<2>
ENET_MDI_TRAN_N<2>
ENET_MDI_TRAN_N<0>
ENET_MDI_TRAN_P<1>
ENET_MDI_TRAN_P<0>74B3
74B3
74B3
74B3
74B3
74B3
74B3
74B3
8C8
7B3
34B8
34B8
34B8
34B8
34B8
34B8
34B8
34B8
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IN
IN
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
MPCI_ACTN_323
TPB0_P
TPBIAS0
PCI_AD12
RESET*
TPBIAS2
PCI_RST*
PCI_INTA*
PCI_PME*
PCI_AD21
PCI_AD31
XO
XI
R1
R0
TPA0_N
TPA0_P
TPB0_N
TPBIAS1
TPA1_P
TPB1_P
TPA1_N
TPA2_P
TPA2_N
TPB2_P
TPB2_N
MODE_A
MODE_420
TEST0
TEST1
PTEST
SE
SM
VSS21
VSS22
VSS20
VSS18
VSS19
VSS16
VSS15
VSS17
VSS13
VSS14
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VSS0
VSSA0
VSSA1
VSSA3
VSSA4
VSSA2
VDDA4
VDDA5
VDDA3
VDDA2
VDDA1
VDDA0
VDD0
VDD2
VDD1
VDD3
VDD4
VDD7
VDD9
PCI_VIOS
PCI_AD0
PCI_AD2
PCI_AD4
PCI_AD5
PCI_AD3
PCI_AD6
PCI_AD9
PCI_AD10
PCI_AD8
PCI_AD11
PCI_AD14
PCI_AD15
PCI_AD13
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD23
PCI_AD22
PCI_AD25
PCI_AD28
PCI_AD26
PCI_AD29
PCI_AD30
PCI_CBE2*
PCI_CBE1*
PCI_CBE0*
PCI_CBE3*
PCI_PAR
PCI_FRAME*
PCI_IRDY*
PCI_TRDY*
PCI_DEVSEL*
PCI_STOP*
PCI_IDSEL
PCI_REQ*
PCI_GNT*
PCI_PERR*
PCI_SERR*
PCI_CLK
CLKRUN*
VDD5
PCI_AD27
PCI_AD24
VDD6
PCI_AD1
TPB1_N
PC0
PC2
CONTENDER
CARDBUSN
PCI_AD7
PC1
IO
IO
IO
IO
IO
IO
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
PAGE NOTES
PCI_CLK_FW - NEED TO REFERENCE TO ALIAS PAGE
FW_PC0 - FIREWIRE POWER CLASS IDENTIFIER
PCI_DEVSEL_L, PCI_STOP_L, PCI_PAR, PCI_PERR_L, PCI_SERR_L
CONNECT TO VDD FOR 3.3V OPERATION
PLACE R4032 VERY CLOSE TO SB
THIS IS FROM ICH-8
7/26/2005 - CONNECTED PIN E10 TO GND
5/19/2005 - FIRST REVISION OF PAGE6/21/2005 - CHANGED INT* TO INT_PIRQD_L (PER ARCHITECTURAL DEFINITION)
FW_A_TPA_P/N, FW_A_TPB_P/N, FW_A_TPBIAS - PORT 0 FIREWIRE DIFF PAIRS
6/20/2005 - BGA VERSION OF FW323-06 ADDED6/21/2005 - CHANGED PCI_ID TO AD19 (PER ARCHITECTURAL DEFINITION)6/22/2005 - ADDED 510K PULL-DOWN ON RST* AND REMOVED CONNECTION TO PLT_RST_L 6/22/2005 - REMOVED CONSTRAINT SETS AS THEY WILL BE MANAGED ON BOARD SIDE
INT_PIRQD_L - INTERRUPT TO SBPCI_PME_FW_L - DEDICATED PME FOR FIREWIRE (SB GPIO1)
PCI_RST_L - PCI RESET FROM SB
PCI_REQ3_L - PCI REQUEST TO SBPM_CLKRUN_L - CLOCK-RUN PCI PROTOCOL
INPUT/OUTPUT
FW_C_TPA_P/N, FW_C_TPB_P/N, FW_C_TPBIAS - PORT 2 FIREWIRE DIFF PAIRS
6/22/2005 - REMOVED C4421 - REDUNDANT
OUTPUT
PAGE HISTORY
NEED TO CHECK CRYSTAL LOAD CAPACITANCE
MODE FOR EXTERNAL LINK
FW_B_TPA_P/N, FW_B_TPB_P/N, FW_B_TPBIAS - PORT 1 FIREWIRE DIFF PAIRS
6/22/2005 - BRING OUT PC0 CONNECTION TO BE CONNECTED ON PORT PAGE197S0030 3.2MMX2.5MM
PLACE ONE CAP PER TWO PINS STARTING WITH C4016 ON VDDA0
PLACE ONE CAP PER TWO PINS STARTING WITH C4024 ON VDD0
0.001A DURING SLEEPMOBILE TURNS OFF CONTROLLER POWER DURING SLEEP
=PP3V3_S0_PCI - 3.3V POWER FOR PCI FIREWIRE (MOBILE: OFF DURING SLEEP)=PP3V3_S0_FW - 3.3V POWER FOR FIREWIRE (MOBILE: OFF DURING SLEEP)INPUT
6/22/2005 - CHANGED CLK,PME,DIFF PAIR NAMES TO BE RE-USE COMPLIANT
DUAL PORT DEVICES ARE POWER CLASS 4 (’100’)SINGLE PORT DEVICES ARE POWER CLASS 0 (’000’)
SPEC RECOMMENDS 2.49K
MANUFACTURING TEST PINS
6/21/2005 - CHANGED REQ/GNT TO REQ3/GNT3 (PER ARCHITECTURAL DEFINITION)
PCI_AD<0..31>,PCI_C_BE_L<0..3>,PCI_FRAME_L,PCI_IRDY_L,PCI_TRDY_L,
PCI_GNT3_L - PCI GRANT FROM SB
LOW = PCI OPERATIONLOW = NOT BUS MANAGER
C40161
2
10UFX5R603
20%6.3V
R40521
2
1%MF-LF1/16W2.1K
402
C40181
2402
20%10VCERM
0.1UF
C40291
240216VX5R10%0.1UF
C40251
240216V10%X5R
0.1UFC40171
240216V10%X5R
0.1UF
C40201
240216V10%X5R
0.1UF
R40001 2
MF-LF1/16W402
3905%
C40241
2
10UFX5R603
20%6.3V
L40001 2
600-OHM-300MA
0402
U4000
B1
D1
G12
M5B6
E10
E12F13F12
F10G10
L11M12M11N12M10N11M4N5N4M3
H10
M2N3K4M1K2J4K1J2J1H2
H12
H4H1
J13J12K13K10L12M13
K12M9L3L1
G2
N8
N6
E1
L2
D2
M6
N10
M8
F2
E2
F1
N9
M7
N7
G13
A4
B7
A6
B4
A3B3
C2C1
B9A9
B11A11
C12C11
A10B10
A12B12
D12D13
B8
D8
C13
G4N1N2K5K6K7L13
H13
A2
D10
A13
B13
A7A8D6
A1
B2
G1
G6
G7
G8
H6
H7
H8
J5
J9
J10
C3
K8
K9
N13
D4
E4
E5
F4
F6
F7
F8
E13E9
D9
D7
D5
A5
B5FW32306BGA
CRITICAL
R40201
2402
1/16WMF-LF
5%510K
R40321 2100
1%
MF-LF1/16W
402
C40221
2
0.1UFCERM10V20%
402
C40261
2402
20%10VCERM
0.1UFC40281
2
0.1UFCERM10V20%
402
C40301
2402
20%10VCERM
0.1UFC40321
2
0.1UFCERM10V20%
402
R40371
2402
475%
MF-LF1/16WR40351
2402
475%
MF-LF1/16W
R40341
2402
475%
MF-LF1/16W
R40331
2402
475%
MF-LF1/16W
R40361
2402
475%
MF-LF1/16W
R40311
24021/16WMF-LF
5%22
Y4003
2 4
1 3
SM-3.2X2.5MM24.576MHZ
CRITICAL
C4011 1
240250VCERM
15PF5%
C40121
240250VCERM
15PF5%
FIREWIRE CONTROLLERSYNC_DATE=08/30/2005
01
76
SYNC_MASTER=ENET
37
051-7455
PCI_AD<14>
PCI_AD<12>
PCI_AD<7>
PCI_AD<4>
=PP3V3_S3_PCI
FW_XO_R
FW_B_TPB_N
VOLTAGE=3.3VMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.2MM
PP3V3_S3_FW_AVDD
FW_C_TPB_NFW_C_TPB_PFW_C_TPA_NFW_C_TPA_P
FW_B_TPA_NFW_B_TPB_P
FW_B_TPA_P
FW_A_TPB_N
FW_A_TPA_PFW_A_TPA_N
FW_R0
FW_C_TPBIAS
PCI_AD<19>
PCI_PME_FW_LINT_PIRQD_L
PCI_CLK33M_FWPCI_SERR_L
PCI_FW_REQ_L
FW_PCI_RST_LPCI_RST_L
PCI_AD<31>PCI_C_BE_L<0>PCI_C_BE_L<1>PCI_C_BE_L<2>PCI_C_BE_L<3>PCI_PARPCI_FRAME_LPCI_IRDY_LPCI_TRDY_L
PCI_STOP_LPCI_DEVSEL_L
PCI_AD<20>PCI_AD<21>PCI_AD<22>PCI_AD<23>PCI_AD<24>
PCI_AD<26>PCI_AD<25>
PCI_AD<27>PCI_AD<28>PCI_AD<29>PCI_AD<30>
PCI_AD<2>PCI_AD<3>
PCI_AD<5>
PCI_AD<11>
PCI_AD<15>PCI_AD<16>PCI_AD<17>PCI_AD<18>
FW_A_TPBIAS
FW_A_TPB_P
PCI_AD<0>PCI_AD<1>
PCI_AD<6>
PCI_AD<8>PCI_AD<9>PCI_AD<10>
FW_PCI_IDSEL
PCI_FW_GNT_LPCI_PERR_L
PM_CLKRUN_L
FW_B_TPBIAS
FW_R1
FW_XO
FW_XI
FW_PWRON_RST_L
FW_PC0
FW_PTEST
PCI_AD<13>
FW_SE
FW_TEST0
FW_SM
FW_TEST1
=PP3V3_S3_FW
46B6
74C3
75B3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
44C5
74D3
74D3
74D3
74D3
74D3
24C5
23A8
29B3
23A6
23B6
74D3
74D3
74D3
74D3
74D3
74D3
23A6
23A6
23A6
23A6
23A6
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
74D3
23A6
24C8
74D3
23A8
23B8
23B8
23B8
7A4
8D2
8D2
8D2
8D2
8D2
8D2
8D2
8D2
38B6
38B6
38B6
8D2
23A8
24A5
23A4
29A5
23A4
23A4
23A6
23A8
23B6
23B6
23B6
23B6
23A6
23A4
23A4
23A4
23A4
23A4
23A8
23A8
23A8
23A8
23A8
23A8
23A8
23A8
23A8
23A8
23A8
23B8
23B8
23B8
23B8
23A8
23A8
23A8
23A8
38C6
38B6
23B8
23B8
23B8
23B8
23B8
23B8
23B5
23A4
6C2
8D2
38C8
23B8
7A4
D
SG
D
SG
NC
V-
V+-
+
NC
IO
IO
IO
IO
IO
OUT
TPO#
TPI
TPO
TPI#
VGND
VP
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)TABLE_5_ITEM
TABLE_5_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
Cable Power
Page Notes
"Snapback" & "Late VG" Protection
(TPB-)
(TPB+)
(TPA-)
(TPA+)
1394APORT 0
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A 0.5V DROP
LATE-VG DETECTION CIRCUIT
FireWire Design Guide (FWDG 0.6, 5/14/03)1394b implementation based on Apple
7/26/05 - UPDATED SIGNAL NAMES FOR FW PORT POWER ENABLE
7/26/05 - SWITCHED TO 514-0124 FOR PRE-PROTO CONNECTOR
6/22/05 - CHANGED DIFF PAIR NAMES TO MATCH REUSE
PAGE HISTORY
OUTPUT:
FW_TPA0_P/N,FW_TPB0_P/N,FW_TPBIAS0 - FIREWIRE DIFF PAIRS
=FWPWR_PWRON - ADDITIONAL POWER CONTROL
INPUT/OUTPUT:
7/26/05 - CHANGED FL4590 TO 1.1A VERSION7/26/05 - REMOVED R4520 - IT HASN’T BEEN STUFFED FOR MANY PRODUCTS
7/26/05 - CHANGED CONNECTOR PORT NAMING TO PORT07/26/05 - UPDATED LATE-VG POWER RAIL CIRCUIT FROM M1
6/22/05 - REMOVED CONSTRAINTS BECAUSE USING ALLEGRO CONST MANAGER 6/22/05 - CONNECTED FW_PC0 FOR SINGLE PORT
7/26/05 - REMOVED ETHERNET LOW-POWER MODE CIRCUIT
1 FOR DUAL PORT
0 FOR SINGLE PORT
5/19/05 - INITIAL REVISION
(PPFW_PORT0_VP)
(GND_FW_PORT0_VGND)
[LATE VG NOTES]
PLACEHOLDER FOR SMALL PACKAGE DIODE
PORT POWER CLASS
machine AC Adapter is plugged
NC
Enables port power whenever
INPUT:
FW_PC0 - POWER CLASS IDENTIFIER (SINGLE PORT - TIE LOW)
or system at run state with battery only
=GND_CHASSIS_FW_PORT0 - CHASSIS GROUND
=PP3V3_S5_FW - DIGITAL POWER
=PPBUS_FW - PORT POWER
514-0456
C43011
2
220PF
402
5%
CERM25V
C4323 1
2
0.01UFCERM402
16V10%
C43551
2 CERM-X5R6.3V10%0.33UF
402
R43561
2MF-LF
2.0M
402
1/16W5%
C43541
2
0.1UF10%X5R16V
402
R43521
2
1%1/16W
10K
MF-LF402
R43511
2
1/16W5%10K
MF-LF402
R43541 2200K
1%1/16WMF-LF402
R43531
2
80.6K1/16W1%
MF-LF402
C43531
2
100PFCERM50V5%
402
D4350
13
CRITICAL
MMBZ5227BSOT23
C43521
2402
0.001UF50VCERM
NO STUFF
10%
R43501 2
402
1/16WMF-LF
5%
330
C43001
2 CERM-X5R402
6.3V10%0.33UF
Q4392 6
2 1
SOT563SSM6N15FE
Q4392 3
5 4
SOT563SSM6N15FE
FL4320
1
2
3
4 5
6
7
8
CRITICAL
SMTCM2010-100-4P
D43511 2
SOD-723
1SS418
U43504
6
3
1
5
2
CRITICAL
SC70TLV7211
CRITICALD4391
1
3
5
4
2
HN2D01JEFSOT665
C4325 1
2402
16VCERM
0.01UF10%
L4310
1 2
FERR-250-OHM
SM
C43101
210%
CERM50V
0.001UF
402
D4320
1
2
6
CRITICAL
SOT-363BAV99DW-X-F
D4321
4
5
3
CRITICALBAV99DW-X-F
SOT-363
D4320
4
5
3
CRITICAL
SOT-363BAV99DW-X-F
D4321
1
2
6
CRITICAL
SOT-363BAV99DW-X-F
FL4390
1 2
CRITICAL
MINISMDC
1.1A-24V
R43911
2402
3.3K5%
1/16WMF-LF
C43901
2402X7R25V10%0.01UF
R43901
2402
4.7K5%
MF-LF1/16W
R43011
2MF-LF402
56.21/16W1%
R43951
2 402
470K5%
MF-LF1/16W
R43941 210K
5%
MF-LF1/16W
402
R43001
2
56.21/16WMF-LF402
1%
F-RT-TH3
4
6
5
3
2
1
7 8
1394A
CRITICALOMIT
J4300
C4320 1
2
0.01UFCERM16V
402
10%
Q4390
1
2
5
6
3
4
CRITICAL
SM-LFFDC638P
C43241
2603-1
50VX7R10%0.01UFR43041
2
4.99K
402
1/16W1%
MF-LF
D43901 2
CRITICAL
SM
CRS08
R43021
2402
56.21%1/16WMF-LF
R43031
2
56.21%1/16WMF-LF402
C4322 1
2
0.01UF
402
10%CERM16V
C4321 1
216V
402
10%0.01UF
CERM
514-0456 NORMALCRITICALJ4300CONN,6P 1394A RCPT,MIDPLANE,MG3,LF1
514-0476 FANCYCRITICALJ4300CONN,6P 1394A RCPT,MIDPLANE,BLACK,LF1
051-7455
SYNC_DATE=07/17/2006
FIREWIRE PORTSYNC_MASTER=GPU
7638
01
VOLTAGE=19VPPFW_SWITCHMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
PPFW_PORT0_VP_FMIN_LINE_WIDTH=0.5MMMIN_NECK_WIDTH=0.25MM
VOLTAGE=16.5V
MIN_LINE_WIDTH=0.5MMVOLTAGE=16.5VPPFW_PORT0_VP
MIN_NECK_WIDTH=0.25MM
FW_PORT0_TPA_P_FLFW_PORT0_TPA_N_FL
=PPBUS_S5_FWPWRSW
FWPWR_EN_LMIN_LINE_WIDTH=0.15MMMIN_NECK_WIDTH=0.15MM
FWLATEVG_3V_REF
PP2V4_FWLATEVG
PP2V4_FWLATEVG_RC
FW_A_TPB_N
FW_PORTPWR_EN
FW_A_TPA_PFW_A_TPA_NFW_A_TPB_P
FW_PORT0_TPB
FW_PORT0_TPA_N
FWPWR_EN_AND
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.35MMVOLTAGE=3.3VPP2V4_FWLATEVG=PP3V3_S5_FWLATEVG
FW_PC0
FW_PORTPWR_EN
=GND_CHASSIS_FW_UPPER
=GND_CHASSIS_FW_DOWN
FW_PORT0_TPB_N_FL
LATEVG_EVENT_L
FW_PORT0_TPB_P_FL
FW_PORT0_TPB_N
SMC_ADAPTER_EN FWPWR_ACIN
FWPWR_EN=PP3V3_S0_FW
FW_PORT0_TPB_P
FW_PORT0_TPA_P
FW_A_TPBIAS
=PP3V3_S5_FWLATEVG
FWPWR_EN_L_DIVMIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.15MM
PPBUS_S5_FWPWRSW_F
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MMVOLTAGE=18.5V
57C4 45B3 44D5 35C7
38A6
37A3
33C7
38A8
6B2
7B1
38A7
37B3
38C5
37B3
37B3
37B3
38C5 7D1
38A4
8A6
8C8
6C1
7D4
37B3
7D1
OUT
OUT
OUT
D
SG
D
SG
Y
B
A
S
G
D
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
ICH8 GPIO54
ODD_PWR_EN_L is OD and core wellODD detect need less than 100ms include OS latency
This signal has integrated series resistor and pull down in ICH8M
NC
PER ATA7 SPEC
NC
NC
NC
NC
NC
Indicates disk presence, to SMC
NC
NCNC
Per ATA Spec
CORE RAIL 5V
ICH8 GPIO5
on SB page.both pull up resistors
BLEED CIRCUIT TO DISCHARGE ODD POWER RAIL WHEN ODD IS DISABLED.
516S0339
PER ATA SPEC
R44511
2
4.7K1/16W5%
MF-LF402
C4404 1
25%
CERM50V
402
10PF
NOSTUFF
R44591
2402
1/16W5%6.2K
MF-LF
R44581
2
05%
MF-LF1/16W
402
R44241
2
10K
NOSTUFF
402MF-LF
5%1/16W
R44531
2
33K5%
MF-LF1/16W
402
C44761 2
402X5R16V10%
0.1UF
NOSTUFF
R44651
2MF-LF
5%6.2K1/16W
402
R44761
2MF-LF1/16W
402
5%10K
J440151
52
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
6
78
9
CRITICAL
M-ST-SM5-1775184-0
C44751
210%CERM-X5R402
0.47UF6.3V
R44251 2
5%1/16WMF-LF
10K
402
Q4475 6
2 1
SSM6N15FESOT563
Q4475 3
5 4
SOT563SSM6N15FE
R44201
2
1/16W5%
MF-LF402
100K
R44771 2
1/16W5%
330
402MF-LF
R44011 2
1/16WMF-LF402
5%
0
ODD_PWR_CORE
R44021 2
ODD_PWR_RESUME
0
1/16W
402MF-LF
5%
R44601
2402MF-LF
5%1/16W
100K
U4401
3
2
1
4
5SC70MC74VHC1G09
CRITICAL
Q4410
1
2
5
6
3
4
CRITICAL
FDC606PSOT-6
Q44202
6
1
MMDT3904XFSOT-363-LF
R44611 2
402
24.9K1%
1/16WMF-LF
R44621
2
1/16W5%
MF-LF
4.7
402
C44771
210%X5R16V0.1UF
402
051-7455
PATA CONNECTOR
7639
01
ODD_PWR_EN_L_B
=PP3V3_S0_SB
IDE_PDD<14>IDE_PDD<15>
SMC_ODD_DETECT
IDE_PDCS3_L
IDE_PDDACK_L
IDE_PDD<12>
=PP3V3_S0_PATA
IDE_PDA<2>
IDE_CSEL_PD
IDE_PDD<8>
IDE_PDCS1_LIDE_PDA<0>IDE_PDA<1>
IDE_PDIOW_L
IDE_PDD<0> IDE_PDDREQIDE_PDIOR_L
IDE_PDD<13>
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.35MM
VOLTAGE=5V
PP5V_S0_IDE_PATA
IDE_PDD<3>
IDE_PDD<1>
IDE_PDIORDY
SB_GPIO40
ODD_PWR_EN_SLOW_START
ODD_PWR_EN_L
=PP5V_S0_IDE_RESET
ODD_RST_5VTOL_LODD_RST_BUF_L
ODD_PWR_EN_L_R
=PP5V_S0_IDE_PATA
ODD_POWER_DISCHARGE
ODD_PWR_EN_SLOW_START_L
IDE_PDD<2>
IDE_PDD<4>IDE_PDD<5>IDE_PDD<6>IDE_PDD<7>
IDE_PDD<11>IDE_PDD<10>IDE_PDD<9>
IDE_IRQ14
ODD_PWR_EN_SLOW_START_L_R
=PP5V_S5_PATA
ODD_PWR_EN_SLOW_START_R
ODD_RST_BUF_L
=PP5V_S0_IDE_PATA
ODD_PWR_EN_L_R
26D8
73D3
73D3
73D3
73D3
73D3
73D3
73D3
73D3
73D3
73D3
73D3
73D3 73D3
73D3
73D3 73D3
73D3
73D3
23A6
73D3
73D3
73D3
73D3
73D3
73D3
73D3
73D3
73D3
73D3
7D4
22B4
22B4
22B4
22B4
22B4
7D4
22B4
22B4
22B4
22B4
22B4
22B4
22C4 22A4
22B4
22B4 22B4
22C4
22A4
23C8
23A4
7A7
23B6
39C5 39C7
39C4
22B4
22B4
22B4
22B4
22B4
22B4
22B4
22B4
22B4
7C1
39A7
39A5
39A6
OUT
IN
OUT
OUT
IN
OUT
SYM_VER-1
SYM_VER-1
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
SATA CONNECTOR
518S0390
NC
PLACE L4502 NEAR SB
PLACE R4522 AND C4522 NEAR J4501
SATA DIFF PAIR GND VIAS
(TO IR RECEIVER)
NCNCNC
PLACE L4501 NEAR J4501
PLACE R4550 AND C4550 NEAR J4501
SYSTEM (SLEEP) LED FILTER
VALUE=3900PF IN REFERENCE SCHEM
PLACE NEAR ICH8 PIN
CAPS TO BE SAME DISTANCEFROM SB WITHIN EACH PAIR
GV45081
HOLE-VIA-P5RP25
GV45061
HOLE-VIA-P5RP25
GV45011
HOLE-VIA-P5RP25
GV45031
HOLE-VIA-P5RP25
GV45051
HOLE-VIA-P5RP25
GV45071
HOLE-VIA-P5RP25
GV45021
HOLE-VIA-P5RP25
GV45041
HOLE-VIA-P5RP25
0
R45011
2402MF-LF1/16W1%24.9
0
L4501
1
2 3
4
CRITICAL
1210-4SM190-OHM-100MA
C45221
2 16VCERM402
0.01UF10%
R45501 2
402
1005%
MF-LF1/16W
C45501
2
4.7UF20%6.3VCERM603
L4502
1
2 3
4
CRITICAL
1210-4SM190-OHM-100MAC4500
1 2
4020.0047UF
R45221 2
402
1/16WMF-LF
5%
10
C45021 2
4020.0047UF
C45011 2
0.0047UF402
C45031 2
4020.0047UF
C45211
2
NOSTUFF
603X5R6.3V20%10UF
C45201
2
NOSTUFF
0.1UFX5R40216V10%
J450120
21
1
10
11
12
13
14
15
16
17
18
19
2
3
4
5
6
7
8
9
20247-019E
CRITICAL
F-ST-SM
40 76
01
SATA CONNECTOR
051-7455
GND_CHASSIS_SATA
PP5V_S3_SYSLED_F
SYS_LED_ANODE_L
IR_RX_OUT
SATA_A_D2R_C_P
SATA_A_R2D_N
SATA_A_D2R_C_N
SATA_A_R2D_P
=PP5V_S0_SATA
SATA_A_D2R_F_P
SATA_A_R2D_F_P
SATA_A_D2R_P
SATA_A_D2R_N
SYS_LED_ANODE
SATA_RBIAS_PNMAKE_BASE=TRUE SATA_RBIAS_P
SATA_RBIAS_N
SATA_A_R2D_F_N
=PP5V_S3_SYSLED
SATA_A_R2D_C_P
SATA_A_R2D_C_N
SATA_A_D2R_F_N
73D3
73D3
45A3
22A6
22B6
45A4
73D3
73D3
8C7
43C8
73D3
73D3
73D3
73D3
7A7
22B6
22B6
6B2
7A4
22B6
22B6
SYM_VER-1
SYM_VER-1
GND
D+
D-
VBUS
GND
D+
D-
VBUS
EN1*
OC1*
IN OUT1
GND TPAD
OUT2
OC2*
EN2*
OE* SEL
GND
D+A
D-B
D+
VCC
D-A
D+B
D-
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
USB 2.0 CONNECTORS
SEL=1 CHOOSE USB
ROUTE USB DATA LINES AS DIFFERENTIAL PAIRSPLACE L4600 NEAR J4600
SEL=0 CHOOSE SMC
ROUTE USB DATA LINES AS DIFFERENTIAL PAIRS
L4601 Monitor SMT for tombstone
LAYOUT NOTE:C4606,C4607 ARE EMC BY-PASS CAPS FOR J4601
LAYOUT NOTE:C4602,C4603 ARE EMC BY-PASS CAPS FOR J4600
PLACE L4601 NEAR J4601
L4600 Monitor SMT for tombstone
PLACE C4675 NEAR U4675
514-0457
514-0457
41
L460190-OHM-100MA
TCM1005
CRITICAL
2 3
2
1C46030.01UF10%CERM16V
402
10%2
1C46020.01UFCERM16V
402
4
3
CRITICALL4600
90-OHM-100MATCM1005
1
2
3
4
2
6
1
5F-RT-TH
USB-M71-MG3
CRITICALJ4600
OMIT
3
4
2
6
1
5F-RT-TH
USB-M71-MG3
OMITCRITICALJ4601
2
1
6.3V
100UF20%POLYB2
C46112
1
100UF
CRITICAL
6.3V20%
B2
2
1
X5R
20%
603
10uFC4613
6.3V20%
1
402CERM10V
0.1UFC4612
2
21
L4602
0402-LF
FERR-120-OHM-1.5A
21
L4604
0402-LF
FERR-120-OHM-1.5A
21
L4603
0402-LF
FERR-120-OHM-1.5A
21
L4605FERR-120-OHM-1.5A
0402-LF
R465021 EXTAUSB_OC_F_L
1/16WMF-LF
5%
1K
402
21
R46511K5%
1/16WMF-LF402
EXTBUSB_OC_F_L
2
1C4650
402CERM-X5R6.3V10%0.47UF
2
1C465110%
402
6.3VCERM-X5R
0.47UF
3
D4600
2
1
CRITICAL
RCLAMP0502B
SC-75
2
1
3
CRITICAL
SC-75D4601
RCLAMP0502B
C467521
0.1UF
CERM
20%10V
402
4022
1R4677
MF-LF
10K1/16W5%
2
1C46060.01UF10%CERM16V
4022
1C4607
402
16VCERM10%0.01UF
9
6
7
5
8
2
1
4
3
TPS2060
MSOP
U4600CRITICAL
PI3USB10LPU4675
TQFNCRITICAL
57
31
2
4
8 10
9
6
0R4670
1/16W
NOSTUFF
21
5%
MF-LF402
NOSTUFF
20
R4671
5%1/16WMF-LF402
1
CONN,4P USB RCPT,MIDPLANE,MG3,LF J4600,J4601 NORMALCRITICAL2514-0457
FANCYCRITICALJ4600,J4601CONN,4P USB RCPT,MIDPLANE,BLACK,LF2514-0477
41
SYNC_MASTER=USB
USB EXTERNAL CONNECTORSSYNC_DATE=06/30/2006
01
76
051-7455
=PP5V_S5_USB
MIN_LINE_WIDTH=0.6MMVOLTAGE=5VPP5V_S3_USB2_EXTA
PP5V_S3_USB2_EXTBVOLTAGE=5V
PM_SLP_S4_LS5V
SMC_RX_LSMC_TX_L
=USB2_EXTA_P
USB2_MUXED_EXTA_NUSB2_MUXED_EXTA_P
USB2_EXTB_F_N=USB2_EXTB_N
USB2_MUXED_EXTA_P
=USB2_EXTA_N
=GND_CHASSIS_USB
PP5V_S3_USB2_EXTB_F
PP5V_S3_USB2_EXTB_FMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.3MMVOLTAGE=5V
USB2_EXTB_F_P
=PP3V42_G3H_SMCUSBMUX
=EXTBUSB_OC_L
=EXTAUSB_OC_L
=GND_CHASSIS_USB
=GND_CHASSIS_USB
PP5V_S3_USB2_EXTA_F
PP5V_S3_USB2_EXTA_FMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.3MMVOLTAGE=5V
=GND_CHASSIS_USB
=USB2_EXTB_P
USB2_GND_EXTA_F
MIN_NECK_WIDTH=0.3MMMIN_LINE_WIDTH=0.6MMVOLTAGE=0V
USB2_GND_EXTB_F
MIN_NECK_WIDTH=0.3MMVOLTAGE=0VMIN_LINE_WIDTH=0.6MM
USB2_EXTA_F_NUSB2_EXTA_F_P
USB2_MUXED_EXTA_N
USB_DEBUGPRT_EN_L
MIN_LINE_WIDTH=0.6MM
POLY
CRITICAL
C4610
OMIT
OMIT
46B4
46B6
45D5
45D5
41C2
41C4
41C4
41C4
44C5
44C5
41A4
41C2
41A4
41C2
44B8
44B8
41A2
41A2
41A2
41A4
7C1
65B6
6C2
6C2
8C2
41C5
41C5
8B2
8C2
8C8
41C3
41B2
7B1
8B2
8C2
8C8
8C8
41D3
41D2
8C8
8B2
41A5
44B8
41A5
OUT
SYM_VER-1
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
GEYSER AND DIMM0 REMOTE TEMP SENSORS
PLACE L4701 NEAR J4700
PLACE C4700 NEAR J4700
516S0588
R47101 2
402MF-LF1/16W
1K5%
C47101
2402CERM10V
0.1UF20%
C47001
2402
0.1UF10V20%CERM
D4700
3
1
2
CRITICAL
RCLAMP0502B
SC-75
L47001 2
600-OHM-300MA
0402
L47021 2
600-OHM-300MA
0402
J4700
1
10
2
3 4
5 6
7 8
9
F-ST-SM
CRITICAL
53307-1039
L4703
1 2
600-OHM-300MA0402
C47031
240216VCERM
0.01uF10%
L4701
1
2 3
4
CRITICAL
90-OHM-100MATCM1005
CONNECTOR MISC
76
01
SYNC_DATE=06/29/2006SYNC_MASTER=USB
42
051-7455
VOLTAGE=5VMIN_NECK_WIDTH=0.3MM
PP5V_S3_GEYSER_F
MIN_LINE_WIDTH=0.6MM
GEYSER_GND_FMIN_LINE_WIDTH=0.6MMMIN_NECK_WIDTH=0.3MMVOLTAGE=0V
=USB2_GEYSER_P
=USB2_GEYSER_N
CONN_GEYSER_ONOFF_L
=PP5V_S3_GEYSER
SMC_LID_LC SMC_LID
MAKE_BASE=TRUESMC_ONOFF_L
CONN_GEYSER_USB_P
CONN_GEYSER_USB_N
CONN_GEYSER_ONOFF_FLTR_L
57A8
45D5
45C5
45C8
44B5
44C5
8C2
8C2
7A4
6B2
SYM_VER-1
SYM_VER-1
P0_3/INT1
P0_4/INT2
P0_5/TIO0
P0_6/TIO1
P0_7
P0_2/INT0
P0_1
THRM_PAD
NC
P1_7
P1_6/MISO
P1_5/SMOSI
P1_4/SCLK
P3_1
P3_0
P1_3/SSEL
P1_2/VREG
VDD
P1_1/D-
P1_0/D+
VSS
NC
P2_1
P2_0
P0_0
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
518S0521
SB HAS INTERNAL 15K PULL-DOWNS
TO M13D SLOT
IR CYPRESS ENCORE II USB CONTROLLER
PLACE C4800 AND C4801NEAR U4800 PIN 16
PLACE L4810 NEAR J4800
PLACE L4800 NEAR J4800
3G CONNECTOR
BLUETOOTH
PLACE L4811 NEAR J4800
PLACE C4810 C4811 NEAR L4810
C4803 CLOSE TO U4800 PIN 2
C48111
2
0.1UF20%10VCERM402
L4812
1
2 3
4
90-OHM-100MA
CRITICAL
TCM1005
C48101
2603
10UF
X5R
20%6.3V
L48101 2
120-OHM-0.3A-EMI
0402-LF
L48111 2
120-OHM-0.3A-EMI
0402-LF
C48031
2
0.001UF50VCERM10%
402
R48001 2
402
1/16W
100
MF-LF
5%
J4850
1
10
11
12
13
14
2
3
4
5
6
7
8
9
LVC-D10SFYGF-RT-SM
CRITICALNOSTUFF
L4855
1
23
4
90-OHM-100MA
CRITICAL
TCM1005
NOSTUFF
U4800
1011121719
2728293031
765432132
1415182023242526
98
2122
33
16
13
OMIT
CRITICALCY7C63833
QFN
C48001
2
1UF10V10%X5R402
C48011
2402
0.1UF20%10VCERM
L48541 2
FERR-120-OHM-1.5A
NOSTUFF
0402
L48531 2
FERR-220-OHM-2A
0603
NOSTUFF
L48521 2
FERR-220-OHM-2A
0603
NOSTUFF
C48501
210%0.01UF50V
402X7R
NOSTUFFC48511
2402
0.01UFX7R10%50V
NOSTUFF
J4810
5
6
1
2
3
4
M-RT-SM78171-0004
CRITICAL
C48021
210%CERM50V0.001UF
402
C48521
2
NOSTUFF
402X7R10%50V0.01UF
R48011 2
5%
MF-LF1/16W
402
0
R48021 2
0
402
1/16WMF-LF
5%
C48041
2402X5R10%10V1UF
R48031 2
5%
MF-LF1/16W
402
0
IR CONTROLLER & BT INTERFACE
01
43 76
051-7455
=PP5V_S3_IR PP5V_S3_IR_R
TP_IR_P00TP_IR_P01
TP_IR_P03TP_IR_P04
USB2_IR_N_R
=USB2_IR_P
USB2_IR_P_R=USB2_IR_N
ENCORE_VREG_C
IR_RX_OUT_RC
TP_IR_P02
USB2_BT_F_NUSB2_BT_F_P
MIN_LINE_WIDTH=0.2MMVOLTAGE=0VMIN_NECK_WIDTH=0.2MM
GND_BT_F
=USB2_BT_N
=USB2_BT_P
=GND_CHASSIS_3GPOWER
=PP3V3_S3_BT
IR_RX_OUT
MIN_NECK_WIDTH=0.2MMVOLTAGE=3.3VMIN_LINE_WIDTH=0.2MM
PP3V3_S3_BT_F
USB2_3G_F_NUSB2_3G_F_P
PP5V0_S0_3G_F
GND_CHASSIS_3G_CONN
=GND_CHASSIS_3GPOWER
GND_3G_F
=USB2_3G_N
=USB2_3G_P
=PP5V_S0_3G
43B5
43A5
7A4
8C2
8C2
6C1
6C1
6A2
8B2
8C2
8D8
7A4
40C6
6A2
6C1
6C1
8D8
8C2
8C2
7A7
IN
IN
IN
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
OUT
OUT
P16
P51
P50
P42/SDA1
P97/IRQ15*/SDA0
P95/IRQ14*
P94/IRQ13*
P93/IRQ12*
P92/IRQ0*
P91/IRQ1*
P86/IRQ5*/SCK1/SCL1
P83/LPCPD*
P82/CLKRUN*
P80/PME*
P35/LRESET*
P34/LFRAME*
P10
P12
P13
P14
P15
P17
P31/LAD1
P30/LAD0
P32/LAD2
P33/LAD3
P36/LCLK
P37/SERIRQ
P44/TMO1
P77/AN7
P76/AN6
P81/GA20
P96/EXCL
P11
P47/PWX1/PWM1
P45
P46/PWX0/PWM0
P40/TMIO
P43/TMI1/EXSCK1
P27
P26
P25
P24
P23
P22
P21
P20
P41/TMO0
P52/SCL0
P60/KIN0*
P61/KIN1*
P62/KIN2*
P63/KIN3*
P64/KIN4*
P65/KIN5*
P66/IRQ6*/KIN6*
P67/IRQ7*/KIN7*
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P84/IRQ3*/TXD1
P85/IRQ4*/RXD1
P90/IRQ2*
(1 OF 4)
PA2/KIN10*/PS2AC
PA3/KIN11*/PS2AD
PA5/KIN13*/PS2BD
PA4/KIN12*/PS2BC
PB2
PB3
PB4
PE0
PG6/EXIRQ14*/EXSDAB
PG5/EXIRQ13*/EXSCLA
PH1/EXIRQ7*
PH0/EXIRQ6*
PG7/EXIRQ15*/EXSCLB
PG4/EXIRQ12*/EXSDAA
PH3/EXEXCL
PH2/FWE
PB5
PF4/PWM4
PF2/IRQ10*/TMOY
PG2/EXIRQ10*/SDA2
PG0/EXIRQ8*/TMIX
PF7/PWM7
PC3/TIOCD0/TCLKB/WUE11*
PH5
PB7
PB6
PH4
PF5/PWM5
PF6/PWM6
PG1/EXIRQ9*/TMIY
PA6/KIN14*/PS2CC
PA7/KIN15*/PS2CD
PD0/AN8
PD1/AN9
PD2/AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
PF0/IRQ8*/PWM2
PF1/IRQ9*/PWM3
PB0/LSMI*
PB1/LSCI
PC0/TIOCA0/WUE8*
PC1/TIOCB0/WUE9*
PC2/TIOCC0/TCLKA/WUE10*
PC4/TIOCA1/WUE12*
PC5/TIOCB1/TCLKC/WUE13*
PC6/TIOCA2/WUE14*
PC7/TIOCB2/TCLKD/WUE15*
PG3/EXIRQ11*/SCL2
PF3/IRQ11*/TMOX
PA1/KIN9*/PA2DD
PA0/KIN8*/PA2DC
PE1*/ETCK
PE2*/ETDI
PE3*/ETDO
PE4*/ETMS
(2 OF 4)
VCL
AVREF
VCC
VCC
VCC
AVCC
XTAL
EXTAL
AVCC
VCC
MD1
MD2
NMI
RES*
ETRST*
AVREF
AVSSVSS
(3 OF 4)
NC22
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC9
NC6
NC11
NC10
NC8
NC7
NC5
NC4
NC3
NC2
NC1
NC0
(4 OF 4)
OUT
OUT
BI
IN
IN
OUT
BI
BI
OUT
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
ININ
OUT
OUT
BI
BI
OUT
IN
OUT
OUT
OUT
IN
BI
BI
BI
BI
IN
IN
IN
OUT
BI
IN
IN
IN
IN
BI
BI
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
(OC)
(OC)
(OC)
(OC)
(OC)
(DEBUG_SW_1)
(DEBUG_SW_2)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(OC)
(DEBUG_SW_3)
pins designed as outputs can be left floating,
(OC)
NC
NC
NC
If SMS interrupt is not used, pull up to SMC rail.
NOTE: SMS Interrupt can be active high or low, rename net accordingly.
(OC)
those designated as inputs require pull-ups.
NOTE: Unused pins have "SMC_Pxx" names. Unused
(OC)
C4902 1
2
805CERM
22UF20%
6.3V
6C2 24D5 46B4
6C2 45D7 46B4
42C8 45C8 45D5
C4907 1
2CERM-X5R
0.47UF
PLACEMENT_NOTE=Place C4907 close to U4900 pin F1
10%
402
6.3V
C49031
2 CERM10V
0.1UF
402
20%
C4920 1
2
PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15
CERM10V
0.1UF
402
20%
R49991 2
PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15
MF-LF
5%1/16W
4.7
402
C49041
2 CERM10V
0.1UF
402
20%
XW4900
1
2
SM
24C3
59C7
C49051
2 CERM10V
0.1UF
402
20%
24C2
45D5 63B4 63B5
6B2 27A5 58A3
44A4
C49061
2 CERM10V
0.1UF
402
20%
48C1 59C7
6B2 48B1
44A4
44A4
66C2
48D6
66B1
45B3
6D1 45C5 57A2
6C1 45B6 57C3 57C7 66A6
6C2 41A8 44C5 45D5 46B6
6C2 41A8 44C5 45D5 46B4
6C1 33C7 35C7 38C6 45B3 57C4
65C6 U4900B12
C13
A15
B14
B15
C14
D12
C15
D13
D14
D15
E12
E14
E15
E13
F14
D9
C9
A9
B9
D8
C8
A8
D7
A5
B5
D5
C3
B1
C2
D3
C1
G1
G4
F2
L13
L14
L15
K12
K13
K14
J12
J13
N12
R13
P13
R14
P14
R15
N13
P15
C7
A7
B7
D6
C6
A6
B6
K4
J2
J1
J3
J4
H2
H1
G2
BGA
SMC_H8S2116
OMIT
U4900R3
P3
R2
N3
R1
N2
M4
N1
B10
A10
D10
A11
B11
C11
A12
D11
G14
G15
G13
G12
H14
H15
H13
H12
M11
P11
R11
N11
P10
R10
N10
M10
M3
M2
M1
L4
L2
M7
P6
R6
N6
M6
R5
P5
N5
P9
R9
N9
P8
R8
M8
P7
R7
E1
F3
K2
C4
D4
B3
OMIT
BGA
SMC_H8S2116
U4900
N14
N15
M14
M15
P12
R12
L1
B2
E2
K1
F4
E3
P2
P1
J15
A1
F1
D1
P4
R4
F12
F13
B13
A13
A4
B4
D2
A2
SMC_H8S2116
OMIT
BGA
U4900
G3
H3
K15
J14
F15
A14
C12
C10
C5
A3
B8
E4
K3
H4
M9
N8
L3
N4
M5
N7
M12
M13
L12
BGA
SMC_H8S2116
OMIT
6C1 45B6 66A3
6C1 45B6 66A4
47B3
R49091
2
1/16W5%
MF-LF
10K
402
6C2 46B4
6C2 46B6
R49011
2
1/16W5%10K
402MF-LF
R49021
2
10K
MF-LF
5%1/16W
402
R49031
2
1/16W5%
MF-LF
0
NO STUFF
402
R49981
2
1/16W5%
MF-LF
10K
402
41A5
6C1 45D5 57C8
8B2 15B7
24A5 24C3
48A8
39B2
45C3
44B4
24C8
45D5
44B4
6D2 50B4
44B4
44B4
6A7 44A4
44B4
6D2 50C4
44B4
51C2
51C2
61C5
51C2
44A4
44A4
62C2
6C2 45C5 46B4
45B3
6C2 45C5 46B4
6C2 45C5 46B6
6C2 45C5 46B6
6B2 42C3 45C5 57A8
6C1 66A8
44A4
66B8
44A4
47C3
47C3
47D3
47D3
47C6
47C6
45B6
45B5
44B4
51C7
45C6
6C2 41A8 44B8 45D5 46B4
6C2 41A8 44B8 45D5 46B6
45C5
51A8 45D5
44A4
45A6
6C2 24C8 46B4
8B2 15B7
24D5 27C5
6C2 46B6
24C8
6C2 24C8 37A5 46B6
24C2
45C5
6D2 22D4 46C6
6D2 22D4 46C6
6C2 22D4 46C4
6C2 22D4 46C4
6C2 22D4 46B6
27C1
29A3 29A5 75B3
44B4
47D6
24D3 33C7 35C7 45A6 58B7 62B8
24D3 33B7 65A6 65C4
24D3 45C3
45A7
47D6
47B3
45D1
SYNC_DATE=10/30/2006SYNC_MASTER=T9_MLB
SMC
44 76
01051-7455
PP3V3_S5_AVREF_SMC
=PP3V42_G3H_SMC
GND_SMC_AVSS
SMC_RESET_L
SMC_P67
NC_SMC_P20MAKE_BASE=TRUE
NC_SMC_GFX_THROTTLE_LMAKE_BASE=TRUE
MAKE_BASE=TRUENC_SMC_P14
NC_SMC_P22MAKE_BASE=TRUE
NC_SMC_P23MAKE_BASE=TRUE
NC_SMC_P21MAKE_BASE=TRUE
SMC_P14
SMC_WAKE_SCI_L
SMC_BATT_ISENSE
SMC_PBUS_VSENSE
SMC_DCIN_ISENSE
SMC_P23SMC_P26
SMC_P22SMC_P21
SMC_SUS_CLK
SMC_BS_ALRT_L
NC_SMC_P43MAKE_BASE=TRUE
NC_SMC_P64MAKE_BASE=TRUE
SMC_GPU_VSENSE
SMC_P81SMC_P64
SMC_P43
SMC_PF1
ALS_GAINSMC_EXCARD_PWR_EN
NC_SMC_FAN_0_CTLMAKE_BASE=TRUE
MAKE_BASE=TRUENC_SMC_FAN_2_TACH
NC_SMC_FAN_3_CTLMAKE_BASE=TRUENC_SMC_FAN_2_CTLMAKE_BASE=TRUE
NC_SMC_PF0MAKE_BASE=TRUENC_ALS_RIGHTMAKE_BASE=TRUE
NC_SMC_FAN_3_TACHMAKE_BASE=TRUE
NC_ALS_LEFTMAKE_BASE=TRUE
SMC_EXTAL
SMC_XTAL
SMC_TRST_L
SMC_KBC_MDE
SMC_NMI
SMC_MD1
MIN_NECK_WIDTH=0.20 MM
PP3V3_S5_SMC_AVCC
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.25 MM
SMC_VCL
SMC_RX_L
SMC_NB_1V25_ISENSE
SMC_CPU_VSENSE
SMC_P64
SMC_PROCHOT_3_3_L
PM_LAN_ENABLE
SMC_P22
PM_SYSRST_L
SMC_FAN_1_TACH
SMC_FAN_0_TACH
SMC_FAN_3_CTL
SMC_FAN_2_CTL
SMC_GFX_OVERTEMP_L
SMC_EXCARD_OC_L
ISENSE_CAL_EN
SMC_ODD_DETECT
SMC_RUNTIME_SCI_L
SMC_EXCARD_CP
SMC_EXCARD_PWR_EN
SMC_PB0
SYS_ONEWIRE
PM_BATLOW_L
SMB_0_S0_DATA
PM_S4_STATE_L
SMC_CPU_ISENSE
SMC_PM_G2_EN
SMC_PA1
PM_EXTTS_L<0>
SMC_P23
SMC_P26
RSMRST_PWRGD
SMC_RSTGATE_L
ALL_SYS_PWRGD
SMC_BATT_TRICKLE_EN_L
LPC_AD<0>
LPC_AD<1>
LPC_AD<2>
LPC_AD<3>
SMC_LRESET_L
PCI_CLK33M_SMC
INT_SERIRQ
SMC_P44
USB_DEBUGPRT_EN_L
PM_EXTTS_L<1>
SMC_FAN_0_CTL
SMC_FAN_3_TACH
SMS_X_AXIS
SMC_NB_CORE_ISENSE
SMC_NB_1V8_ISENSE
ALS_LEFT
ALS_RIGHT
PM_RSMRST_L
SMC_P21
IMVP_VR_ON
SMC_FAN_1_CTL
SMC_ANALOG_ID
SMS_Z_AXIS
SMS_Y_AXIS
SMC_FAN_2_TACH
PM_SLP_S3_L
SMC_TCK
PM_CLKRUN_L
PM_SUS_STAT_L
SMC_ONOFF_L
PM_SLP_S5_L
SMC_TX_L
SMC_P81
SMB_MGMT_CLK
SMC_SYS_LED
SMC_P45
SMC_GFX_THROTTLE_L
PM_LAN_PWRGD
SMC_P14
SMC_GPU_ISENSE
SMC_ADAPTER_EN
SMC_P62
SMC_P63
SMC_P46
SMC_P20
SMC_PF1
SMC_TMS
NC_SMC_FAN_0_TACHMAKE_BASE=TRUESMC_FAN_0_TACH
NC_SMC_PF1MAKE_BASE=TRUE
MAKE_BASE=TRUENC_SMC_BATT_VSET
ALS_LEFT
SMC_P20
SMC_TDI
LPC_FRAME_L
SMB_MGMT_DATA
SMC_BC_ACOK
SMC_TDO
SMC_PF0
SMC_LID
SMC_PF3
SMC_BATT_ISET
SMC_PA0
SMB_0_S0_CLK
SMC_RX_L
SMC_TX_L
SMC_P46
SMS_ONOFF_L
SMC_P63SMC_P62
SMC_P44 MAKE_BASE=TRUENC_SMC_P44
MAKE_BASE=TRUENC_SMC_P27
MAKE_BASE=TRUENC_SMC_P63
SMC_FAN_0_CTL
NC_SMC_P46MAKE_BASE=TRUE
MAKE_BASE=TRUENC_SMC_P26
MAKE_BASE=TRUENC_SMC_P62
MAKE_BASE=TRUENC_SMC_P81
NC_SMC_SYS_KBDLEDMAKE_BASE=TRUE
NC_SMC_EXCARD_PWR_ENMAKE_BASE=TRUENC_ALS_GAINMAKE_BASE=TRUE
SMC_SYS_KBDLED
SMC_P27
MAKE_BASE=TRUENC_SMC_RSTGATE_LMAKE_BASE=TRUENC_SMC_SYS_VSET
SMC_PH4
ALS_GAIN
SMC_PF0
SMC_FAN_3_CTL
SMC_GFX_THROTTLE_L
SMC_GPU1_VSENSE
SMC_SYS_VSETSMC_BATT_VSET
SMC_FAN_3_TACH
SMC_FAN_2_CTL
SMC_FAN_2_TACH
ALS_RIGHT
SMC_RSTGATE_L
SMC_CASE_OPEN
SMC_SYS_KBDLED
SMC_P43
SMC_P27
SMC_BATT_CHG_EN
PM_PWRBTN_L
SMC_BATT_VSET
SMC_SYS_ISET
SMC_SYS_VSET
SMC_PG0
SMB_B_S0_DATA
SMC_P45 SMC_ENRGYSTR_LDO_ENMAKE_BASE=TRUE
SMC_ENRGYSTR_LDO_PGOODMAKE_BASE=TRUE
SMC_GPU1_ISENSESMC_GPU_ISENSEMAKE_BASE=TRUE
SMC_GPU_VSENSEMAKE_BASE=TRUE
SMC_PH4
SMC_FWE
SMC_THRMTRIP
SMC_PROCHOT
SMB_B_S0_CLK
SMB_A_S3_CLK
SMB_A_S3_DATA
SMB_BSA_CLK
SMB_BSA_DATA
SMC_SMS_INT
66C2 66B1 62C2 61C5 60B2
51B8
48C6
45D8
48C1
45D4
48B1
45C1
48A1
44A8
66C1
60C7
45C6
7C1
45B6
45C5
44D8
44C8
44C8
44C8
44C8
44C5
44D5
44C8
44B5
44A5
44B8
45C7
45C7
44B4
44B4
45C5
45C5
44B4
44B4
44B4
44B4
44B4
44A4
44B4
44B4
44B4
44B8
44C8
44B4
44A8
44A8
44B4
44A4
45C1
45C5
44B4
44D5
44D5
44C8
44A8
44B8
44C8
44A4
44B5
44A8
44C8
48B1
44B5
44B5
6A7
44A8
44A8
44A8
44D8
44B4
44B4
45C5
44C8 66D3
45C5
60B2 44C5
44C5
44A5
D
SG
IN
D
SG
OUT
D
SG
IN
D
SG
OUT
NCCD
GND
OUT
VDD
OUT
GND
VIN VOUT
OUT
TABLE_ALT_ITEM
TABLE_5_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
REFERENCE DESIGNATOR(S) BOM OPTIONTABLE_5_HEAD
QTY DESCRIPTIONPART#
SYSTEM (SLEEP) LED CURRENT DRIVER
3.3V TO PBUS LEVEL SHIFTING
NC
R5011 CLOSE TO SB0.0094A NORMAL
Silk: "SMC RST"
SMS_INT_L
0.007A FANCY
SMC_CPU_RESET_3_3_L
ENABLE VSENSE IN S0 ONLY
Silk: "PWR BTN"
SMC AVREF Supply
RC FILTERED AT SATA CONN
SMC_TPM_RESET_L
SMC 1.05V to 3.3V Level ShiftingTHESE NEED TO BE PULLED TO THE PROPER RAIL:
Is this the best part to use?
SMS_INT_L
SMC 3.3V to 1.05V Level Shifting
SMC Reset Button / Brownout Detect
Debug Power Button SMC Crystal Circuit
MF-LF
10K5%1/16W4022
1 R5076
10K21R5053
CERM5%
15PF
50V402
21
C5021
10K21R5085R5086 10K21R5087 10K21
R5048 2 10K1
100K21R5094
R5030 10K21
10K21R5080
10K21R5054
10K21R5055
10K21R5028
10K21R5024
100K21R5081
10K21R5047
10K21R5096
10K21R5097
2.0K21R5082
R5073 100K21
SOT-363MMDT3906XF
4
3
5 Q5050
402
1/16W1%
MF-LF
3.74K21
R5052
402MF-LF
1%1/16W
357
2
1R5051
SOT-363MMDT3906XF
1
6
2Q5050
470K21R5083
CRITICAL
20.00MHZ5X3.2-SM
21
Y5020 10K1 2R509110KR5098 21
10KR5099 21
SOT563SSM6N15FE
12
6Q5002
10K21R5084
402MF-LF1/16W1%
470K21
R5075
SOT563SSM6N15FE
45
3Q5002
R50891 10K2
10K21R5049
R5090 21 10K
5%
MF-LF1/16W
3.3K
402
21
R5071
3.3K5%
MF-LF402
1/16W
2
1R5070
BC847BV-X-FSOT563
1
6
2Q5077
SOT563BC847BV-X-F
4
3
5Q5077
402MF-LF1/16W5%470
2
1R5078
R5079 10K21
402MF-LF1/16W1%
OMIT
31.6
2
1R5050
470K21R5088
SOT563SSM6N15FE
45
3Q5001
402CERM50V10%0.001UF
2
1C5050
100K21R5006
SOT563SSM6N15FE
12
6Q5001
MF-LF4021/16W1K5%
2
1R5000
SOT23-5RN5VD30A-F
CRITICAL2
1
4
3
5
U5000CERM20%
0.1UF
40210V 2
1C5000
402
0.01UF16VCERM10%
2
1C50015%
402
0
MF-LF1/16W
NOSTUFF
2
1R5001
40250VCERM5%
15PF21
C5020
402
10%16V0.01UFCERM2
1C5067
603X5R6.3V20%10uF
2
1C5066
10KR50951 2
4021/16W5%
0
NOSTUFF
MF-LF
21
R5072
MF-LF
05%
NOSTUFF
1/10W6032
1R5010
CRITICAL
SOT23-3ISL60002-33
21
3
VR5065
CERM-X5R10%0.47UF
4026.3V2
1C5065
0
1/16WMF-LF402
5%21
R5011
? TI REF3133353S1381353S1278 VR5065
FANCYR505044.2, 1%, 1/16W, MF-LF, 4021114S0086
NORMALR505031.6, 1%, 1/16W, MF-LF, 4021114S0071
051-7455
SYNC_MASTER=GPU
45
01
SYNC_DATE=07/17/2006SMC SUPPORT
76
SMC_NB_1V25_ISENSE
RSMRST_PWRGD
SMC_PA0
=PP5V_S3_SYSLED
SYS_LED_ILIM
PM_THRMTRIP_L
SMC_BC_ACOK
CPU_PROCHOT_L_R
VOLTAGE=3.3VMIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.4 MMPP3V3_S5_AVREF_SMC
CPU_PROCHOT_L
PP3V3_S0
GND_SMC_AVSSMIN_LINE_WIDTH=0.4 MMMIN_NECK_WIDTH=0.2 MMVOLTAGE=0V
SMC_MANUAL_RST_L
=PP3V42_G3H_SMCVREF
SMC_SUS_CLKSUS_CLK_SB
SMC_PROCHOT
SMC_ONOFF_L
SMC_RESET_L
PM_SLP_S3_L
=PPVIN_S5_IMVP
SMC_SYS_LED
SYS_LED_EN
SMC_PF3
SMC_ANALOG_ID
=PP3V42_G3H_SMC
SMC_GFX_OVERTEMP_L
SYS_LED_ISETPBUS_SMC_VSENSE_EN_L
SMC_PROCHOT_3_3_L
PP1V05_S0
CPU_PROCHOT_BUF
CPU_PROCHOT_L
SMC_BATT_CHG_EN
SMC_THRMTRIP
SYS_LED_ANODESYS_LED_BIAS
SMC_PB0SMC_PA1
SYS_ONEWIRE
SMC_TX_L
SMC_TCK
PM_LAN_PWRGD
SMC_ADAPTER_EN
SMC_CASE_OPEN
SMC_EXCARD_CP
=PP3V42_G3H_SMC
SMC_XTAL
SMC_BATT_TRICKLE_EN_L
SMC_EXTAL
SMC_FWESMC_LID
SMC_P67SMC_PG0
SMC_TDI
SMC_ENRGYSTR_LDO_PGOOD
SMC_TMS
SMC_ONOFF_L
=PP3V3_S0_SMC_LS
SMC_EXCARD_OC_L
SMC_BS_ALRT_L
=PP3V42_G3H_SMC
PM_SLP_S5_L
SMC_TDO
SMC_RX_L
66C2 66B1 62C2 61C5 60B2
62B8
57C4
66A6
48C6
58B7
51B8
46B6
44D5
51B8
51B8
46B4
70B3
57C7
70C3
48C1
44C5
45D8
70C3
44C5
38C6
45D4
57A8
45D8
44C5
63B5
22C2
57C3
59C8
48B1
45D5
46B4
35C7
45D4
59C8
66A4
57C8
44B8
46B4
35C7
45C1
66A3
44B5
46B4
46B6
45C8
57A2
45C1
44B8
63B4
40B6
15A6
44C5
45B5
7D4
48A1
44C5
44C3
33C7
44D4
7D7
45C3
44C8
40C5
44B8
41A8
44B5
33C7
44D4
44C8
42C3
44B5
66C1
44B5
44C5
44C5
44D4
44C5
41A8
44C5
44D8
44B8
7A4
9C6
6C1
44D4
9C5
6A2
44C1
6B2
7C1
44C5 24D3
44A5
42C8
6C2
24D3
7A1
44C8
44B5
44A8
7C1
44A8
48D7
44C5
6B2
9C5
6C1
44A5
6B2
44B8
44B8
6C1
6C2
6C2
44C5
6C1
44B5
44B8
7C1
44C3
6C1
44C3
44A5
6B2
44C5
44B5
6C2
44A2
6C2
42C8
7D4
44B8
6D1
7C1
24D3
6C2
BI
BI
IN
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
BI
BI
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
OUT
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
LPC+ Connector
516S0416
FWH_INIT_L Generation
6C2 22D4 44C8
6C2 24C8 44C8
6C2 29B3 75C3
6C2 24D5 44C5
6C2 24C8 37A5 44C5
6C2 23B5
6C2 44B5 45C5
6C2 44C1
6C2 44D1
6C2 27D1
6C2 22D4 44C8
6D2 22D4 44C8
6D2 22D4 44C8
6C2 44B5 45C5
6C2 44C3 45D7
6C2 44C1
6C2 24A7 24D5
R51921
2 402
5%1/16WMF-LF
LPCPLUS
330R51911
2
1.3K
402MF-LF1/16W5%
LPCPLUS
R51901 2
5%1/16WMF-LF402
330
LPCPLUS
PLACEMENT_NOTE=Place R5190 to minimize CPU_INIT_L stub
9D6 22C4 70B3
6C2 41A8 44B8 44C5 45D5
6C2 41A8 44B8 44C5 45D5
6C2 44B5 45C5
6C2 44B5 45C5
Q5190 5
3
4
LPCPLUS
SOT563BC847BV-X-F
Q5190 2
6
1
BC847BV-X-F
LPCPLUS
SOT563
J5100
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
SM1
CRITICALLPCPLUS
F-ST-5047
6C2 22D4 44C8
76
LPC+ Debug Connector
01
SYNC_MASTER=WFERRY SYNC_DATE=06/01/2006
46
051-7455
=PP5V_S0_LPCPLUS
LPC_AD<0>LPC_AD<1> LPC_AD<2>
=PP3V42_G3H_LPCPLUS
BOOT_LPC_SPI_LSMC_TMSDEBUG_RESET_LSMC_TRST_LSMC_TDO
SMC_TCKSMC_TDI
LPC_AD<3>
FWH_INIT_L
PM_CLKRUN_LCPU_INIT_R_L
CPU_INIT_LS3V3
LINDACARD_GPIO
SMC_NMISMC_RESET_L
PM_SUS_STAT_LINT_SERIRQ
PCI_CLK33M_LPCPLUS
SMC_MD1
=PP3V3_S0_LPCPLUS
CPU_INIT_L
SMC_TX_LSMC_RX_L
LPC_FRAME_L
7A7
7B1
6D2
6D2
6C2
7C4
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
ICH8-M SMBus Connections
SMC MGMT BusSMC
AIRPORT
U4900
SMC "MANAGEMENT" SMBUS CONNECTIONS
SMC "B" SMBus Connections
SO-DIMM "A"
(Write: 0x16 Read: 0x17)
SMC "0" SMBus Connections
SMC "Battery A" SMBus Connections
J3400
CPU TempEMC1043-5: U5520
(MASTER?)
ICH8-MU2300
(MASTER) (Write: 0x98 Read: 0x99)
NOTE: SMC RMT bus remains powered and may be active in S3 stateSMC "A" SMBus Connections
U4900(MASTER)
SMC
SMCU4900
(MASTER)
SMC
U4900SMC
(MASTER)U4900
J3100(Write: 0xA0 Read: 0xA1)
Clock Chip(Write: 0xD2 Read: 0xD3)
SLG8LP537V: U2900ICH8-M
U2300(MASTER)
J3200SO-DIMM "B"
(Write: 0xA4 Read: 0xA5)
U5500HEAT PIPE/FIN-STACK
J6950Battery
SMSU5930
ICH8-M ME SMBus Connections
R52001
2MF-LF
4.7K1/16W
402
5%
R52011
2
4.7K
402
5%1/16WMF-LF
R52801
2402
1/16W5%
8.2K
MF-LF
R52811
2402
1/16WMF-LF
5%8.2K
R52611
2402
5%4.7K1/16WMF-LF
R52601
2
5%
MF-LF402
4.7K1/16W
R52711
2402MF-LF1/16W5%100K
R52701
2402MF-LF1/16W
100K5%
R52511
2402
5%4.7K1/16WMF-LF
R52501
2
4.7K5%
MF-LF1/16W
402
R52311
2
10K5%1/16WMF-LF402
R52301
2
10K5%
402
1/16WMF-LF
R52331
2
10K
402MF-LF1/16W5%
R52321
2402MF-LF
5%1/16W
10K
SYNC_MASTER=WFERRY
SMBUS CONNECTIONS
47 76
01051-7455
SYNC_DATE=06/01/2006
SMB_MGMT_CLK
=I2C_SMS_SDA
SMBUS_SMC_B_S0_SDAMAKE_BASE=TRUE
=I2C_SMS_SCL
=SMB_AIRPORT_CLK
SMB_MGMT_DATA SMBUS_SMC_MGMT_SDAMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_MGMT_SCL
THRM_CPU_SMB_CLK
=PP3V3_S3_SMBUS_SMC_MGMT
=SMB_AIRPORT_DATA
MAKE_BASE=TRUESMBUS_SB_ME_SDA
SMBUS_SB_ME_SCLMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_0_S0_SDA
MAKE_BASE=TRUESMBUS_SMC_B_S0_SCL
=PP3V3_S0_SMBUS_SMC_B_S0
=SMBUS_CK505_SCL
SMBUS_SMC_BSA_SCLMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SMC_BSA_SDA =SMBUS_BATT_SDA
THRM_CPU_SMB_DATA
=PP3V3_S5_SMBUS_SB_ME
SMB_ME_CLK
SMB_ME_DATA
=PP3V3_S3_SMBUS_SMC_A_S3
MAKE_BASE=TRUESMBUS_SMC_A_S3_SCL
MAKE_BASE=TRUESMBUS_SMC_A_S3_SDA
SMB_A_S3_CLK
SMB_A_S3_DATA
=PP3V42_G3H_SMBUS_SMC_BSA
SMB_0_S0_DATA
SMB_0_S0_CLK
SMB_B_S0_CLK
SMB_B_S0_DATA
=SMBUS_CK505_SDA
=I2C_SODIMMA_SCL
=I2C_SODIMMA_SDA
SMBUS_SB_SCLMAKE_BASE=TRUE
MAKE_BASE=TRUESMBUS_SB_SDA
=PP3V3_S0_SMBUS_SB
SMB_CLK
SMB_DATA
=I2C_SODIMMB_SCL
=I2C_SODIMMB_SDA
SMB_BSA_DATA
SMB_BSA_CLK
MAKE_BASE=TRUESMBUS_SMC_0_S0_SCL
=PP3V3_S0_SMBUS_SMC_0_S0
THRM_HEATPIPE_SMB_DATA
THRM_HEATPIPE_SMB_CLK
=SMBUS_BATT_SCL76C3
51B6
76C3
73A3
73A3
73A3
73A3
44C5
51A6
6B2
51A6
33B3
44C8 76C3
76C3
49B4
7A4
33B3
76C3
6B2
7C4
28B6
76C3
76C3 57A2
49B4
7D1
24D5
24D5
7A4
76C3
76C3
44A5
44A5
7B1
44B5
44B8
44A5
44A5
28B6
30A6
30A6
7C4
24D5
24D5
31A6
31A6
44A5
44A5
76C3
7C4
49D4
49D4
57A2
IN
V-
V++
-
S D
G
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
CPU CURRENT SENSE
PLACE C5350 NEAR SMC
PLACE RC FILTER CLOSE TO SMC
DRIVEN LOW IN S0
PROCESSOR DCIN VOLTAGE SENSE
Switches in fixed load on power supplies to calibrate current sense circuitsCurrent Sense Calibration Circuit
GPU VOLTAGE SENSE
C5376 CLOSE TO SMC
C5312 CLOSE TO SMC
CPU VOLTAGE SENSE
R53431
2
1/4W1%
1206
1.00
MF-LF
R53511
2402MF-LF1/16W1%5.49K C53501
2 6.3VCERM-X5R
0.22UF10%
402
R53501
2
27.4K1/16WMF-LF
1%
402
C53041
2
NOSTUFF
0.1UFCERM10V20%
402
C53551
2
0.1UF
NOSTUFF
CERM10V20%
402R53031
2
1/16WMF-LF
1M1%
402
R53001 2
1%
1M
1/16WMF-LF402
R53071 2
5%
0
MF-LF1/16W
402
R53051 230.1K
1%
MF-LF1/16W
402
R53081 2
402
1/16WMF-LF
5%
0R53061 230.1K
1%
MF-LF1/16W
402
C53761
2
0.22UF6.3VX5R402
20%
R53811 24.53K
1%MF-LF1/16W402
U53001
3
4
2
5
CRITICAL
HPA00141AIDCKRSC70-5
C53001 2
50V10%CERM
470PF
402
R53421 21K
402
5%
MF-LF1/16W
U53022
3 1
54
SC70-5
SN74AHCT1G125DCKRE4
CRITICAL
Q5350
3
1
2
SOT-723SSM3J15FV
C53031
2
470PF10%50VCERM402
C53011 20.1UF
10V20%
402CERM
R53021 2
1%MF-LF1/16W402
4.53K
C53021
220%6.3VX5R
0.22UF
402
Q530012563
4
TSOP-LFSI3446DV
CRITICAL
R53121 2
402MF-LF
4.53K1%
1/16WC53121
220%6.3V0.22UFX5R402
051-745548
SYNC_MASTER=GPU
CPU Current & Voltage SenseSYNC_DATE=07/17/2006
76
01
=PP3V3_S0_CPUPOWER
CPU_ISENSE_R_N
CPU_ISENSE_R_P
CPUVCORE_ISENSE_CALMIN_NECK_WIDTH=0.20 mmMIN_LINE_WIDTH=0.50 mm
ISENSE_CAL_EN_5V
=PP5V_S0_ISENSECAL
ISENSE_CAL_EN ISENSE_CAL_EN_5V_R
=PPVCORE_S0_CPU
IMVP6_VO IMVP6_CPU_ISENSE_N
GND_SMC_AVSS
SMC_CPU_ISENSE
IMVP6_DROOP
GND_SMC_AVSS
PBUS_S0_SMC_VSENSE=PPVIN_S5_CPU_IMVP
PBUS_SMC_VSENSE_EN_L
IMVP6_CPU_ISENSE_P
SMC_PBUS_VSENSE
CPU_ISENSE_OUT_R
=PPVCORE_S0_NB_GFX SMC_GPU1_VSENSE
GND_SMC_AVSS
GND_SMC_AVSS
SMC_CPU_VSENSE=PPVCORE_S0_CPU
66C2
66C2
66C2
66C2
66B1
66B1
66B1
66B1
62C2
62C2
62C2
62C2
61C5
61C5
61C5
61C5
60B2
60B2
60B2
60B2
48B3
48C6
48C1
48C6
48C6
48B5
11D7
48B1
48B1
59D8
21C5
48C1
48C1
11D7
10D7
48A1
48A1
59D4
17D5
48B1
48A1
10D7
10B5
59B6
45B6
59C7
59B6
45B6
59C2
17B7
45B6
45B6
44C5 10B5
7C4
7A7
44B8
7D7
59A4
44C1
44C5
59A4
44C1
7B1
45A5
44C5
7B7 44A2
44C1
44C1
6B2 7D7
IO
IO
IO
IO
OUT
IN
VDD
SMDATA
SMCLK
GND
DP1
DN1
DP2
DN2
VDD
SMDATA
SMCLK
GND
DP1
DN1
DP2
DN2
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR
CPU TEMPERATURE ZONE
(TO CPU INTERNAL THERMAL DIODE)
ADDR= 1001 100B
NEXT TO U5500
10 MIL SPACING
LAYER.CPU_THERMD_N
FOR CPU_THERMD_P AND
ADD GND GUARD TRACE
LAYOUT NOTE:LAYOUT NOTE:
PLACE C5511
ADDR= 1001 100B
PLACE C5501 NEAR U5500 VDD
PLACE C5522 NEAR U5520 VDD
CPU_THERMD_N ON SAME
10 MIL TRACE
ROUTE CPU_THERMD_P AND
1. ROUTE DXP AND DXN DIFFERENTIALLY
HEAT-PIPE/FIN-STACK TEMPERATURE ZONE
3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR1. ROUTE DXP AND DXN DIFFERENTIALLY
TEMP DIODE JUNCTIONSCONNECTOR DRIVES TWO
518S0521
(WRITE: 0X98 READ: 0X99)
PLACE C5501 NEXTTO U5500 VDD
2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR1. ROUTE DXP AND DXN DIFFERENTIALLY
3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD
NEXT TO U5500PLACE C5510
PLACE UNDER J3101PLACE C5524 NEXT TO Q5520
2. ROUTE GROUNDED GAURD TRACES AROUND THE DXP/DXN DIFF PAIR1. ROUTE DXP AND DXN DIFFERENTIALLY
3. 10 MIL TRACE WIDTHS AND 10MIL SPACING BETWEEN THE GAURD
(Write: 0x98 Read: 0x99)
J5550
5
6
1
2
3
4
M-RT-SM78171-0004
CRITICAL
C55241
2
NOSTUFF
CERM402
50V10%0.0022UF
C55021
210%1UF6.3VCERM402
C55101
2 50V
402CERM10%0.0022UF
C55011
210%X5R
0.1UF16V402
R55241 233
5%1/16WMF-LF402C55231
2
1UFCERM10%6.3V402
C55211
210%50V
0.0022UFCERM402
C55201
2
0.0022UF10%50VCERM402
R55221 2
101%
1/16WMF-LF402
U5520
2
4
1
3
5
87
6
MSOPEMC1043-5
CRITICAL
R55231 2
101%
1/16WMF-LF402
C55221
2 X5R10%0.1UF16V402
Q5520 1
3
2
CRITICAL
BC846BM3T5GSOT732-3
R55011 2335%
1/16WMF-LF402
U5500
2
4
1
3
5
87
6
EMC1043-5MSOP
CRITICAL
C55111
210%50V
402CERM
0.0022UF
051-745549
SYNC_DATE=06/21/2006
76
01
SYNC_MASTER=GPU
TEMPERATURE SENSE
THRM_FINSTACK_P
THRM_FINSTACK_N
=PP3V3_S0_THRM_SNRPP3V3_S0_THRM_HEATPIPE_F
THRM_HEATPIPE_SMB_CLKTHRM_HEATPIPE_SMB_DATA
THRM_DIMM_DX_F_P THRM_DIMM_DX_P
THRM_DIMM_DX_F_N
THRM_DIMM_DX_N
CPU_THERMD_N
CPU_THERMD_P
THRM_CPU_SMB_CLKTHRM_CPU_SMB_DATA
=PP3V3_S0_THRM_SNRPP3V3_S0_THRM_CPU_F
THRM_HEATPIPE_N
THRM_HEATPIPE_P
49C2
49D2
6A1
6A1
7C4
47D3
47D3
6A1
6A1
9C6
9C6
47C3
47C3
7C4
6A1
6A1
D
GS
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
5V DC
518S0521
NCGND
NC
MOTOR CONTROLTACH
R56651 2
402MF-LF5%
1/16W
47K
R56601
2
47K1/16WMF-LF
402
5%
R5661 1
2
100K
402MF-LF1/16W
5% Q5660
3
12
SOD-VESMSSM3K15FV
J5601
5
6
1
2
3
4
M-RT-SM78171-0004
CRITICAL
051-745576
SYNC_MASTER=ENET
50
01
SYNC_DATE=11/10/2005Fan
=PP3V3_S0_FAN_RT
FAN_RT_TACH
=PP5V_S0_FAN_RT
SMC_FAN_1_TACH
SMC_FAN_1_CTLFAN_RT_PWM
7C4
7A7
44A8
44A8
6D2
6D2
6D2
6D2
6D2
6D2
TEST
S0
S1
PS
GND
NC2
NC1
OUTPUTX
NC13
NC14
OUTPUTZ
OUTPUTY
VMUX
SELF
THRMLPAD
VDD
NC
CSB
RESERVED
SCK
INT
GND
VDD
SDO
SDI
VDDIO
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
NC
NC
NCNC
7/26/2005 - CONNECTED PD PIN TO SMC’S SMS_ONOFF_L
INPUT
PAGE HISTORY
OUTPUTSMS_ACC_*_AXIS - ACCELEROMETER OUTPUT TO SCU
=PP3V3_S3_SMS - 3.3V POWER FOR SMS (STAYS ALIVE IN SLEEP)
7/26/2005 - 7/26/2005 - REMOVED BOM TABLE AND UPDATED SYMBOL TO KXM52-2050
NC
NC
+X
+Z (up)
1
Package Top
+Y
(Placed on board bottom side)Desired Orientation
5/19/2005 - FIRST REVISION OF PAGE
SMS_ONOFF_L - CONNECT TO SMC TO BE ABLE TO PUT SMS INTO LOW-POWER MODE
PAGE NOTES
SMC_ACC_SELFTEST-->is a test signal
NC
NC
Package Top
1
+Y
+Z (UP)
+X
Desired Orientation(Placed on board bottom side)
0 -->Normal operation1 -->Self test
NC
STUFF R5930 TO USE U5920STUFF R5931 TO USE U5930
C5920 1
2402X5R10%
0.1UF16V
2
1
402MF-LF1/16W5%10KR5921
U5920
4
1
1314
2
5
7
6
8
1110
9
15
3 12CRITICAL
KXPA42050DFN
C59051
2 X5R
0.033UF
40216V10%
C59061
2 X5R
0.033UF
40216V10%
0.1UF10%16VX5R402
2
C59321
R593010K5%1/16WMF-LF4022
1NOSTUFF
R593110K5%1/16WMF-LF4022
1
C593116VCERM-X5R402
2
1
0.022UF10%
BMA150U5930
CRITICAL
LGA
9
8
7
11
21
34
6
105
12
C59041
2
0.033UF
402X5R16V10%
051-74557651
SYNC_DATE=08/23/2005SYNC_MASTER=SMC
01
SMS
SMS_ACC_SELFTEST
=PP3V3_S3_SMS
SMS_ONOFF_LSMS_X_AXISSMS_Y_AXISSMS_Z_AXIS
=PP3V42_G3H_SMC
=I2C_SMS_SDASMC_SMS_INT
=I2C_SMS_SCL
=PP3V3_S3_SMBUS_SMC_MGMT45D8 45D4 45C1 44D4
47C3
7A4
44A5
44A8
44A8
44A8
7C1
47B1
44B5
47B1
7A4
SO
VDD
CE*
SCK
VSSHOLD*
SI
WP* OUTIN
IN IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
R6193 close to SB
R6114 close to u6100
R6190 close to SB
R6191 close to SB
C6100 1
2402
0.1UF16VX5R
10%
R61011
2
1/16W5%
402
3.3K
MF-LF
R61001
2
1/16W5%
402MF-LF
3.3K
R61141 2
1/16W5%
402MF-LF
15
PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100U6100
1
7
6 5
2
8
4
3
SST25VF016B
SOI
16MBIT
OMIT
CRITICAL
23C5 73A3
R61901 2
MF-LF
15
1/16W5%
402
PLACEMENT_NOTE=Place R6190 within 12.7mm of U2300
R61911 2
MF-LF402
5%1/16W
15
PLACEMENT_NOTE=Place R6191 within 12.7mm of U2300
23C5 73A3
23C5 73A3
R61931 2
15
402MF-LF
5%1/16W
PLACEMENT_NOTE=Place R6193 within 12.7mm of U2300
23C5 73A3
SYNC_DATE=04/26/2006SYNC_MASTER=WFERRY
SPI ROMs
52 76
01051-7455
SPI_SO
SPI_SI_RSPI_A_SI_R
SPI_A_SO_R
SPI_SCLK_R
SPI_CE_R_L<0> SPI_CE_L<0>
SPI_A_SCLK_R
=PP3V3_S5_ROM
SPI_A_WP_LSPI_A_HOLD_L
73A3
73A3 73A3
73A3
7D1
IN
IN
IN
IN
OUT
THRM_PAD NC
IN1
EN
IN2
OUT1
OUT2
NR/FB
GND
PORT-B-VREFO2
PORT-A-VREFO/DCVOL
PORT-E-L
THRM_PAD
AVSS1
SYNC
CD-R
PORT-F-VREFO
PORT-E-VREFO
PORT-B-VREFO
PORT-C-VREFO
PORT-B-R
PORT-B-L
PORT-E-R
PORT-H-R
PORT-H-L
PORT-G-R
PORT-G-L
JDREF
VREF
PORT-D-R
PORT-D-L
PORT-C-R
PORT-C-L
SPDIFO
PORT-F-R
PORT-F-L
DVSS
CD-GND
BEEP
AVSS2
AVDD2
AVDD1
SDATA_IN
CD-L
SENSE_A
SENSE_B
GPIO1/DMIC-L
BCLK
DVDD
NC
SPDIFI/EAPD/MIDI-I/DMIC-R
PORT-A-L
PORT-A-R
RESET*
GPIO0/DMIC-CLK
SDATA_OUT
DVDD_IO
REV B3
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
APPLE P/N 353S1576AUDIO 4.5V REGULATOR
VOUT=1.2246V*[1+(R6210/R6211)]=4.58VPLACE R6210, R6211, AND C6224 CLOSE TO U6201
AUDIO CODECAPPLE P/N 353S1538
C62081
210%16V
402X5R
CRITICAL
0.1UF
R62041 2
1/16W
402
39
MF-LF
5%
C62121
2 CERM402
0.001UF10%50V
C62061
2402
10%50VCERM
0.001UFC62031
2
0.001UF
402
50VCERM
10%
C6207
2 50V20%
CERM402
0.001UF
L6201
1 2
FERR-220-OHM
0402
R62051
2
1/16W
402
1%
MF-LF
20.0K
C62001UF
1
2402
10%
CRITICAL
6.3V
C6205 1
2
150UF6.3V20%
POLY
CRITICAL
CASE-B2
C6204 1
220%
POLY6.3V
CASE-B2
150UF
CRITICAL
L6200
1 2
FERR-220-OHM
0402
C6221 1
26.3VX5R
CRITICAL
603
10UF20%
R62021 2
MF-LF
5%1/16W
1K
402
C62201
216VX5R
10%
402
0.1UF
R62001 2
NO STUFF
0
1/16WMF-LF402
5%
C62231
2402
0.001UF10%50VCERM
L6202
1 2
0402
R62111
2
1%
MF-LF
29.4K1/16W
402
R62101
2 402
80.6K
MF-LF
1%1/16W
R62061 2
5%1/16WMF-LF402
39
R62091
2MF-LF1/16W
100K5%
402
U6201
8
6
1
2
7
5
3
4
9
LREG_TPS79501DRBSON
27
U6200
2538
26
42
6
12
1918
20
1 9
4 7
23
4037
3941
33
2122
28
32
2324
29
3536 14
1531
161730
4344
4546
11
85
1334
4748
10
49
ALC885Q-VB3-GRQFN
CRITICAL
R62711
2
5%1/16W
402
10K
MF-LF
2
R62701NO STUFF
5%1/16WMF-LF402
100K
C62241
2 CERM402
5%15PF50V
C6210 1
216VTANTSMA-LF
CRITICAL
10%3.3UF
C62011
2 CERM50V10%
402
0.001UF
R62031
2
5%
402MF-LF1/16W
100K
R62011
2
1/16W
402
NO STUFF
05%
MF-LF
AUDIO: CODEC
SYNC_MASTER=M70AUDIO
051-745576
01
53
MIN_NECK_WIDTH=0.20MMVOLTAGE=3.3V CODEC_DVDD
AUD_CODEC_VREF
NO_TEST NC_AUD_BI_PORT_H_RNO_TEST NC_AUD_BI_PORT_H_L
AUD_BI_PORT_G_RNO_TEST NC_AUD_BI_PORT_G_L
AUD_BI_PORT_B_RAUD_BI_PORT_B_LAUD_VREF_PORT_B
AUD_VREF_PORT_A
AUD_REG_SHDN_L
NC_VRPNO_TEST
AUD_BI_PORT_D_R
NO_TESTNC_BAL_IN_L
ACZ_RST_L
AUD_BI_PORT_C_R
=PP3V3_S0_AUDIO
=GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.30 MM
VOLTAGE=5V=PP5V_S0_AUDIO
MIN_NECK_WIDTH=0.20 MM
BEEP
AUD_GPIO_0
ACZ_BITCLK
AUD_BI_PORT_C_L
=GND_AUDIO_CODEC
AUD_BI_PORT_A_L
NC_AUD_VREF_PORT_FNO_TEST
NC_AUD_BI_PORT_F_RNO_TEST
AUD_SENSE_B
AUD_SPDIF_OUT
AUD_SENSE_AAUD_SPDIF_I
AUD_BI_PORT_A_R
AUD_4V5_REG_IN
4V5_REG_FB
PP4V5_AUDIO_ANALOG
NC_AUD_BI_PORT_F_LNO_TEST
MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.40MM
PP4V5_AUDIO_ANALOGVOLTAGE=4.5V
AVDD_ADC_DACMIN_NECK_WIDTH=0.20MM
AUD_GPIO_1
ACZ_SYNCCODEC_DVDD
ACZ_SDATAIN<0>
AUD_SPDIF_O
MIN_LINE_WIDTH=0.30MMMIN_NECK_WIDTH=0.20MM
=PP3V3_S0_AUDIOVOLTAGE=3.3V
NO_TEST NC_AUD_BI_PORT_E_R
NO_TESTNC_BAL_IN_R
NO_TEST NC_AUD_VREF_PORT_E
NO_TEST NC_AUD_BI_PORT_E_L
NO_TESTNC_BAL_IN_COM
NO_TEST NC_AUD_VREF_PORT_CNO_TEST NC_AUD_VREF_PORT_D
AUD_CODEC_JDREF
AUD_BI_PORT_D_L
=GND_AUDIO_CODECMIN_NECK_WIDTH=0.20 MMVOLTAGE=0V
MIN_LINE_WIDTH=0.30 MM
CODEC_SDATA_IN
ACZ_SDATAOUT
CERM
1
FERR-220-OHM
OMIT OMIT
56C4
56C4
56C4
56B8
56B8
56B8
56B5
56B5
56B5
56B4
56B4
56B4
56B1
56B1
56B1
56A8
56A8
56A8
56A4
56A4
56A4
55B3
55B3
55B3
54C8
54C8
54C8
54B8
54B8
54B8
56B5
54A8
54A8
56B5
54A8
55D8
53D3
56C4
53B7
55D8
53D3
8A5
53D7
53B7
7A7
8A5
53A7
56C8
8A5
8A5
53A7
53A7
8A5
53C8
54A8
56A4
56A4
56B4
56C2
54C8
6C1
56A1
7C4
8B4
6D1
54A8
6C1
56B1
8B4
56C4
56C8
55D3
56A8
55B3
56C4
53D3
53A3
6C1
53D6
6D1
7C4
54B8
8B4
6D1
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
GND PGND
VDD PVDD
IN-
IN+
SYNC
OUT-
OUT+
SHDN*
THRMLPAD
GND PGND
VDD PVDD
IN-
IN+
SYNC
OUT-
OUT+
SHDN*
THRMLPAD
GND PGND
VDD PVDD
IN-
IN+
SYNC
OUT-
OUT+
SHDN*
THRMLPAD
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
SATELLITE & SUB TWEETER AMPLIFIER APN:353S1595
169 HZ < FC < 282 HZ
80 HZ < FC < 132 HZ
12DB
SATELLITE
GAIN
RIGHT SATELLITE
SUB-TWEETER
LEFT SATELLITE
SUB
R66101
2
5%
402
10K1/16WMF-LF
C66101 2
CRITICAL
0.047UF
10%
X7R402
16V
C66201 2
402
CRITICAL
0.047UF
X7R16V10%
C6631 1
2
0.1UF
X5R
CRITICAL
10%
402
16V
L6611
1 2
0402
FERR-1000-OHM
53C7
53C7
53C7
C6607 1
26.3V10%
402CERM
1uF
R6600
402
5%
MF-LF1/16W
0
L6620
1 2
FERR-1000-OHM
0402
L6610
1 2
FERR-1000-OHM
0402
6B1 55C2
6B1 55C2
6B1 55C2
6B1 55C2
C6606 1
2402
CERM
10%1UF6.3V
6A1 55C2
6A1 55C2
C66301 20.1UF
X5R402
16V
CRITICAL
10%
L6630
1 2
0402
FERR-1000-OHM
53B2
C6621 1
2402
0.047UF16V
CRITICAL
10%
X7R
C6609 1
2CERM
10%6.3V
1uF
402
C66051
220%
CASE-B2
120UF6.3VPOLY
CRITICAL
U6630
4
3
2
9
8
7
10
56
11
1
TDFN1
CRITICAL
MAX9705
U6610
4
3
2
9
8
7
10
56
11
1
TDFN1MAX9705
CRITICAL
U6620
4
3
2
9
8
7
10
56
11
1
TDFN1MAX9705
CRITICAL
C6611 1
2402
0.047UF
CRITICAL
16V10%
X7R
C6608 1
2402
6.3VCERM
10%1uF
C6602 1
2402
CERM
10%1UF6.3V 2
R66011
2
5%100
MF-LF1/16W
402
C66031
2
CASE-B3-SM
CRITICAL
47UF
POLY6.3V20%
C6604 1
2402
CERM
10%1UF6.3V
R666012
1/16WMF-LF
5%
402
0
R666112
1/16W
0
402
5%
MF-LF
R667012
1/16WMF-LF
5%
402
0
R667112
1/16W
0
402
5%
MF-LF
R668012
1/16WMF-LF
5%
402
0
R668112
0
402
5%
MF-LF1/16W
R66021
2
1/16WMF-LF
1005%
402
XW66001 2
SM
051-7455
SYNC_MASTER=M70AUDIO
AUDI0: SPEAKER AMPSYNC_DATE=03/12/2007
7654
01
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=5VMIN_LINE_WIDTH=0.60 MM
=PP5V_S0_AUDIO_AMP
AUD_BI_PORT_D_R AUD_SPKRAMP_INR
=GND_AUDIO_CODEC
PP5V_S0_AUDIO_FVOLTAGE=5VMIN_LINE_WIDTH=0.30 MMMIN_NECK_WIDTH=0.20 MM
=GND_AUDIO_CODEC
AUD_SPKRAMP_SHUTDOWN_L
MAX9705_SUB_N
=GND_AUDIO_AMP
=GND_AUDIO_AMP
PP5V_S0_AUDIO_F
SPKRAMP_THERMPLANE
=GND_AUDIO_AMP
=PP5V_S0_AUDIO_AMP
=PP5V_S0_AUDIO_AMP
PP5V_S0_AUDIO_F
AUD_SPKRAMP_INSUB_L AUD_SPKRAMP_INSUB
SPKRAMP_SYNC1
=GND_AUDIO_AMPMIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.60 MM
SPKRAMP_THERMPLANE
MIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 MMSPKRAMP_L_P_OUT
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 mm
SPKRCONN_R_P_OUT
MIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 MMSPKRAMP_R_P_OUT
MIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 MMSPKRCONN_L_P_OUT
MIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 MMSPKRAMP_SUB_P_OUT
MIN_LINE_WIDTH=0.30 mm
SPKRCONN_SUB_P_OUTMIN_NECK_WIDTH=0.20 MM
SPKRCONN_R_N_OUT
MIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mmMIN_NECK_WIDTH=0.20 MMSPKRCONN_L_N_OUT
MIN_NECK_WIDTH=0.20 MMSPKRCONN_SUB_N_OUT
MIN_LINE_WIDTH=0.30 mm
SPKRAMP_THERMPLANE
MIN_NECK_WIDTH=0.20 MMSPKRAMP_L_N_OUT
MIN_LINE_WIDTH=0.30 mm
MIN_LINE_WIDTH=0.30 mm
SPKRAMP_SUB_N_OUTMIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 mm
SPKRAMP_R_N_OUTMIN_NECK_WIDTH=0.20 MM
AUD_BI_PORT_D_L
SPKRAMP_SYNC2
SPKRAMP_SUB_P_OUT
AUD_GPIO_0
AUD_BI_PORT_G_R
SPKRAMP_SYNC1
MAX9705_L_N
AUD_SPKRAMP_INL
MAX9705_R_N
AUD_SPKRAMP_INR_L
AUD_SPKRAMP_INL_L
AUD_SPKRAMP_SHUTDOWN_L
AUD_SPKRAMP_SHUTDOWN_L
SPKRAMP_SUB_N_OUT
=GND_AUDIO_CODEC
CRITICAL
C6601
POLY
SPKRAMP_R_P_OUTSPKRAMP_R_N_OUT
SPKRAMP_THERMPLANE
SPKRAMP_L_P_OUT
SPKRAMP_SYNC2SPKRAMP_L_N_OUT
CASE-B3-SM
6.3V20%47UF
1
OMIT
OMIT
OMIT
56C4
56C4
56C4
56B8
56B8
56B8
56B5
56B5
56B5
56B4
56B4
56B4
56B1
56B1
56B1
56A8
56A8
56A8
56A4
56A4
56A4
55B3
55B3
55B3
54B8
54C8
54C8
54A8
54B8
54A8
54C8
53D3
53D3
54C8
54B8
54C8
54D8
54D8
54C8
53D3
54B8
53B7
53B7
54B8
54A8
54A8
54B8
54C8
54B8
54C4
54C4
53B7
7A7
53A7
54C8
53A7
54C8
54A5
54A5
54C4
54C4
54A5
7A7
7A7
54C8
54A8
54B4
54B4
54B4
54C8
54B8
53A7
6D1
8B4
54B8
8B4
54B8
8A4
8A4
54B8
54A4
8A4
6D1
6D1
54C4
54C4
8A4
54A4
54B4
54D3
54C4
54A4
54A4
54B4
54A4
54C4
54B4
54B3
54A4
54A6
54A6
54B3
54C3
8B4
54A4
54C3
54A4
54C3
IN
IN
IN
IN
IN
IN
VCCGNDVOUT
SHLD_PIN
SHLD_PIN
VINGNDVCC
SHLD_PIN
SHLD_PIN
OUT
OUT
OUT
BI
BI
OUT
IN
BI
BI
OUT
OUT
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
APN:514-0458
APN:514-0459
AUDIO JACK 2: LINE IN CONNECTOR, SPDIF RX
AUDIO JACK 1: LO/HP CONNECTOR, SPDIF TX
APN:518S0521
APN:518S0519
SPEAKER CONNECTOR
MIC EMI FILTER
MIC CONNECTORAPN:518S0392
L6700
1 2
FERR-120-OHM-1.5A
0402-LF
L6702
1 2
FERR-1000-OHM
0402
L6703
1 2
FERR-1000-OHM
0402
1
L6705
2
FERR-1000-OHM
0402
L6707
1 2
FERR-1000-OHM
0402
C67001
2402CERM6.3V
1UF10%
6A1 54B1
6A1 54B1
6B1 54D1
6B1 54C1
XW67001 2
SM
XW67011 2
SM
R67491 2
MF-LF1/16W5%
402
10
C67511
2 X5R
10uF20%
603
6.3V
L6790
1 2
FERR-220-OHM
0402
6B1 54C1
6B1 54C1
1/16W
R67911 2
402
0
5%
MF-LF
F-RT-TH
3
4
6
9
10
7
8
1
5
2
AUDIO-IN-MG3-M71
OMIT
CRITICAL
J6750
XW67051 2
SM
J6701
4
5
1
2
3
CRITICAL
M-RT-SM148227-0301
2
3
4
5
1
7
6
9
10
8
F-RT-TH
OMITCRITICALJ6700
AUDIO-OUT-M71-MG3
J6703
5
6
1
2
3
4
M-RT-SM78171-0004
CRITICAL
J6702
3
4
1
2
78171-0002
CRITICAL
M-RT-SM
L6770
1 2
FERR-1000-OHM
0402
L6772
1 2
FERR-1000-OHM
0402
6B1 56A6
6B1 56A6
L6750
1 2
FERR-120-OHM-1.5A
0402-LF
L6751
1 2
FERR-120-OHM-1.5A
0402-LF
R67401
2MF-LF1/16W
402
5%0
L6771
1 2
FERR-1000-OHM
0402
L6773
1 2
0402
FERR-1000-OHM
DZ6770
1
2
6.8V-100PF
CRITICAL
402
DZ6771
1
2
CRITICAL
6.8V-100PF402
DZ6702
1
2
402
CRITICAL
6.8V-100PF
DZ6704
1
2
6.8V-100PF
CRITICAL
402
DZ6705
1
2CRITICAL
4026.8V-100PF
DZ6703
1
2
402
CRITICAL
6.8V-100PF
DZ6753
1
2
4026.8V-100PF
CRITICAL
DZ6752
1
2
6.8V-100PF402
CRITICAL
L6754
1 2
FERR-1000-OHM
0402
DZ6754
1
2
402
CRITICAL
6.8V-100PF
DZ6755
1
2CRITICAL
4026.8V-100PF
NO STUFF
DZ67001 3
2 4
04055.6V-15A
DZ6701
1 3
2 404055.6V-15A
NO STUFF
DZ67501 3
2 4
NO STUFF
5.6V-15A0405
DZ6751
1 3
2 4
NO STUFF
5.6V-15A0405
L6756
1 2
FERR-1000-OHM
0402
R67501 2
MF-LF402
10K
5%1/16W
R67511 2
MF-LF
4.7
402
5%1/16W
C67561
2
100PF5%50V
402CERM
L6755
1 2
FERR-1000-OHM
0402
L6753
1 2
0402
FERR-1000-OHM
L6752
1 2
FERR-1000-OHM
0402
L6757
1 2
FERR-1000-OHM
0402
C67501
2
1UF10%
402
6.3VCERM
53C2
56A2
56B2
56A8
53C2
56C1
56C1
L6701
1 2
FERR-120-OHM-1.5A
0402-LF
L6704
1 2
FERR-1000-OHM
0402
L6706
1 2
0402
FERR-1000-OHM
56B6 56B8
56C8
R67001 2
5%
10K
402MF-LF1/16W
R67011 2
1/16W5%
MF-LF402
4.7
C67051
25%
402CERM50V
100PF
514-0479 CONN, 3.5MM COMBO AUDIO OUT, RA, BLACK, LF CRITICALJ6700 FANCY1
514-0478 1 CONN, 3.5MM COMBO AUDIO IN, RA, BLACK, LF J6750 CRITICAL FANCY
514-0458 CRITICAL1 J6750 NORMALCONN, 3.5MM COMBO AUDIO IN, RA, MG3, LF
514-0459 CONN, 3.5MM COMBO AUDIO OUT, RA MG3, LF1 CRITICALJ6700 NORMAL
AUDIO: JACK
051-745555
01
76
SYNC_DATE=03/12/2007SYNC_MASTER=M70AUDIO
AUD_SPDIF_OUT
CHASSIS_AUDIO_JACK_ISOL
AUD_CONNJ1_SLEEVEDET
AUD_CONNJ1_TIP
AUD_CONNJ1_RING
AUD_CONNJ1_SLEEVE
AUD_CONNJ1_TIPDETAUD_CONNJ1_TIPDET_F
MIC_LO
AUD_J2_COM
AUD_CONNJ2_SLEEVE_F
AUD_CONNJ2_TIPDET_F
AUD_J1_TIPDET_R
MIC_LO_CONN_F
MIC_HI_CONN_F
CHASSIS_AUDIO_JACK_ISOLAUD_J2_TIPDET_R
AUD_CONNJ2_SLEEVEDET_F
CHASSIS_AUDIO_JACK_ISOL
AUD_CONNJ2_TIP_F
AUD_CONNJ1_SLEEVEDET_F
AUD_J1_COM
AUD_CONNJ1_TIP_F
AUD_PORTC_R
AUD_SPDIF_I
MIC_SHLD_CONN
MIC_HI
CHASSIS_AUDIO_JACK_ISOL
MIC_HI_CONN
SPKRCONN_L_N_OUT
AUD_CONNJ1_SLEEVE_F
SPKRCONN_SUB_P_OUT
AUD_PORTA_R
AUD_PORTA_L
AUD_J1_SLEEVEDET_R
=PP3V3_S0_AUDIO
SPKRCONN_R_N_OUT
SPKRCONN_SUB_N_OUTSPKRCONN_R_P_OUT
MIC_SHLD_CONN
SPKRCONN_L_P_OUT
MIC_LO_CONN
GND_AUDIO_SPDIF_DGND
AUD_J2_OPT_OUT
PP3V3_S0_AUDIO_SPDIF
AUD_CONNJ2_TIPDET
AUD_CONNJ2_SLEEVE
AUD_CONNJ2_RING
AUD_CONNJ2_TIPAUD_CONNJ2_RING_F
AUD_CONNJ2_SLEEVEDET
GND_AUDIO_SPDIF_DGND
=GND_CHASSIS_AUDIO_JACK
AUD_PORTC_L
MIC_LO_CONN
MIC_HI_CONN
AUD_CONNJ1_RING_F
=GND_AUDIO_CODEC
PP3V3_S0_AUDIO_SPDIF
56C4 56B8 56B5 56B4 56B1 56A8 56A4 54C8 54B8 54A8
56B5
53D3
55C1
55C8
55C8
56A6
55C8
53D7
56A6
53B7
55A8
55C1
55C1
55D3
55A8
55B1
53A7
55A1
55B1
55D3
55D3
53A7
55A3
55A8
55A3
6B1
55A3
6B1
7C4
6B1
6B1
55A8
55D8
55C8
8D8
6B1
6B1
8B4
55B8
IN
OUT
OUT
INOUT
IN
IN
IN
IN
OUT
IN
IN
D
G S
D
SG
D
SG
D
SG
D
SG
OUTLINR
INL OUTR
SHDN*
CEXT
VCC
GND PADTHM
IN
OUTIN
IN OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
HP OUT
0X1A (26,PORTC)VREF_B (80%)
0X06 (6)0X04 (4)
0X15 (21,PORTA)
VREFN/A
N/AN/A
N/A
DET ASSIGNMENT
0X1F (31,SPDIF IN)0X18 (24,PORTB)0X1A (26,PORTC)
0X0A (10)0X07 (7)0X08 (8)CONVERTER PIN COMPLEX
N/A
VOLUME0X08 (8)0X07 (7)
N/A
0X08 (8)0X07 (7)
MUTE CONTROL
0X24 (36)0X23 (35)
CODEC INPUT SIGNAL PATHSMIXER
N/A
0X1B (27,PORTE)
0X26 (38)VREF_A(100%)
GPIO 0
MUTE CONTROL
N/A
GPIO 0N/AN/A
DET ASSIGNMENT
0X1E (30,SPDIF OUT)
0X14 (20,PORTD)0X16 (22,PORTG)
0X15 (21,PORTA)0X25 (37)0X05 (5)
0X0E (14)SUB SPKRSAT SPKR
FUNCTION
SPDIF OUT
PORT C LI
NC
NC
NC
SPDIF IN
LINE IN
Line-in (PORT C) DETECT
PORT A HP/LO
MIC INPUT CIRCUITRY
PLACE C6852 NEAR U6200
N/A
PORT A DETECT
PLACE L6800/C6800 CLOSE TO Q6800
PORT E DETECT(SPDIF DELEGATE)
FUNCTION
CONVERTER PIN COMPLEXVOLUME
MIC IN
0X0F (15)
CODEC OUTPUT SIGNAL PATHS
APN:353S1459HP/LO DE-POP SWITCH
C68011
2 40210%X5R
16V0.1UF
R68021 2
47K
1/16WMF-LF402
5%
1 2
20%6.3VPOLYB2
100UF
C6831
1 2
CRITICAL
B2
6.3V20%
100UF
POLY
53C2
55C3
55C3
53C2 53C2 56A8
55C3
C6850
1 2
16V402
10%
0.1uF
CRITICALX5R
R68531 2
NO STUFF
MF-LF1/16W
5%
402
0
XW6800
1 2
SM
R68541 2
0
NO STUFF
5%1/16W
402MF-LF
R6855
1 2
2.2K
1/16W 5%402MF-LF
R68521
2 402
100K5%
MF-LF1/16W
R6851
1 2
4025%1/16W
MF-LF
330
C6851 1
2
CRITICAL
402CERM50V10%
680PF
6B1 55B3
6B1 55B3
6B1 55A1 55D3
C68001
2
10%
402
0.1UF
X5R16V
L6800
1 2
FERR-1000-OHM
0402
R68061
2
39.2K
MF-LF
1%1/16W
402
R68031 2
MF-LF402
5%
100K
1/16WR68611
2
1/16W5%
MF-LF402
270K
C68021
2
0.01UF
402
16V10%
CERM
53C2
55C3 56B6
R68131
2402
5%1/16WMF-LF
10K
C68111
210% 16VX5R
0.1UF
402
1 2
1/16W
47K
MF-LF
5%
55A3
C68351
216V
0.1UF
402X5R
10%
C6852 1
2402
CRITICAL
CERM
5%50V
NO STUFF100PF
R6850
1 2
1/16WMF-LF
6.81K
4021%
C68361
2402
10%1UF
6.3VCERM
C68531
2603X5R
10UF
6.3V20%
CRITICAL
Q68023
12
SOD-VESM
SSM3K15FV
Q6800 3
54
SSM6N15FESOT563
Q6800 6
21
SSM6N15FESOT563
Q6801 3
54
SSM6N15FESOT563
Q6801 6
21
SOT563SSM6N15FE
C6832
12
3.3UF
CRITICAL
TANTSMA-LF
10%16V
C6833
12
CRITICAL
3.3UF
10%16VTANT
SMA-LF
R68051
2
39.2K
1/16W
402
1%
MF-LF
U6801
MAX9890BETA+
TDFN
CRITICAL
R68391
2MF-LF402
10K
1/16W5%
53C2
R68011
2
270K
402MF-LF
5%1/16W
R68111
2MF-LF
270K
402
5%1/16W
53C7 55B3
R6836 1
2
27.4K1%
402MF-LF1/16W
55B3
R6837 1
2402
27.4K1%
1/16WMF-LF
53C7
R6835 1
2
27.4K1%
1/16WMF-LF402
R6834 1
2402
27.4K1%
1/16WMF-LF
R68561 2
NO STUFF
MF-LF
0
402
1/16W5%
SYNC_MASTER=M70AUDIO
AUDIO: JACK TRANSLATORS
051-74557656
01
SYNC_DATE=03/12/2007
=GND_AUDIO_CODEC
AUD_PORTC_L
AUD_PORTC_R AUD_BI_PORT_C_R
AUD_BI_PORT_C_L
AUD_PORTA_DET_L
=GND_AUDIO_CODEC
=GND_AUDIO_CODEC
AUD_INJACK_INSERT_L
AUD_J2_DET_RC
MAX9890_CEXT
PP3V3_S0_AUDIO_F
AUD_J2_TIPDET_R
PP3V3_S0_AUDIO_F
AUD_SENSE_A
AUD_PORTA_L
PP3V3_S0_AUDIO_F
AUD_BI_PORT_B_LMAKE_BASE=TRUE
AUD_BI_PORT_B_R
VREF_PORT_B_R
MAX9890_OUTR
AUD_BI_PORT_A_R
AUD_VREF_PORT_A
AUD_BI_PORT_A_L
MIC_IN
=GND_AUDIO_CODEC
=PP3V3_S0_AUDIO
AUD_J1_TIPDET_R
=GND_AUDIO_CODEC
AUD_J1_SLEEVEDET_R
AUD_J1_SLEEVEDET_R
AUD_PORTE_DET_L
AUD_SENSE_B
AUD_OUTJACK_INSERT_L
AUD_VREF_PORT_B
=GND_AUDIO_CODEC
MAX9890_OUTL
AUD_PORTA_R
=GND_AUDIO_CODEC
=PP5V_S0_AUDIO
PP3V3_S0_AUDIO_F
=GND_AUDIO_CODEC
AUD_SENSE_A
MIC_HI
MIC_SHLD_CONN
=GND_CHASSIS_AUDIO_MIC
MIC_LO
AUD_J1_SLEEVEDET_INV
AUD_J1_DET_RC
R6812
402
C6830CRITICAL
OMIT
OMIT
56C4
56C4
56C4
56C4
56C4
56B8
56B8
56C4
56B8
56C4
56B8
56B8
56B8
56B5
56B5
56B8
56B5
56B8
56B5
56B4
56B5
56B4
56B4
56B5
56B4
56B5
56B4
56B1
56B4
56B1
56B1
56B1
56B1
56B4
56A8
56A8
56B1
56A8
56A8
56A8
56A8
56B1
56A4
56A4
56A4
56A4
56A4
56A4
56A4
56A8
55B3
55B3
55B3
55B3
55B3
55B3
55B3
55B3
54C8
54C8
54C8
54C8
54C8
54C8
54C8
54C8
54B8
54B8
54B8
54B8
54B8
54B8
54B8
54B8
54A8
54A8
54A8
54A8
54A8
54A8
54A8
54A8
53D3
53D3
53D3
53D3
55D8
53D3
53D3
53D3
53D3
53B7
53B7
53B7
56B8
56C8
56C8
53B7
53D7
53B7
53B7
53B7
53A7
56C8
53B7
53A7
53A7
53A7
56B3
56B8
56C8
56B8
53A7
53A7
53A7
56B8
53A7
53A7
7A7
56B3
53A7
8B4
8B4
8B4
56A8
56B3
53C2
56A8
53C2
53C2
8B4
7C4
8B4
55C3
53C2
8B4
8B4
6D1
56A8
8B4
8D8
V-
V+
D SG
D
SG
D
SG
D
GS
NC
Y
B
A
G
D
S
NC
V-
V+-
+
DSG
VOID
D1
D3
D4S3S2
GATE
S1D2
TABLE_ALT_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
ACIN DETECTIONNC
OVP
PIN 1
MLB TOP VIEW
NCNC
BATTERY INTERFACE
INRUSH LIMITER518S0526
LID HALL EFFECT SENSOR
DC-JACK INTERFACE
R69321
2
24.3K1%1/16WMF-LF402 C69301
210%
402X5R25V0.1UF
R69331
2MF-LF
100K5%
4021/16W
R69311
2
5%100K
402MF-LF1/16WU6990 2
4
1
3
5
CRITICAL
LM397SOT23-5
J6900
1
2
3
4
5
M-RT-SM87438-0563
CRITICAL
R69001
2 402MF-LF1/16W100K5%
C69031
2402CERM50V0.001UF10%
R69011
2
1%1/16WMF-LF402
1KR69031
2
5%10K1/16WMF-LF402
R69041
2 1/16W47K5%
402MF-LFD6900
3
1
2
CRITICAL
RCLAMP2402B
SC-75
R69111 2
1/16W5%
402MF-LF
100K
R6905
1 2
475%1/8W
805MF-LF
R6902
1 2
1K1/16WMF-LF5%
402
C69071
2
0.001UF50VCERM10%
402
Q6920
6
2
1
SOT563SSM6N15FE
Q69106
2 1
SOT563SSM6N15FE
Q69103
5 4
SOT563SSM6N15FE
Q69993
12
SOD-VESMSSM3K15FV
D6901
1
3
5
4
2
SOT665HN2D01JEF
CRITICAL
R69401 2
805MF-LF
475%1/8W
U6950
2
1
3
5
4
SOT665
CRITICALTC7SZ08AFEF
Q6940 3
1
2
NTK3142PSOT723-3
U69004
6
3
1
5
2
SC70TLV7211
CRITICAL
Q6920
3
54
SOT563SSM6N15FE
L6901
1 2
FERR-50-OHMSM-LF
L6902
1 2
120-OHM-0.3A-EMI0402-LF
L6903
1 2
0402-LF120-OHM-0.3A-EMI
L6904
1 2
0402-LF120-OHM-0.3A-EMI
L6905
1 2
SM-LFFERR-50-OHM
C69061
2 CERM50V5%47pF
402
C69151
2 CERM50V5%47pF
402
C69091
2402CERM50V10%0.001UF
C69051
2
0.001UF10%
CERM402
50V
C69111
2402
10%
CERM50V
0.001UF
J6950
1
10
1112
1314
1516
1718
19
2
20
34
56
78
9
F-ST-SM
CRITICAL
127216FA020
L6909
1 2
600-OHM-300MA0402
L6907
1 2
600-OHM-300MA0402
C69211
2402CERM16V
0.01uF10%
L6908
1 2
600-OHM-300MA0402
C69201
2402
10%0.01uF16VCERM
C69181
210%25V0.1UF
402X5R
R69081
2
1%102K
402MF-LF1/16W
R6910
1 2
1M1/16WMF-LF402
5%R69091
2MF-LF
1%51.1K1/16W
402
R69071
2
10.7K
MF-LF1/16W1%
402
R69061
2MF-LF
102K
402
1/16W1%
R69141
2
330K5%1/16WMF-LF402
R69131
2
470K5%
MF-LF402
1/16W
C69171
2
0.22UFX5R25V603
20%
Q6950
5
6
7
8
4
1
2
3
CRITICAL
AO4409SOI
C69021
2
0.01uFX7R402
25V10%
F6900
1 2
6AMP-24V
CRITICAL
1206-1
?376S0543 AOS MOSFETQ6950376S0466
SYNC_DATE=07/13/2005SYNC_MASTER=POWERDC-In & Battery Connectors
57 76
051-7455 01
TI & NATIONAL353S1717 ?353S1297 U6990
VOLTAGE=18.5V
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=2 MM
PP18V5_DCIN_F
SMC_BC_ACOK
VOLTAGE=18.5VMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.20 MM
=PP18V5_G3H_INRUSH
SMC_ADAPTER_EN
ACIN_1V20_REF
ACIN_DIV
PPVBATT_G3H_RBATT_POS_F
=PPDCIN_G3H
SYS_ONEWIRE
SMC_BC_ACOK_ONEWIRE_R
ACIN_ENABLE_L
SYS_ONEWIRE_BILAT
ONEWIRE_EN
ONEWIRE_PWR_EN_L
ONEWIRE_PWR_EN_L_DIV=GND_DCIN_CHGND
PP18V5_DCIN_ONEWIRE
ONEWIRE_OV
ONEWIRE_ESD
ONEWIRE_DCIN_DIV
ACIN_ENABLE_GATE
ADAPTER_SENSE
SMC_BS_ALRT_L
=SMBUS_BATT_SDA
BATT_POS_F
=SMBUS_BATT_SCL
SMBUS_BATT_SDA_F
SMC_BS_ALRT_L_F
=GND_BATT_CHGND
SMBUS_BATT_SCL_F
GND_SMC_LID_F
SMC_LID_F
PP3V42_G3H_LIDSWITCH_F
=GND_BATT_CHGND
=PP3V42_G3H_LIDSWITCH
SMC_LID
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.5VPP18V5_DCIN
BATT_POS
=PP3V42_G3H_ACIN
SMC_BC_ACOK
PPDCIN_G3H_R
ACIN_ENABLE_L_DIVMIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.2 MM
BATT_NEG
45B3
66A6
44D5
66A6
57C3
38C6
45C5
66B8
57C7
45B6
35C7
45D5
45C5
44B5
66A8
45B6
44C5
33C7
66B2
44B8
66A6
44C5
66B2
57A6
57A6
42C3
66A5
44C5
6C1
7B3
6C1
57B2
7B3
6C1
8C8
6C1
6D1
47C1
57D5
47C1
6D1
8D8
6D1
8D8
7B1
6B2
6D1
7B1
6C1
6D1
NC
NC
NC
NC
UVLO_D
UVLO_C
UVLO_B
UVLO_A
RESET*
DLY_OFF_C
DLY_OFF_D
DLY_OFF_A
DLY_OFF_B
DLY_ON_D
DLY_ON_C
DLY_ON_B
DLY_ON_A
GATE_D
GATE_C
GATE_B
GATE_A
VDD
ENABLE_1
PADTHML
GND
SENSE
CT
VDD
GND
RESET*
MR*
D
SG
D
SGD
G
S
D
G
S
D
SG
D
SG
G
SD
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_ALT_ITEM
NCNC
AFTER UVLO_D VALID
33 mOhm @4.5VRDS(ON)
1.8V S0 FETCHANNEL
1.810 A33 mOhm @4.5V
LOADING
1.05V S0 RUN/SS CONTROL5V S0 FET
DEASSERTED 160MS
U7002.3 has int 90K pull-up
1.25V S0 RUN/SS CONTROLFDC655BN
FDC655BN
0.260 A 1.5V S0 RUN/SS CONTROL
FDM6296N-TYPE
4.348 A
~26MS
MOSFET
N-TYPEMOSFET
RDS(ON)
3.3V S0 FETCHANNEL N-TYPEMOSFET
NC
NC
15 mOhm @4.5VLOADINGRDS(ON)CHANNEL
LOADING
LATEST ISSUE: 2007/01/02
S0 FETS & POWER SEQUENCING & PGOOD
C7003
1 2CERM
0.0022UF10%50V
402
C7004
1 2CERM50V
0.0022UF10%
402
C7005
1 2402
50V10%0.0022UF
CERM
U7000
181334
2181615
1
2567
10
111922
9
24
25
20121714
23
CRITICAL
QFNISL6130IRZA
R70021
2
4.87K
MF-LF
1%1/16W
402
R700112
1%1/16W
402MF-LF
30.9K
R70041
2MF-LF402
7.5K1%1/16W
R70061
2
13.7K1/16W
402MF-LF
1%
C70231
210%0.022UF16V
402CERM-X5R
C70221
2
0.01UF10%
NOSTUFF
16VCERM402
C70211
210%
402CERM16V
NOSTUFF
0.01UF
C70001
2 6.3V10%
1UFCERM402
U70024
2
3
1 5
6
SOT23-6TPS3808-1.25V
CRITICAL
C70011
2
0.1UF10%16VX5R402
C70021
2
0.001UF10%50V402CERM
Q70073
5 4
SSM6N15FESOT563
R70121
2402
100K
MF-LF
5%1/16W
R700312
MF-LF402
1%1/16W
28.7K
R700512
1/16WMF-LF
1%22.1K
402
R7040
12
3305%
MF-LF1/16W
402
Q70076
2 1
SSM6N15FESOT563
R7030
12
100K5%1/16WMF-LF402
R7031
12
1/16W
402
3305%
MF-LF
C70301
210%16V
402CERM
0.01UF
R7050
12402
1/16W5%10KMF-LF
C70401
2
0.0012UF10%50VCERM402
R7051
12
1/16WMF-LF
5%330
402
C70501
2 50V0.001UF
402
10%CERM
R7041
12
100K1/16W5%
MF-LF402
C70241
2 CERM
0.01UF
402
10%16V
NOSTUFF
R70071 2
MF-LF1/16W5%47
402
Q70011
2
5
6 3
4
CRITICAL
SOT6FDC655BN
Q70041
2
5
6 3
4
CRITICAL
SOT6FDC655BN
Q70063
5 4
SSM6N15FESOT563
Q70066
2 1
SOT563SSM6N15FE
R70611
2
5%470K1/16WMF-LF402
Q7000
5
4
1
2
3
CRITICAL
MICROFET3X3FDM6296
SYNC_DATE=05/31/2006SYNC_MASTER=DSIMON-WF
S0 FETS & Power Sequencing
58
01
76
051-7455
376S0445376S0448 Q7000?
RUNSS_GATE_D
S0SEQ_BEGIN TP_DLY_ON_C
PGOOD_1V05S0
P3V3S0_EN
DLY_OFF_CDLY_OFF_D
DLY_OFF_ADLY_OFF_B
TP_DLY_ON_D
TP_DLY_ON_BTP_DLY_ON_A
=PP5V_S5_FET
ALL_SYS_PWRGD
=PP3V3_S0_FET
ALL_SYS_PWRGD_ANDMAKEBASE=TRUE
1V05S0_RUNSS
=PP3V3_S0_FET
=PP5V_S0_FET
ALL_SYSPWRGD_DLYPGOOD_1V5S0
=PP1V8_S3_FET
1V5S0_RUNSS_BUF
RUNSS_GATE_D_L
=PP5V_S5_FET
1V05S0_RUNSS_BUF
1V25S0_RUNSS_BUF
RUNSS_GATE_D_L
1V25S0_RUNSS
=PP3V3_S0_FET
=PP3V3_S0_FET
1V5S0_RUNSS
RUNSS_GATE_D_L
=PP3V3_S0_FET
=PP3V3_S0_FET
=PP3V3_S5_FET
=PP1V8_S0_FET
=PP1V25_S0_FET
PGOOD_1V8S3
PM_SLP_S3_L
S0PWRGD_5V_DIVS0PWRGD_3V3_DIVS0PWRGD_1V8_DIV
=PP1V8_S0_FET
P1V8S0_EN
P5VS0_EN
PGOOD_SEQUENCER
=PP5V_S0_FET
=PP5V_S5_FET
58D3
58D3
58D3
58D3
58D3
58C4
62B8
58C4
58C4
58C4
58C4
58C3
58C3
45A6
65B5
58C3
58C3
65B5
58C3
58B8
58B8
58B8
44C5
65B5
58D5
44D8
58B8
58B3
58D5
58B8
58B3
58B3
58B3
65C4
35C7
58C6
58B3
27A5
58B3
58A3
58D4
58C6
58C2
58A3
58A3
61B5
58C2
58A3
58A3
65A5
58C4
33C7
58B8
58C8
58B3
61A6
7C1
6B2
7D6
61B5
7D6
7A8
61A3
7B4
58C2
7C1
58B2
64B6
7D6
7D6
6D7
58B2
7D6
7D6
7D1
7B8
7C7
62A3
24D3
7B8
7A8
7C1
IN
IN
OUT
IN
OUT
IN
VID0
DPRSTP*
NC
VW
COMP
FB
FB2
RBIAS
VR_TT*
NTC
VR_ON
PGOOD
PSI*
RTN
VSEN
DFB
DROOP
VO
OCSET
VSUM
ISEN2
VID1
VID3
VID2
VID4
VID5
VID6
PGND2
VIN VDD PVCC
LGATE2
PHASE2
UGATE2
ISEN1
PGND1
LGATE1
UGATE1
PHASE1
BOOT1
BOOT2
3V3
VDIFF
SOFT
DPRSLPVR
TPADGND
CLK_EN*
IMONOUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
LATEST ISSUE: 2007/01/23
MIN_LINE_WIDTH
IMVP6 CPU VCORE REGULATOR
(IMVP6_COMP)
NOTE 1: C7132,C7133 = 27.4 OHM FOR VALIDATING CPU ONLY.
(IMVP6_VO)
PWM FREQ. = 300 kHzMAX CURRENT = 44A
MPC1055LR36DCR=0.8mOhm
(IMVP6_ISEN1)
MIN_NECK_WIDTHMIN_LINE_WIDTH
MIN_NECK_WIDTH
(IMVP6_PHASE1)
(IMVP6_ISEN2)
(IMVP6_PHASE2)
1
(IMVP6_VSUM)
(IMVP6_VO)
ERT-J1VR103J
1-Phase DCM
1-Phase CCM
0
DPRSLPVR
1
0
PSI*
0
10 1
DPRSTP*
MIN_NECK_WIDTH
1
1-Phase DCM
(IMVP6_FB)
1
2-Phase CCM
Operation Mode
0
(GND)
0
(GND)FROM SMC
ERT-J0EV474J
MPC1055LR36DCR=0.8mOhm
(IMVP6_VW)
R1100/R1101 **ON THE CPU PAGE** PROTECT THE IMVP6 IF THE CPU IS NOT INSTALLED
MIN_LINE_WIDTH
C71001
2
0.0022UF
NO STUFF
10%
CERM402
50V
XW71001
2
SM
OMIT
C71901
2
0.0022UF
CERM50V10%
402
NO STUFF R7100
1 2
MF-LF
1%
402
1/16W
10K
R71011
2
3.65K1/16WMF-LF402
1%
C71151
2
0.1UF
X5R16V
402
10%
R71161
2
1/16W1%
MF-LF
13.7K
402
R71151
2 402MF-LF1/16W
11K1%
R7105
1 2
MF-LF
1%10K1/16W
402
C7104
1 2
402
6.3VCERM-X5R
10%0.22uF
R71431
2MF-LF
3.65K
402
1%1/16W
L7101
1 2
CRITICAL
0.36UH-30A-0.80MOHMMPC1055-SM
L7100
1 2
0.36UH-30A-0.80MOHM
CRITICAL
MPC1055-SM
C71021
2
0.0022UF10%50VCERM402
NO STUFFC71921
2 50VCERM
NO STUFF
10%
402
0.0022UF
C71271
2
0.1UF
402X5R16V10%
R7120
1 2
MF-LF1/16W
402
5%10
R7112
1 2
101/16W
402MF-LF
5%
C71261
2 402
10%1UF
CERM6.3V
C71961
2
0.01UF16V10%
CERM402
R7121
1 2
MF-LF1/16W
105%
402
C71301
2 X5R16V
0.1uF
402
10%
R7113
1 2
1K
NO STUFF
MF-LF1/16W1%
402
R71091
2
1K
MF-LF1/16W1%
402 R71111
2
255
MF-LF1/16W1%
402
C71141
2 CERM50V
470PF
402
10%
R71141
2
97.6K
MF-LF1/16W1%
402
C71131
2
220PF5%25V
402CERM
C71071
2
10%
CERM50V
0.001UF
402
R71101
2 402
1%1/16WMF-LF
6.81K
R7117
1 2
402
4.32K1%1/16WMF-LF
R71181
2
1/16W
402
1%1K
MF-LF
C71291
2 50V5%
402CERM
180pF
C71281
2 402
0.22UF6.3V10%
CERM-X5R
C7131
1 2
10%0.068UF
402CERM10V
C7132
1 2
NO STUFF
0.01UF10%16V
402CERM
C7133
1 2
X7R402
10%16V
0.018UF
R71221
2 402
5%01/16WMF-LF
R71231
2402
5%01/16WMF-LF
C71341
2
10%
X5R16V
402
0.033UF
C71351
2 X5R
10UF6.3V20%
603
R7127
1 2402
1%1/16WMF-LF
4.02K
NO STUFF
C7110
1 2
CERM
0.01uF
NO STUFF
16V
402
10%
C7105
1 2
0.015uF
16V10%
402X7R
R7108
1 2
147K
402
1%1/16WMF-LF
C71061
2
0.001UF50VCERM402
10%
C71161
2
NO STUFF
50V10%
CERM402
0.001UF
R71301
2
1/16WMF-LF
1%
402
3.92K
C7121
1 2
10%6.3V
402
0.22uF
CERM-X5R
C7103
1 2
10%
402
6.3VCERM-X5R
0.22uFR7104
1 2
MF-LF1/16W
402
15%
R7107
1 2
402MF-LF1/16W
15%
R7131
1
2
CRITICAL
10KOHM-5%0603-LF
R71451
2
1%
MF-LF
4991/16W
402
R7126
1 2
NO STUFF
CRITICAL470K402
R7125
1 2
402
05%1/16WMF-LF
R7124
1 2
402MF-LF
05%1/16W
R7106
1 2
NO STUFF
0
402
1/16WMF-LF
5%
C71091
2 16V33UF
CRITICAL
POLY20%
CASED2E-SM
C71171
2
33UF20%
CRITICAL
CASED2E-SMPOLY16V
C71011
2CASED2E-SM
CRITICAL
33UF20%16VPOLY
C71081
220%33UF
CASED2E-SMPOLY
CRITICAL
16V
C71181
2 X5R
1UF
603
25V10%
C71991
2
1UF25V10%
X5R603
Q7100
5
4
1 2 3
RJK0305DPB
CRITICAL
LFPAK
Q7101
5
4
1 2 3
CRITICAL
LFPAKRJK0301DPB
Q7104
5
4
1 2 3
CRITICAL
RJK0301DPBLFPAK
Q7102
5
4
1 2 3
CRITICAL
LFPAKRJK0305DPB
Q71035
4
1 2 3
CRITICAL
RJK0301DPBLFPAK
Q71055
4
1 2 3
RJK0301DPB
CRITICAL
LFPAK
U7100
48
36
26
47
10
17
45
46
16
11
12
21
3
24
23
32
30
25
6
8
33
291
34
28
2
31
4
15
7
49
35
27
22
13
37
38
39
40
41
42
43
20
18
44
5
14
19
9
ISL9504BCRZ
CRITICAL
QFN
R7146
1 2
1%
MF-LF1/16W
402
4.53K
NO STUFF
R71521 2
402MF-LF1/16W1%10K
NO STUFF
R7151
1 2
NO STUFF10K1%
402MF-LF1/16W
SYNC_MASTER=POWER SYNC_DATE=07/13/2005
051-7455
IMVP6 CPU VCore Regulator
59 76
01
128S0093 KEMET T520V336M016ATE0457650C7101,C7108?128S0092
128S0093 KEMET T520V336M016ATE0457650128S0092 C7109,C7117?
1.5 MM 0.25 MMIMVP6_LGATE1
1.5 MM 0.25 MMIMVP6_PHASE1
IMVP6_COMP
IMVP6_VO
IMVP6_RTN
IMVP6_VSEN
IMVP6_VSUM
IMVP6_DROOP
IMVP6_OCSET
IMVP6_ISEN2
IMVP6_LGATE2
IMVP6_PHASE2
IMVP6_UGATE2
IMVP6_ISEN1
IMVP6_LGATE1
IMVP6_PHASE1
IMVP6_UGATE1
IMVP6_BOOT2_RC
IMVP6_BOOT1_RC
0.25 MM1.5 MMIMVP6_UGATE1
0.25 MM0.25 MMIMVP6_ISEN1
IMVP6_FB
IMVP6_VDIFF_RC
IMVP6_VR_TT
IMVP6_BOOT1IMVP6_BOOT2
IMVP6_FB2
MIN_NECK_WIDTH=0.2 MM
PPVIN_S5_IMVP6_VINMIN_LINE_WIDTH=0.25 MM
0.25 MM0.25 MMIMVP6_ISEN2
IMVP6_UGATE2 0.25 MM0.25 MM0.25 MM 0.25 MMIMVP6_LGATE2
0.25 MMIMVP6_VSEN 0.25 MM
0.20 MMIMVP6_OCSET 0.25 MMCPU_VCCSENSE_NIMVP6_VSUM 0.20 MM0.25 MM
0.50 MM 0.20 MMGND_IMVP6_SGND0.25 MM 0.20 MMIMVP6_VO
0.20 MM0.25 MMIMVP6_DROOP0.20 MM0.25 MMIMVP6_DFB0.20 MM0.25 MMIMVP6_SOFT
IMVP6_BOOT2 0.25 MM0.25 MM0.20 MM0.25 MMIMVP6_FB20.20 MM0.25 MMIMVP6_FB
IMVP6_VW 0.25 MM0.25 MM
=PP3V3_S0_IMVP
0.20 MM0.25 MMIMVP6_RBIAS
IMVP6_COMP_RC
IMVP6_BOOT1 0.25 MM 0.25 MM
IMVP6_RTN 0.25 MM0.25 MM
IMVP6_COMP 0.20 MM0.25 MM
IMVP_VR_ON
=PPVIN_S5_CPU_IMVP
CPU_VID<1>
IMVP6_VO_R
=PPVIN_S5_CPU_IMVP
IMVP6_VDIFF 0.20 MM0.25 MM
CPU_VCCSENSE_N 0.25 MM0.25 MMCPU_VCCSENSE_P 0.25 MM 0.25 MM
VR_PWRGD_CK505_L
VR_PWRGOOD_DELAY
IMVP6_NTC
IMVP6_SOFT
CPU_PROCHOT_L
=PPVORE_S0_CPU_REG
IMVP6_NTC_R
IMVP6_VW
GND_IMVP6_SGND
IMVP6_RBIAS
IMVP_DPRSLPVR
IMVP6_PMON
IMVP6_PSI_L
CPU_DPRSTP_L
IMVP6_DFB
PM_DPRSLPVR
CPU_VCCSENSE_P
0.25 MM 0.25 MMIMVP6_PHASE2
IMVP6_VDIFF
CPU_VID<0>
CPU_VID<2>CPU_VID<3>CPU_VID<4>
PP3V3_S0_IMVP6_3V3
MIN_LINE_WIDTH=0.25 MMMIN_NECK_WIDTH=0.2 MM
GND_IMVP6_SGND
=PPVIN_S5_CPU_IMVP
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.25 MMVOLTAGE=5V
PP5V_S0_IMVP6_VDD
=PP5V_S0_CPU_IMVP
CPU_VID<5>
SMC_CPU_ISENSE
CPU_VID<6>
59D8
59D8
70C3
70B3
59D4
70A3
59D4
59C2
70A3
70A3
45C3
22C4
70B3
70A3
59C2
59A4
59A4
59A4
59A4
59C8
59B6
59B6
59B7
59B7
48D7
70A3
48D7
59A5
59A5
27B5
45B5
59C8
59A4
15B6
24C3
59A4
70A3
70A3
70A3
70A3
59B7
48D7
70A3
48C1
70A3
59C6
59C6
6D7
48C5
59A4 59A4
59A4
48D5
59A4
59A6
59A6
59A6
59A6
59A8
59A8
59A8
59A8
59C6
59C6
59A4
59A8
59A6
59A4
59C6
59C6
59C6
59B5
59B6 10A6
59C6
59B7
48C5
48D5
59B6
59C7
59C6
59B7
59B7
59B7
7C4
6D7
59C6
59B6
6D7
7B1
10B7
7B1
59B7
10A6
10A6
27A7
15B6
59A4
9C5
7D8
59A4
59A4
6D7
70B3
27B2
9B2
59A4
15A6
10A6
59C6
59A4
10B7
10B7
10B7
10B7
59A4
7B1
7A7
10B7
44C5
10B7
R1-
R1+ R2
V-
V+
+
SOFT
VW
VSUM
VSS
VSEN
VR_ON
VO
VIN
VID1
VID0
VDIFF
UGATE
THRM_PAD
RTN
PVCC
PHASEPGOOD
PGND
OCSET
LGATE
FDE
FB
DROOP
DFB
COMP
BOOT
AF_EN
VDD
RBIAS
VID2
VID3
VID4
IMON
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
RENDER VCORE POWER SUPPLY
MIN_NECK_WIDTHMIN_LINE_WIDTHMIN_NECK_WIDTHMIN_LINE_WIDTH
PLACE C7221 NEAR U7201 PIN 7
PLACE RC CLOSE TO SMC
Placement Note:
NC
MAX CURRENT = 7.7APWM FREQ. = 333 kHz
LATEST ISSUE: 2006/12/22
I103
I104
I105
I106
I107
I108
I109
I110
I111
I112
I113
I114
I115
I116
I117
I118
I119
I120
I121
I122
I123
I124
I125
C7201
12
0.1UF
402X5R16V10%
2
402
1/16W1%
MF-LF
750
C72221
2
0.22UF
402X5R6.3V20%
R72261 2
1001%1/16WMF-LF402
R72271 2
402MF-LF1/16W1%4.53K
C72231
2402
0.1UF
X5R16V10%
U72013
2
6
1
8
5
47
CRITICAL
MSOPINA326EA-250
C72031
2
470PF
CERM402
10%50V
R72001 2
MF-LF402
5%1/16W
10
R72071
2 402MF-LF1/16W1%200K
R72061
2 4021/16WMF-LF1%2.21K
R72051 2
0.002
CRITICAL
1206MF-LF1/4W1%
U7200
30
17
511
10
6
32
28
21
3
20
31 19
22
1
9
2
33
18
16
7
2324252627
14
12
29
8
15
134
QFNCRITICAL
ISL6263B R7201
1 2
1/16WMF-LF402
05%
R72201
2
1/16WMF-LF
5%30K
402
1
2 6.3V20%X5R
10UF
603
Q7200
5
4
1 2 3
LFPAK
CRITICAL
RJK0305DPB
Q7201
5
4
1 2 3
RJK0303DPB
CRITICAL
R72251 2
5%
402
1/16WMF-LF
100K
L7200
1 2
CRITICAL
0.82UH-16.5AIHLP2525EZ-SM
C72001
210%0.01UFX7R402
25V
C72041
2 CERM402
47PF50V5%
R72081 2
MF-LF1/16W1%15.8K
402
C7205
12
0.001UFCERM402
10%50V
C72061
2 16V
402
10%0.1UFX5R
R72091 2
402MF-LF1/16W1%1K
R7210
1 2402MF-LF1/16W
2.94K1%
C7207
12
10%50VCERM402
330PF
R7212
1 2402MF-LF1/16W1%2.21K
C7208
12
0.0018UF50VCERM10%
402
R7211
1 2402MF-LF1/16W
1.1K1%
R7213
1 2402MF-LF1/16W1%150K
C7209
12
50V10%680PFCERM402
R72141
2402MF-LF1/16W1%6.98KC72111
210%0.001UFCERM50V
402
C7210 1
2402
50V5%
CERM
150PF
C7212
12
0.001UF
402CERM50V10%
R72151
2402MF-LF1/16W
05%
R72161
2402MF-LF1/16W
05%
R7217
1 2
1/16W1%150K
402MF-LF
C721512
16V0.015UFX7R10%
402
R7218
1 2402MF-LF1/16W1%4.53K
NO STUFFR72031 2
1/16W5%
MF-LF402
1
R72021 2
402
1/16W
105%
MF-LF
C72021
2
2.2UF6.3V20%CERM1603
C7221
12
1UF6.3VCERM402
10%
C72141
2
0.001UFCERM
10%50V
402
C72131
2
0.001UF10%50VCERM402
C72171
2
CRITICAL
POLY16V20%
CASED2E-SM
33UFC72181
2
1UF10%
603
25VX5R
2 CASE-D2E-LF2.5V330UF
CRITICAL
20%POLY
XW72001 2
SM
R7224
1 2
10K1/16W
402
5%
MF-LF
R72211
2
NO STUFF
1%10K1/16WMF-LF402
R72231 2
5%
402
10K1/16WMF-LF
R72221
2402MF-LF1/16W1%10K
NO STUFF
128S0092128S0093 ? KEMET T520V336M016ATE0457650C7217
01
7660
SYNC_DATE=06/29/2006
Render VCore Supplies
051-7455
SYNC_MASTER=GPU
GCORE_VSUM
GCORE_VSEN
GFX_VID<1>
GFX_VID<0>
GCORE_VDIFF
GCORE_UGATE
GCORE_PVCC
GCORE_FB
GCORE_DROOP
GCORE_COMP
GCORE_BOOT
GCORE_AF_EN
GCORE_VDD
GCORE_RBIAS
GFX_VID<2>
GFX_VID<3>
GFX_VID<4>
0.3 MM 0.25 MMGCORE_VSEN
0.3 MM 0.25 MMGCORE_OCSET0.3 MM 0.25 MMGCORE_VW0.3 MM 0.25 MMGCORE_RTN
0.3 MMGCORE_RBIAS 0.25 MM0.3 MM 0.25 MMGCORE_SOFT0.3 MM 0.25 MMGCORE_COMP
GCORE_FB 0.3 MM 0.25 MM0.3 MMGCORE_VDIFF 0.25 MM0.3 MMGCORE_FB_RC 0.25 MM0.3 MMGCORE_VDIFF_RC 0.25 MM
1 MMGCORE_PHASE 0.25 MM0.3 MMGCORE_BOOT 0.25 MM1 MMGCORE_UGATE 0.25 MM1 MMGCORE_LGATE 0.25 MM0.3 MMGCORE_BOOT_RC 0.25 MM0.6 MMGND_GCORE_SGND 0.25 MM0.3 MMGCORE_VDD 0.25 MM0.3 MMGCORE_PVCC 0.25 MM0.3 MMGCORE_VIN 0.25 MM0.3 MMGCORE_DROOP 0.25 MM0.3 MMGCORE_VSUM 0.25 MM
GCORE_DFB 0.3 MM 0.25 MM
GND_SMC_AVSS
GPU_ISENSE_R1_N
GND_GCORE_SGND
=PP5V_S0_NB_GFX_IMVP
SMC_GPU1_ISENSE
GPU_ISENSE_VCC
GPU_ISENSE_R2
=PPVIN_S5_NB_GFX_IMVP
GCORE_VSUM_R
=PP3V3_S0_PDCISENS
GPU_ISENSE_R1_PGPU_ISENSE
GCORE_BOOT_RC
GCORE_FB_RC
GCORE_VDIFF_RC
SMC_GPU1_ISENSE
=PP3V3_S0_NB_GFX_IMVP
GND_GCORE_SGND
GCORE_VIN
GCORE_SOFT
GFX_VR_EN
GCORE_PMON
GCORE_PHASE
GCORE_RTN
GCORE_VW
GCORE_LGATE
GCORE_FDE
=PPVCORE_S0_NB_GFX_IMVP
GCORE_OCSET
GCORE_DFB
GND_GCORE_SGND
C72201C7219
R72041
LFPAK
OMIT
66C2 66B1 62C2 61C5 48C6 48C1 48B1
60D7
48A1
60D7
66C3
60C5
60D7
21B6
21B6
21B6
21B6
60C5
45B6
60A7
60C7
61C5
60B2
60A7
60C5
60A7
60A5
15B3
15B3
60A5
60A7
60A7
60A5
60A7
60A5
60A7
60A7
60A5
15B3
15B3
15A3
60C6
60B5
60B6
60B6
60D6
60C6
60B6
60B6
60B6
60B6
60B6
60C5
60C5
60C5
60C5
60C5
60A5
60D5
60D5
60C5
60B5
60B5
60B5
44C1
60A5
7A7
44A2
7B1
7C4
60A5
60A5
44A2
7C4
60A5
60A7
60A5
8B1
60A7
60A5
60A5
60A7
7B8
60A5
60A7
60A7
R1-
R1+ R2
V-
V+
+
V5FILT
DR_VH1
VO2VO1
VFB2VFB1
VBST2VBST1
V5IN
TRIP2TRIP1
TONSEL
THRM_PAD
PGOOD2PGOOD1
LL2
GNDEN2
EN1
DR_VL2
DR_VH2
PGND
DR_VL1
LL1
SYM(1 OF 2)
S
D
G
S
D
G
S
D
G
JUMPER
D
S
G
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
<Rd>
Vout = 0.758V * (1 + Ra / Rb)
"note: pu on pgood page"
put 6 vias under the thermal
1.5V/1.05V POWER SUPPLY
<Rc>
Routing Note:The discharge path (VO1) should havea dedicated trace to the output cap;separate from the output voltagesensing trace,
MAX CURRENT = 8A
Placement Note:
Placement Note:R7361,C7305 close to U7300 pin 15. separate from the output voltage
The discharge path (VO2) should havea dedicated trace to the output cap;
Note: pu on PGOOD page
S0
Routing Note:
NC
C7301 close to U7600 pin 16. sensing trace,
<Rb>
<Ra>
PLACE C7303 NEAR U7301 PIN 7
State PM_SLP_S3_L
0.0VLOW
PP1V05_S0
1.5VHIGH
S3/S5/G3Hot
PP1V5_S0
1.05V
0.00V
PLACE C7390,C7391
Placement Note:
NEAR NB
PWM FREQ. = 300 kHz PWM FREQ. = 360 kHzMAX CURRENT = 4A
pad (pin 25)
Routing Note:
LATEST ISSUE: 2006/12/22
PLACE RC CLOSE TO SMC
Vout = 0.758V * (1 + Rc / Rd)
C73061
2
0.22UF6.3V20%
X5R402
R73051 2
4.53K1%1/16WMF-LF402
R73901 2
402MF-LF1/16W1%100
C73031
2
0.1UF
X5R16V10%
402
U73013
2
6
1
8
5
47
CRITICAL
MSOPINA326EA-250
C73991
250VCERM
470PF
402
10%
R73911
2
1%MF-LF4021/16W200K
C73901
2 6.3VCERM
22UF20%
805
R73021
2
0.002
CRITICAL
1/4W
1206MF-LF
1%
R73921
2
2.21K1/16WMF-LF1%
402
U730021 10
19 12
238
3
20 11
18
13
24 7
25
4
17 14
15
16
22 9
2 5
1 6CRITICAL
TPS51124QFN
Q7361
5
4
1 2 3
CRITICAL
SI7110DNPWRPK-1212-8
R7364
1 2
MF-LF1/16W5%0
402
C7364
12
X5R10%
40216V0.1UF
L7360
1 2
CRITICAL
1.0UH-13A-5.6M-OHMSM-IHLP
C73921
23
CRITICAL
2.0V
330UF10%TANTD2T
C73801
2
33UFPOLY16V20%
CASED2E-SM
CRITICALC73811
225V
1UF10%
X5R603
R73671
220.0K1/16WMF-LF402
1%
R73681
2
1%1/16WMF-LF402
20.5K
R73651
2 402
3.74K1%MF-LF1/16W
C73891
2 CERM40225V220PF5%
R7324
1 2
MF-LF
05%1/16W402
C7324
12
10%
402X5R16V0.1UF
C73691
2 50VCERM5%100PF
NO STUFF
402
Q73205
4
123
CRITICAL
PWRPK-1212-8SI7110DN
5
4
123
CRITICAL
C73401 33UF20%POLY16V
CRITICALC73411
225V
603
1UF10%
X5R
1R73251
2
1%6.65K1/16WMF-LF402
R73271
2 402MF-LF1/16W1%7.68K
R73281
2
20.0K
402MF-LF1/16W1%
C73291
2
NO STUFF
50V
100PF5%
402CERM
C73011
2 6.3VX5R20%10UF
603
R7361
1 2
1/16W
3.3MF-LF5%
402
C73051
21UF
402
10V10%
X5R
XW73201 2
OPEN-SAWTOOTH
C73501
2 6.3V20%10UFX5R603
XW73001 2
SM
R73261
21/16W274K
NO STUFF
1%MF-LF402
C73251
2
NO STUFF
16VX5R
10%0.1UF
402
C73281
2
NO STUFF
0.001UF
40250VCERM10%
1 2SM-IHLP
Q73605
4
1 2 3
FDM6296MICROFET3X3
CRITICAL
C73981
2 25V5%
402CERM
220PF
C73511
2603X5R20%10UF6.3V
KEMET T520V336M016ATE0457650128S0093 ?128S0092 C7380,C7340
Q7360?376S0448 376S0445
1.5V / 1.05V SuppliesSYNC_MASTER=POWERSYNC_DATE=07/13/2005
051-745561 76
01
NB_ISENSE_VCC
VOLTAGE=1.5VMIN_LINE_WIDTH=1.5 mmMIN_NECK_WIDTH=0.25 mm
PP1V5_S0_REG_PMIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm
1V5S0_VH
MIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm
1V5S0_LL
MIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm
1V5S0_VL
PGOOD_1V5S0
=PPVIN_S5_1V05S0
MIN_NECK_WIDTH=0.25 mmVOLTAGE=1.05VMIN_LINE_WIDTH=1.5 mm
=PP1V05_S0_REG
GND_SMC_AVSS
NB_ISENSE_R2
NB_ISENSE_R1_N
GND_1V51V05S0_SGND
1V05S0_VBST_RC
1V51V05S0_V5FILT
=PP1V5_S0_REG
=PP5V_S5_1V51V05S0
1V5S0_RUNSS
1V05S0_VHMIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mm
1V5S0_VBST 1V5S0_VBST_RC
1V05S0_LL_RC
1V05S0_VBST
1V05S0_VLMIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm
=PPVIN_S5_1V5S0
1V05S0_RUNSS
1V05S0_TRIP
NB_ISENSE
1V5S0_TRIP
NB_ISENSE_R1_P
1V05S0_LLMIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm
=PP3V3_S0_PDCISENS=PP1V05_S0_REG_R
SMC_NB_CORE_ISENSE
PGOOD_1V05S0
GND_1V51V05S0_SGND
1V05S0_VFB 1V5S0_VFB
2
PWRPK-1212-8SI7108DNSQ7321
1.0UH-13A-5.6M-OHML7320CRITICALCASED2E-SM2
C7352330UF20%2.5VPOLYCASE-D2E-LF
CRITICALOMIT
66C2 66B1 62C2 60B2 48C6 48C1 48B1 48A1
66C3
7D8
45B6
62C5
58B1
60C2
58A5
7A1
6B2
44C1
61A3
7C8
7C1
6D7
7A1
58D1
7C4 7D8
44A8
58A5
61B6
R1-
R1+ R2
V-
V+
+
VDDQSET
S3
COMP
VTT
THRM_PAD
DRVH
LL
PGNDCS_GND
CS
PGOOD
NC1
S5
NC0
GND VTTGND
MODE
DRVL
VTTREF VLDOIN VBST V5IN VDDQSNS VTTSNSV5FILT
SYM (1 OF 2)
S
D
G
S
D
G
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
using separate trace.CONNECT VTTSNS TO C7507 PIN1
put 6 vias under the thermal padRouting Note:
Routing Note:
S3
S5/G3Hot
Routing Note:
using separate trace.
PLACE C7504 NEAR U7501 PIN 7
Placement Note:
Placement Note:
<Rb>
Q7521 PIN1,2.3using Kevin connection.
Connect CS_GND to
Routing Note:
Placement Note:PLACE XW7500,XW7501 NEAR C7542 PIN 2
NCNC
S0
HIGH
PM_SLP_S4_L
HIGH
LOW
LOW
HIGH
LOW
1.8V
0.0V
1.8V
0.0V
0.9V
0.0V
PWM FREQ. = 400 kHz
PLACE RC CLOSE TO SMC
PM_SLP_S3_LPP1V8_S3 PP0V9_S0
CONNECT VDDQSNS TO C7542 PIN1
PLACE C7543 NEAR NB
LATEST ISSUE: 2006/12/22
<Ra>
Vout = 0.75V * (1 + Ra / Rb)
State
1.8V/0.9V POWER SUPPLY
MAX CURRENT = 10.75A
R7561
1 2
5%
MF-LF1/16W
100
402
C75051
2402
0.22UFX5R6.3V20%
R7503
1 2
1%4.53K
402MF-LF1/16W
U75013
2
6
1
8
5
47
MSOP
CRITICAL
INA326EA-250
C75641
2
470PF10%CERM50V
402
R75631
2
1%1/16W402MF-LF
200K
R75601
2
1%1/16WMF-LF402
2.94K
R75021
2MF-LF1/4W1%
1206
CRITICAL
0.002
U75006
16
17
21
19
3
20
4
712
18
131011
25
14
15
22
9 823
24
1
5 2
CRITICAL
TPS51116QFN
1 2
SM-IHLP
R75001 2
402MF-LF5%01/16W
C75091
2
0.1uF10%16VX5R402
1
2 16V
C75421
2 CASE-D2E-LF2.5V330UF
CRITICAL
POLY20%
C75411
220%10UF6.3V603X5R
C75021
2 6.3V20%10UFX5R603
R75101
2
1%1/16WMF-LF402
8.25K
R75071 2
402MF-LF1/16W4.75%
XW75001 2
SM
R7521
1 2402MF-LF1/16W1%28K
R75221 2
402MF-LF1/16W20.0K1%
C75031 2
CERM402
5%50V
C75011
2
10UF6.3VX5R603
20%
C75401 2
X5R
0.033UF10%
40216V
C75071
2
10UFX5R6.3V20%
603
C75081
2603
20%6.3VX5R
10UF
C75001 2
1UF10V402
10%X5R
XW75011 2
SM
C75431
2
330UFPOLYCASE-C2
20%2.5V
CRITICAL
1
2 X5R
10%25V
603
1UF
C75041
2402
10%16VX5R
0.1UF
Q75205
4
1 3
CRITICAL
Q7521
5
4
1 2 3
SI7108DNS
CRITICAL
PWRPK-1212-8
R7599
1 2
1/16W402MF-LF
5%100K
01
7662
1.8V/0.9V SuppliesSYNC_MASTER=POWERSYNC_DATE=07/13/2005
051-7455
KEMET T520V336M016ATE0457650C7530128S0093 128S0092 ?
1V8S3_DRVH MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mm
1V8S3_LL MIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm
=PP1V8_S3_REGMIN_LINE_WIDTH=1.5 mmVOLTAGE=1.8VMIN_NECK_WIDTH=0.25 mm
=PP1V5_S0_REGMEMVTT_VREFMEM_ISENSE_R1_N
GND_1V8S3_VTTGND
1V8S3_VBST
PGOOD_1V8S3
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mm
1V8S3_DRVL
=PP1V8_S3_REG_R
MEM_ISENSE_R1_P
1V8S3_RUNSS
=PP3V3_S3_PDCISENS
1V8S3_CS
MEM_ISENSE
=PP3V3_S3_PDCISENS
GND_1V8S3_VTTGND
GND_1V8S3_SGND
MEM_ISENSE_R2
SMC_NB_1V8_ISENSE
MEM_ISENSE_VCC
GND_SMC_AVSS=PP5V_S5_1V8S30V9S0
=PP0V9_S0_REG
1V8S3_VBST_RC
PM_SLP_S3_L
1V8S3_V5FILT
100PF
NO STUFF1V8S3_VDDQSET
=PPVIN_S5_1V8S30V9S0CRITICAL
20%
C7530 C7531
CASED2E-SMPOLY
33UFSI7110DNPWRPK-1212-8
2
1.0UH-13A-5.6M-OHML7520CRITICAL
OMITOMIT
66C2 66B1 61C5 60B2
58B7
48C6
45A6
48C1
44C5
48B1
35C7
48A1
61B1
33C7
62A2
45B6
7B6
7C8
62A6
58B6
7B5
7A1
65C2
24D3
7A4
62C5
44A8
44C1
7D8
JUMPER
DRVL2
LL2
DRVH2
VBST2
EN2
EN3
EN5
VO2
PGOOD2
VREG5
CS1
PGND1
VIN
V5FILT
VREG3
CS2
PGND2
DRVL1
LL1
DRVH1
VBST1
EN1
PGOOD1
TONSEL
SKIPSEL
PWPD
VO1
VFB1
VREF2
VFB2
COMP2
COMP1
SYM (2 OF 3)
GND
JUMPER
S
D
G
S
D
G
S
D
G
D
S
G
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
MAX CURRENT = 7.5A
5V/3.3V POWER SUPPLY
S0/S3/S5 HIGH
0.0V
5.0V 3.3V
LOW 0.0V3.3V
3.3V
G3H
separate from the output voltage
NC
The discharge path (VO2) should havea dedicated trace to the output cap;
Routing Note:
sensing trace,
<Rc>
NC
<Rb><Ra>
a dedicated trace to the output cap;
Routing Note:
State PP3V3_G3H PP5V_S5 PP3V3_S5
PWM FREQ. = 280 kHz
LATEST ISSUE: 2006/12/22
Placement Note:R7601,C7605 close to U7600 pin 20.
C7602 close to U7600 pin 22.
C7604 close to U7600 pin 21.
C7603 CLOSE TO U7600 PIN 19.
R7605,R7603 close to U7600.
MAX CURRENT = 5APWM FREQ. = 430 kHz
SMC_PM_G2_EN
The discharge path (VO1) should have
sensing trace,separate from the output voltage
put 6 vias under the thermal padRouting Note:
(pin 33)
<Rd>Vout = 1V * (1 + Rc / Rd)Vout = 1V * (1 + Ra / Rb)
XW76201 2
OPEN-SAWTOOTH
C7620
12
X5R
0.1UF
402
10%16V
C76511
2
150UF20%
CASE-B2POLY6.3V
CRITICAL
U7600
2 7
23
18
27 14
25 16
29 12
10
9
5
26 15
24
17
30 11
32
33
31
20
28 13
3 6
22
1 84
19
21
LLP
CRITICAL
TPS51120
C76501
2603
10UFX5R6.3V20%
C76221
25%CERM50V22PF
402
C76051
2
1UF
402
10%10VX5R
R76031
2
5.90K
MF-LF402
1%1/16W
C76041
2 X5R603
10UF20%6.3V
C76031
220%
603
10UFX5R6.3V
C76401
233UF
CRITICAL
POLY20%16VCASED2E-SM
L7660
1 2
3.3UHIHLP
CRITICAL
XW76601 2
R7627
1 2
CRITICAL
20K0.1%MF1/16W402
C7627
12
50V
NO STUFF
5%CERM
100PF
402
R7628
1 2
CRITICAL
0.1%MF1/16W
8.66K
402
R7620
1 2
5%
4021/16WMF-LF
0
C76411
210%X5R
1UF25V603
C76521
2
150UF
CRITICAL
20%6.3VPOLYCASE-B2
R7660
1 2
1/16WMF-LF5%
402
0C7660
12
0.1UF
402X5R10%16V
R7667
1 2
CRITICAL
20K0.1%MF1/16W402
R7668
1 2
CRITICAL
0.1%MF
4.99K1/16W402
C7667
12
NO STUFF
CERM50V100PF
402
5%
C76001
2
10%CERM50V0.001UF
402
C76811
210%X5R
1UF25V603
C76801
2
CASED2E-SM
CRITICAL
POLY16V20%33UF
C76921
2
150UF6.3VPOLY
1
2
150UFPOLY6.3V20%
C76901
2
2.2UF10%16V603X5R
C76821
2
CASED2E-SMPOLY16V20%33UF
CRITICAL
C76021
2
1UF
603X5R10%25V
R76051
2
1%MF-LF402
7.87K1/16W
R7601
1 2
4.71/16W5%MF-LF402
XW76011 2
SM
Q7621
5
4
1 2 3
SI7110DNPWRPK-1212-8
CRITICAL
Q7660
5
4
123
PWRPK-1212-8SI7110DN
CRITICAL
L7620
1 2
IHLP4.7UH
Q7661
5
4
123
PWRPK-1212-8
R76701
2
NO STUFF
100K
MF-LF1/16W5%
402
C76711
2
0.01UFCERM40216V10%
R76711
2MF-LF5%100K1/16W
NO STUFF
402
R7610
1 2
MF-LF5%1/16W402
0
C7670 1
2CERM
220PF
NO STUFF
5%25V402
Q7620
5
4
1 2 3
CRITICAL
MICROFET3X3FDM6296
01
7663
5V/3.3V Supplies
051-7455
SYNC_DATE=07/13/2005SYNC_MASTER=POWER
128S0093 KEMET T520V336M016ATE0457650?128S0092 C7682,C7680
128S0092128S0093 KEMET T520V336M016ATE0457650C7640?
Q7620376S0445376S0448 ? KEMET T520V336M016ATE0457650
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mm
5VS5_DRVH
RSMRST_PWRGD
5V3V3S5_VREF
5V3V3S5_TONSEL
5VS5_DRVLMIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm
=PPVIN_S5_3V3S5
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mm
3V3S5_LL
RSMRST_PWRGD
5V3V3S5_V5FILT
GND_5V3V3S5_SGND
=PP3V3_S5_REG
3V3S5_VBST 3V3S5_VBST_RC
5VS5_CS
5VS5_VBST_RC
=PP5V_S5_REG
GND_5V3V3S5_SGNDGND_5V3V3S5_SGND
5VS5_VREG
5V3V3S5_V5FILT=PPVIN_S5_5VS5
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1 mm
5VS5_LL
MIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm3V3S5_DRVH
5VS5_RUNSS
5V3V3S5_VREG33V3S5_CS
MIN_LINE_WIDTH=1 mmMIN_NECK_WIDTH=0.25 mm3V3S5_DRVL
3V3S5_VFB
MIN_NECK_WIDTH=0.25 mmMIN_LINE_WIDTH=1.5 mmVOLTAGE=3.3V
PP3V3_S5_REG_P3V3S5_RUNSS
5VS5_VBST
=PPVIN_S5_5VS5
PP5V_S5_REG_P
GND_5V3V3S5_SGND
5VS5_VFB
CRITICAL
OMIT OMITCRITICAL CRITICAL
SI7110DN20%
MIN_LINE_WIDTH=1.5 mm
OMIT
OPEN-SAWTOOTH
VOLTAGE=5V
OMITMIN_NECK_WIDTH=0.25 mm
CRITICAL
CASE-B2CASE-B2
C7691
63B4 63B5
63C4
63C4 63C4
63B6
45D5 45D5
63B6
63B6 63B4
63B6
65C5
63B4
44D8
7A1
44D8
63A4
63B4
7D3 7C3
63A4 63A4
63C4
7A1
6D7
65C5
63A4
FB
BIAS
SWSHDN*
NC
VIN BOOST
GND
RTRUN/SS
SYNC/MODEITH
VFB
PGOOD
PVINSVIN
THERMPADPGNDSGND
SW
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
<Rc>
NOTE: Be aware of pull-up on this signal.
Continuous
1.25V S0 REGULATOR
Connect RUNSS off-page to controlIf unconnected, powers up with PVIN.
3.0A max output(Switcher limit)
Vout = 0.8V * (1 + Ra / (Rb + Rc))
<Rb>
<Ra>Vout = 1.2516V
3.425V G3H SUPPLY
LATEST ISSUE: 2007/3/8
NC
Supply needs to guarantee 3.31V delivered to SMC VRef generator
<Rb>
Vout = 1.25V * (1 + Ra / Rb)
<Ra>
PWM FREQ. = 1 MHz @16.5VMAX CURRENT = 0.2A
Burst
C77931
2805
22UF6.3V20%CERM
R77911
2402MF-LF1/16W1%348KC77921
2402
22pFCERM5%50V
R77921
2
1%
402MF-LF1/16W200K
L7790
1 2
CRITICAL
CDPH4D19F-SM33uH
C77911
2
402CERM-X5R6.3V10%0.22uF
U7790
7
6
8
4
2
1 5
3
TSOT23-8
CRITICAL
LT3470
C77901
2
CRITICAL
10UF10%25VX5R1206-1
C77301
2 CERM-X5R0805
4V
47UF20%
C7729 1
2CERM-X5R4V20%
47UF
0805
C77281
2
402
25V
1000PF
X7R
10%R77231
2
47.0K
402
1/16WMF-LF
1%
R77241
2
1/16W
402MF-LF
1%60.4K
R77251
2402
1/16WMF-LF
1%23.2K
C7720 1
20805
CERM-X5R4V20%
47UF
U7720
13
6 7
12
10
3
15
1
2
11
4
5
8
9
16
17
14
CRITICAL
LTC3412AQFN
L77202.2UH-3.25A
CRITICAL
IHLP1616BZ-SM
XW77001 2
SM
R77261
2
309K
402
1/16WMF-LF
1%
C7725 1
2
470PF
402
50V10%
CERM
R77271
2
NO STUFF
402
5%0
MF-LF1/16W
R77221
2
5%1M
1/16W
402MF-LF
R77281
2
1/16W
0
MF-LF402
5%
C7724 1
2
402
100PF5%
CERM50V
R77211
2402
1/16W
8.25K1%
MF-LF
C77231
2402
25V
1000PF
X7R
10%
3.42V/1.25V Switcher
7664
051-7455
SYNC_DATE=12/06/2005SYNC_MASTER=ENET
01
GND_P1V2S3_SGND
MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.2 mmVOLTAGE=0V
P1V25S0_VFB
P1V25S0_VFB_DIV
P1V25S0_ITH_RC
P1V25S0_MODEP1V25S0_ITH
1V25S0_RUNSSP1V25S0_RT
=PP3V3_S5_1V25S0
=PP1V25_S0_REG
MIN_LINE_WIDTH=0.6 mmP1V25S0_SW
MIN_NECK_WIDTH=0.25 mm
=PPVIN_G3H_P3V42G3H
PP3V42G3H_SW =PP3V42_G3H_REG
P3V42G3H_FB
P3V42G3H5_BOOST
58C1
7C1
7C8
7B1
7C3
NC
D
SG
IN
D
SG
IN
IN
D
SG
D
SG
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
DLATEST ISSUE: 2006/12/22
48 mOhm @4.5V
FDC638PP-TYPE65 mOhm @2.5V0.098 A
3.3V S3 FET
RDS(ON)0.051 A
FDC638PP-TYPE
5V S3 FET
5V/3.3V S5 RUN/SS CONTROL
Open drain output
MOSFET
RDS(ON)CHANNEL
LOADING
CHANNELMOSFET
LOADING
NC
S3 FETS & S3/S5 CONTROL
1.8V S3 RUN/SS CONTROL
U78702
31
5
4SC70
CRITICAL
74LVC1G07
R78751
2
1/16WMF-LF
10K1%
402
Q7865
1256
3
4
FDC638PSM-LF
CRITICAL
C7801
1 2
50V
0.0022uF10%
402CERM
Q7866
1256
3
4
CRITICAL
SM-LFFDC638P
Q78593
5 4
SOT563SSM6N15FE
R78061 2
402MF-LF1/16W5%10K
C7802
1 2402
0.01UF16V10%
CERM
R7808
1 2402
10K
MF-LF1/16W5%
R7805
1 2
5%100K1/16W
402MF-LF
R78071
2
100K5%
402
1/16WMF-LF
Q78596
2 1
SOT563SSM6N15FE
R7857
1 2
5%470K
402MF-LF1/16W
R78561
2 4021/16W100K5%MF-LF
Q78603
5 4
SOT563SSM6N15FE
Q78606
2 1
SOT563SSM6N15FE
01
7665
S3 FET & S3/S5 Control
051-7455
SYNC_MASTER=DSIMON-WFSYNC_DATE=06/12/2006
1V8S3_RUNSS
=PP3V3_S3_FET
PM_S4_STATE_L
3V3S5_RUNSS
=PP5V_S5_PWRCTL P5VS3_EN_L
5VS5_RUNSS
SMC_PM_G2_EN
=PP3V42_G3H_PWRCTL
=PP5V_S3_FET
=PP3V3_S5_FET
SMC_PM_G2_EN_L
=PP5V_S5_FET
=PP3V3_S3_FET
P3V3S3_EN_L
=PP3V3_S5_FET
PM_SLP_S4_LS5V
PM_S4_STATE_L
65A6
58D5
65C4
44C5
65A5
58C6
65C4 44C5
65A4
33B7
63B5
58C5
58B3
65C3
58C5 33B7
62B8
7A6
24D3
63B4
7C1
6D7
44D5
7B1
7A5
7D1
7C1
7A6
7D1 24D3
GND
OUT
VIN+ VIN-
V+
GND
OUT
VIN+ VIN-
V+
ACSET
EN
CSIP
DCPRN
THRML_PAD
PGND
DCSET
LGATE
UGATE
BOOT
BGATE
DCIN
CSIN
SGATE
VREF
ACPRN
CSON
CSOP
VCOMP
ICOMP
VDDP
CELLS
VADJ
VDD
CHLIM
PHASE
FB
ACLIM
GND
D
SG
D
SG
D
SG
D
S G
D
SG
D
SG
D
SG
D
SG
D
SGD
SG
V+
V-
GND
VCC
PGOOD
OUT
FB
IN
SHDN*
I.C.THRMLPAD
D
G
S
D1
D3
D4S3S2
GATE
S1D2
D1
D3
D4S3S2
GATE
S1D2
D1
D3
D4S3S2
GATE
S1D2
TABLE_ALT_ITEM
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
PWM FREQ. = 300 kHz
LATEST ISSUE: 2006/12/22
Placement Note:
PLACE RC CLOSE TO SMC
PLACE RC CLOSE TO SMC
Placement Note:PLACE NEAR R7908
NC
NCNC
NC
NC
PLACE NEAR R7997
PBUS SUPPLY / BATTERY CHARGER
F7900
1 2
12067AMP
CRITICAL
XW7900
1 2
SM
R79031
2
NO STUFF
100K5%
MF-LF402
1/16W
D7900
12
SOD-123B0530WXFCRITICAL
C79401
210%0.1UF
X5R402
25V
R79971
2 0612
1W0.5%0.02
MF
CRITICAL
R79401
2
1%88.7K1/16W
402MF-LF
C79751
2402
6.3VCERM
1UF10%
R79411
2402MF-LF1/16W
10K1%
U7970
2
15
3 4
CRITICAL
SOT23-5INA193
C79701
2402
6.3VCERM
10%1UF
C79711
2
20%
X5R6.3V
402
0.22UF
C79721
2
0.22UF
402X5R6.3V20%
C7900
1 2
0.033uF
402
10%16VX5R
R79001 2
MF-LF
4.71/16W5%
402
R7905
1 2
1/16W402
18
MF-LF
5%
R79441
2MF-LF1/16W1%
402
100K
R7902
1 2
NO STUFF
5%100K1/16WMF-LF402
C7903 1
2
10%0.1UF
X5R402
25V
R7970
1 2
1%1/16WMF-LF402
4.53K
R7908
1 2
1W0.5%
CRITICAL
0612
0.01
MF
R7971
1 2
4.53K1%1/16WMF-LF402
R79251 2
402MF-LF1/16W1%10K
R7920
1 2
3WMF
5%
2525
27
C79411
2 X5R
10%
402
25V
0.1UF
C7916 1
2
NO STUFF
10%50V
402CERM
0.001UF
R79101 2
2.25%1/16WMF-LF402
C79171
210%
NO STUFF
25VX5R
0.1UF
402
C79021
2
1UF10%
402X5R10V
C79811
2 50V10%CERM
0.0022UF
402
R79811 2
603
1%49.9MF-LF1/10W
C79181
2 CERM10V
0.22UF10%
402
C79081
2
33UF16V20%
POLYCASED2E-SM
CRITICAL
U7975
2
15
3 4
CRITICAL
INA193SOT23-5
C79281
210%0.01UF
CERM16V
402
R79621 2
1/16WMF-LF
1%15.0K
402
R79631
2
1%1/16WMF-LF
44.2K
402
R79791 2
10K5%1/16WMF-LF402
C79271
2402
10%
CERM-X5R16V
0.022UF
R79601 2
1%1/16WMF-LF
15.0K
402 R79611
2 402
20.0K1%1/16WMF-LF
R79691 2
402MF-LF
5%10K1/16W
R79501
2
1%100K1/16WMF-LF402
C79671
2
10%50VCERM402
470PF
U79008
2327
17
142
7
2019
2221
25
2428
1
5
10
3
12
11
16
18
29
15
94
26
13
6
CRITICAL
ISL6257HRZ
QFN
R7909
1 2
1%1/16WMF-LF
100K
402
R7968
1 2
2.37K1%
MF-LF4021/16W
C79801
2
0.1UF
X5R16V
402
10%
C79101
2603
1UF25V10%
X5R
5
4
1 2 3
LFPAKRJK0305DPBQ7901CRITICAL
Q79025
4
1 2 3
CRITICAL
LFPAKRJK0305DPB
R7901
1 2402MF-LF1/16W
56.2K1%
R7967
1 2
MF-LF
1%3.01K1/16W402
C7901
1 2402
50VCERM10%0.001UF C7911
1 2
10%1UF
402
10VX5R
R79511
2 402MF-LF1/16W1%100K
R79061
2
5%2.21/16WMF-LF402
D79221
3SOT23MMBD914XXG
Q7922 3
5 4
SOT563SSM6N15FE
Q79226
2 1
SOT563SSM6N15FE
Q7924 3
5 4
SOT563SSM6N15FE Q79246
21
SSM6N15FESOT563
Q7960 6
2 1
SSM6N15FESOT563
Q7960 3
5 4
SOT563SSM6N15FE
Q79616
2 1
SSM6N15FESOT563
Q7961 3
5 4
SOT563SSM6N15FE
C79501
2
1UF25V10%
603X5R
C79071
2603
1UF10%25VX5R
C79051
2
22UF20%
CRITICAL
25VPOLYCASE-D2-LF
C79061
2 25V20%22UF
CRITICAL
CASE-D2-LFPOLY
R7964
1 2
MF-LF1/16W1%
NOSTUFF
402
2.43K
Q79506
2 1
SSM6N15FESOT563
Q79503
5 4
SSM6N15FESOT563
R7965
1 2
1%
MF-LF1/16W402
100K
U7901
1
2 3
4
5
6
CRITICAL
SOT563
TLV341
U7950
3
2
7
1 8
56
9
4
TDFNMAX8719
CRITICAL
C79521
210%
603X5R25V
1UFR79541
2
5%
MF-LF1/16W
100K
402 C79511
2603
25VX5R
1UF10%
R79531
2402
22.6K0.1%
MF1/16W
CRITICAL
R7952
1 2
CRITICAL
0.1%-50PPM
MF-LF1/16W
221K
402
D7950
1
2
3
BAT54CW-X-FSOT-323
Q7940
3
1
2
FDN360P_NLSOT-23
C79121
2 X5R10V
1UF
402
10%
Q7900
5
6
7
8
4
1
2
3
CRITICAL
AO4409SOI
C79041
2X5R402
10%0.1UF25V
CRITICAL
3
2 1
L79004.7UH
FDA1254-3SM
C79091
2ELEC16V20%
6.3X5.5SM1
CRITICAL
100UF
Q7920
5
6
7
8
4
1
2
3
CRITICAL
AO4409SOI
Q7921
5
6
7
8
4
1
2
3
AO4409
CRITICAL
SOI
R79301
2
470K1%1/16WMF-LF402
R79311
2MF-LF1/16W
330K5%
402
R79221
2
1%39.2K1/16WMF-LF402
R79231
2
1%35.7K1/16WMF-LF402
C79201
2 CERM16V10%0.01uF
402
C79211
2 X5R16V
402
10%0.1UF
C79241
2 CERM16V10%
402
0.01uF
NO STUFF
C79221
2
NO STUFF
0.01UF16V
402
10%
CERM
C79231
2
0.1UF
X5R16V10%
402
128S0092128S0093 C7908,C7910? KEMET T520V336M016ATE0457650
AOS MOSFET? Q7900,Q7920,Q7921376S0543376S0466
SYNC_DATE=08/19/2005
051-7455 01
66 76
SYNC_MASTER=SMC
PBUS Supply/Battery Charger
CHGR_DCIN
CHGR_VDD
=PP18V5_G3H_CHGR
GND_CHGR_SGND
PPVBAT_G3H_CHGR_REGMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
SMC_ENRGYSTR_LDO_EN
SMC_ENRGYSTR_LDO_PGOOD
LDO_FDBK
MIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.25 MMPP18V5_S5_CHGR_SW_R
PPVBATT_G3H_PRE BATT_POS_FMIN_LINE_WIDTH=0.6 MMMIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.2 MMBYPASS_R_GATE
PPVBAT_G3H_CHGR_OUT
BATT_FET_GATE
PPVDCIN_G3H_PREMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
CHGR_SGATE
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.2 MM
CHGR_ACLIM_R
SMC_SYS_ISET_L
MIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.2 MM
LDO_OUT
PPVBAT_G3H_CHGR_OUTMIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.6 MM
DCIN_ISENSE
CHGR_LGATE
GND_CHGR_SGND
CHGR_PHASE
CHGR_CSIN
CHGR_VREF
BATT_RC
MIN_LINE_WIDTH=0.2 MMMIN_NECK_WIDTH=0.2 MM
BATT_ENABLE_L
CHGR_FB
CHGR_ACSET
SMC_BATT_ISET_L
CHGR_BOOT
=PP3V42_G3H_ACIN
CHGR_ACSET_RC
=PP3V42_G3H_ACIN
SMC_SYS_ISET
=PP3V3_S0_PBATTISENS
SMC_BATT_CHG_EN
GND_SMC_AVSS
GND_SMC_AVSS
SMC_BATT_TRICKLE_EN_L
CHGR_VDD
SMC_BATT_ISENSE
BYPASS_R_DRV
BATT_ISENSE
CHGR_VCOMP_RC
=PPBUSB_G3H
CHGR_PHASE_RC
CHGR_CHLIM_R
SMC_BC_ACOK
GND_CHGR_SGND
ACIN_ENABLE_GATE
=PPBUSA_G3H
CHGR_BGATE
CHGR_FB_R
CHGR_UGATE
CHGR_VCOMP
CHGR_ICOMP
CHGR_VDDP
CHGR_CSOP
CHGR_BOOT_RC
SMC_DCIN_ISENSE
CHGR_ACPRN
P3V42_G3H_ACIN_R
=PP3V3_S0_PDCISENS
CHGR_EN
=PP3V42_G3H_ACIN
CHGR_CHLIM
CHGR_ACLIM
CHGR_VREF_VF
SMC_BATT_ISET
66C2
66B1
62C2
62C2
61C5
61C5
60B2
60B2
48C6
48C6
48C1
48C1
57C7
66A8
66B8
48B1
48B1
57C3
66B8
66A5
66A5
45B6
48A1
48A1
45B6
45B6
61C5
66A8
66B8
45C5
57D5 66C2
66B5
66B8
57C4
57C4
44C8
45B6
45B6
44C8
44C5
66B5
60C2
57C4
44B5
66B5
7B1
66A8
44A2
44A2
57B2 6B1
6B1
66B5
7B1
7B1
44B5
7C4
6C1
44C1
44C1
6C1
66C6
44C5
7B3
6C1
66A8
7B3
44C5 7C4
7B1
6C1
IN
IO
IO
IN
SYM_VER-1
IO
IO
IO
IO
IO
IO
IO
IO
D
G S
D
G S
Y
B
A
G
D
S
SYM_VER-1
OUT
OUT
OUT
S
G
D
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
THIS GND CONECTS TO CHASSIS GND
LCD I/F
Plexi: 516S0212*Enclosure: 518S0364
CAMERA I/F
LCD + CAMERA CONNECTOR
(LVDS DDC POWER)
LVDS REFERENCE CURRENT,2.37K OHM PULL DOWN RESISTOR NEEDED
INVERTER CONNECTOR
518S0521
C90141 2
50V
402CERM
10%
0.0022UF
R90001
2
1%
MF-LF1/16W
402
100K
R90131 2
1%1/16WMF-LF
2.37K
402
R90161
2
1/16W5%10K
NOSTUFF
MF-LF402
R90151
2MF-LF
10K5%1/16W402
NOSTUFF
C90121
2 X5R6.3V20%10UF
603
C90111
2
0.1UF
402
10%X5R16V
L90051 20402-LF
FERR-120-OHM-1.5A
C90161
210%50V
0.001UFCERM402
R90021
2
1/16W5%
MF-LF402
100K
L9007
1
2 3
4
CRITICAL
90-OHM-200MASM
L90081 2
120-OHM-0.3A-EMI
0402-LF
R90231 2
4021/16WMF-LF5%
10K
J9001
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
3
4
5
6
7
8
9
F-RT-SM
CRITICALS-050162B
L90021 20402-LF
FERR-120-OHM-1.5A
L90031 20402-LF
FERR-120-OHM-1.5A
R90011 2
402
1%
100K
MF-LF1/16WQ9006
3
1 2
SOD-VESMSSM3K15FV
Q90043
1 2
SOD-VESMSSM3K15FV
U90532
1
3
5
4
CRITICAL
TC7SZ08AFEFSOT665
C90591
2402
16V10%
0.1UF
X5R
Q90053
1
2
SOT723-3NTK3142P
R90141
2
1%
MF-LF1/16W
100K
402
C90021
2
100PFCERM5%50V402
C90031
2402CERM
100PF5%50V
C90001
240250V5%100PFCERM
C90151
2402CERM10%
0.001UF50V
C90101
210%CERM50V
0.001UF
402
C90081
2
0.001UF50VCERM10%
402
J9000
5
6
1
2
3
4
CRITICAL
78171-0004M-RT-SM
L9006
1
2 3
4
CRITICAL
90-OHM-200MASM
DZ9001
1
2
8V-100PF
NOSTUFF
402-1
CRITICALDZ9000
1
2CRITICAL
402-18V-100PF
NOSTUFF
L90101 2
FERR-1000-OHM
0402
NOSTUFF
L90111 2
FERR-1000-OHM
NOSTUFF
0402
L90121 2
FERR-1000-OHM
0402
NOSTUFF
Q9003
1
2
5
6
3
4
CRITICAL
SOT-6FDC606P
C90011
240250V5%100PFCERM
L90001 20402-LF
120-OHM-0.3A-EMI
L90011 20402-LF
120-OHM-0.3A-EMI
C90091 2
10%
CERM50V
402
0.001UF
R90091
2
10K5%MF-LF4021/16W
R90081
2
10K
MF-LF4021/16W5%
L90041 2
FERR-120-OHM-1.5A
0402-LF
C90131 2
50V10%
CERM402
0.0033UF
INVERTER,LVDS,TMDSSYNC_DATE=06/23/2006SYNC_MASTER=GPU
051-745567 76
01=GND_CHASSIS_LVDS
MIC_HI_LVDS_CONN
MIC_LO_LVDS_CONN
LVDS_CTRL_DATA
=PP3V3_S5_LCD
LVDS_DDC_DATA
=GND_CHASSIS_LVDS
=GND_CHASSIS_LVDS
MIC_HI_LVDS_CONNMIC_LO_LVDS_CONNPP5V_S3_CAMERA_F
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MM
VOLTAGE=5V
VOLTAGE=3.3VPP3V3_LCDVDD_SW_F
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MM
=USB2_CAMERA_N
=USB2_CAMERA_P
PP3V3_LCDVDD_SWVOLTAGE=3.3V
MIN_LINE_WIDTH=0.30 MMMIN_NECK_WIDTH=0.20 MM
PLT_RST_L
=PP5V_S0_LCD
LCDVDD_PWREN_L_R
=PPBUS_S5_INV
INVT_CHGND
INV_BKLIGHT_PWM_L
VOLTAGE=5VMIN_LINE_WIDTH=0.30 MMMIN_NECK_WIDTH=0.20 MM
PP5V_INV_F
LVDS_A_DATA_P<2>
LVDS_A_DATA_N<0>
LVDS_A_DATA_P<1>LVDS_A_DATA_N<1>LVDS_A_DATA_P<0>
USB2_CAMERA_CONN_PUSB2_CAMERA_CONN_N
LVDS_A_CLK_F_PLVDS_A_CLK_F_N
LVDS_A_DATA_N<2>
LCDVDD_PWREN_L
LVDS_A_CLK_P
LVDS_BKLT_EN
INV_PWREN_F_L
=PP3V3_S0_LCD
LVDS_VDD_EN
=PP3V3_S0_LCD
LVDS_CTRL_CLK
LVDS_IBG
=PP5V_S3_CAMERA
MIC_LO_LVDS
MIC_SHIELD_LVDS
MIC_HI_LVDS
LVDS_A_CLK_N
=GND_CHASSIS_LVDS
PP3V3_S0_LCD_FVOLTAGE=3.3V MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM
LVDS_DDC_CLK
=PP3V3_S0_LCD
=PP3V3_S0_LCD
MIN_LINE_WIDTH=0.30 MMMIN_NECK_WIDTH=0.20 MMVOLTAGE=5V
PP5V_INV
INV_PWREN_L
LVDS_BKLT_CTLBKLIGHT_CTL
PPBUS_ALL_INV_CONNVOLTAGE=12.6V
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.30 MM
INV_GND
67B2
67B2
67B2
67C6
67A6
67C6
67A4
67A6
67A6
67B7
67C6
67A4
67B7
67B7
67A2
14D5
67A2
67A4
27D4
71D3
71D3
71D3
71D3
71D3
71D3
71D3
67B5
67B5
14D5
71C3
71D3
67A2
67B5
67B5
8C8
67A2
12B1
7D1
14D5
8C8
8C8
67A4
67A4
8C2
8C2
23A6
7A7
7B1
8D8
6B1
6B1
14C5
14C5
14C5
14C5
14C5
14C5
14C5
14D5
7C4
14D5
7C4
12B1
14D5
7A4
14C5
8C8
14D5
7C4
7C4
14D5
6B1
6B1
OUT
OUT
OUT
OUT
OUT
OUT
OUT
TX0_P
TX0_N
TX1_N
TX1_P
TX2_P
TX2_N
TXC_P
SCLDDC
SDADDC
SDG_P
TEST
EXT_SWING
TXC_N
SGND1
SGND0
PGND2
AGND0
AGND1
AGND2
GND1
SPGND
GND0
HTPLG
A1
SDSDA
SDSCL
RESET*
EXT_RES
SDI_P
SDI_N
SDC_P
SDC_N
SDB_P
SDB_N
SDR_N
SDR_P
SDG_N
VCC1
VCC0
VCC2
AVCC0
AVCC1
PVCC1
PVCC2
SVCC0
SVCC1
SPVCC
OVCC
CORESDVO RCVR
I2C MASTERINTER
TEXT MODECONFIG/PRGRM
DIFF SIGDATA
OUT
IN
IN
IN
IN
IN
IN
IN
IN
NC
OUT
OUT
IO
IO
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
R9200 INSURES ESD DIODECURRENT IS SMALL
5.5V TOL INPUT
MINI DVI CONN J9401
3.3V ACTIVE OUTPUT
PLACE R9200,U9201 CLOSE TOTMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH
TMDS_I2C_SCL AND TMDS_I2C_SDA DON’T NEED TO CONNECT
ONE 0.1UF AND 1000PF FOR EACH PIN
ONE 0.1UF AND 1000PF FOR EACH PIN
MCH SDVO CHANNEL R,G,B,CLK SIGNAL TO TMDS CHIP
IF HIGH, ADDRESS=0X72ADDRESS=0X70NC
PLACE THE CAP NEAR THE NB SIDE
ONE 0.1UF AND 1000PF FOR EACH PIN
"Place R9250 near U2300.F12"
=PP3V3_S0_TMDS
402MF-LF1/16W5%100KR9250
402X5R16V10%
0.1UFC9220
402X5R10% 16V0.1UFC9219
402MF-LF1/16W5%
10KR9200
402MF-LF
1/16W
270K5%
R9213
2 TMDS_HTPLG_BUFTMDS_HTPLG_R
TMDS_SDB_P
TMDS_SDC_PTMDS_SDC_N
SDVO_CTRLCLK
PEG_D2R_N<1>
DVI_HOTPLUG_DET
=PP3V3_S0_TMDS
TMDS_TX_P<0>
TMDS_I2C_SCL
TMDS_TX_N<2>TMDS_TX_P<2>TMDS_TX_N<1>TMDS_TX_P<1>
TMDS_TX_CLK_P
TMDS_EXT_SWING
TMDS_I2C_SDA
TMDS_TX_CLK_N
TMDS_TX_N<2>
TMDS_TX_P<1>
DVI_HOTPLUG_DET
=PP1V8_S0_TMDS
PEG_R2D_C_N<1>
PEG_R2D_C_P<1>
TMDS_SDR_N
TMDS_SDB_N
TMDS_TX_N<0>
TMDS_TX<1>
TMDS_TX<2>
TMDS_TX_CLK
PP1V8_S0_ANALOG_SDVO_FPP3V3_S0_PVCC2_TMDS_F
PP3V3_S0_ANALOG_TMDS_FPP1V8_S0_TMDS_F
TMDS_SDG_PTMDS_SDG_N
TMDS_INT_PTMDS_INT_N
PEG_R2D_C_N<0>
PP3V3_S0_PVCC1_TMDS_F
PP3V3_S0_ANALOG_SDVO_F
PEG_R2D_C_P<0>
MIN_LINE_WIDTH=0.3MMMIN_NECK_WIDTH=0.25MM
VOLTAGE=3.3VPP3V3_S0_PVCC1_TMDS_F
PP3V3_S0_ANALOG_SDVO_FVOLTAGE=3.3V
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.3MM
=PP3V3_S0_TMDS
MIN_LINE_WIDTH=0.3MMVOLTAGE=3.3V
MIN_NECK_WIDTH=0.25MM
PP3V3_S0_PVCC2_TMDS_F
TMDS_RST_L
TMDS_TX_N<1>
TMDS_TX_CLK_NTMDS_TX_CLK_P
PP1V8_S0_ANALOG_SDVO_F
MIN_NECK_WIDTH=0.25MM
VOLTAGE=1.8VMIN_LINE_WIDTH=0.5MM
PP3V3_S0_ANALOG_TMDS_F
=PP3V3_S0_TMDS
=PP3V3_S0_TMDS
=PP3V3_S0_TMDS
=PP1V8_S0_TMDS TMDS_TX_P<0>
MIN_NECK_WIDTH=0.25MM
VOLTAGE=3.3VMIN_LINE_WIDTH=0.5MM
PP3V3_S0_ANALOG_TMDS_FVOLTAGE=1.8V
MIN_NECK_WIDTH=0.25MMMIN_LINE_WIDTH=0.5MM
PP1V8_S0_TMDS_F
TMDS_SDR_P
TMDS_TX_N<0>TMDS_TX<0>
TMDS_TX_P<2>
=PP3V3_S0_TMDS
PEG_R2D_C_N<3>
PEG_R2D_C_P<3>
TMDS_EXT_RES
PEG_R2D_C_N<2>
PEG_R2D_C_P<2>
SDVO_CTRLDATA
76
SYNC_DATE=06/06/2005EXTERNAL TMDS
01
68
SYNC_MASTER=GRAPHIC
051-7455
49.91%
MF-LF1/16W402
21
R9207
PEG_D2R_P<1> 21
10%X5R16V402
0.1UF2
1C9221
10UF20%X5R6.3V603
2
1C9204
10UF20%
X5R6.3V
6032
1 C9213
1K5%
MF-LF1/16W
4022
1R9203
SOT-553
CRITICAL
74LVC1G17DRL4
5
1 3
U9201
2
1
2
1
21
MF-LF402
1/16W5%10K
2
1R9206
1/16WMF-LF1%
49.9
402
21
R921049.91%
MF-LF1/16W402
21
R9240
1/16W1%
402MF-LF
49.921
R9239
MF-LF1/16W402
49.91%
21
R9209
1/16WMF-LF1%
49.9
402
21
R920849.91%
MF-LF1/16W402
21
R9238
1/16WMF-LF1%
49.9
402
21
R9237
21
16V0.1UF
X5R
10%
4022
1 C9248
402
10%
X5R
0.1UF
16V2
1 C92470.1UF
16VX5R
10%
4022
1 C9246
X5R402
0.1UF10%16V2
1 C9245
16V0.1UF
X5R
10%
4022
1 C92440.1UF10%
X5R402
16V2
1 C9243
16V10%
X5R
0.1UF
4022
1 C9242
16VX5R
10%0.1UF
4022
1C92030.1UF10%
X5R16V
4022
1C9202
16VX5R
10%0.1UF
4022
1C92110.1UF10%
X5R16V
4022
1C92090.1UF10%16V
402X5R2
1C9207
5%10K
MF-LF402
1/16W
2
1R9205
10%
X5R16V
402
0.1UF
2
1C9235
16VX5R
10%0.1UF
4022
1C92060.1UF10%
X5R16V
4022
1C9233
16VX5R
10%0.1UF
4022
1C92140.1UF10%
X5R16V
4022
1C9231
16VX5R
10%0.1UF
4022
1C9239
10%
CERM50V
0.001UF
4022
1 C9225
0.001UF10%
402
50VCERM2
1 C9222
0.001UF50VCERM
10%
4022
1 C9224
10%
CERM50V
402
0.001UF
2
1 C9223
0.001UF50VCERM
10%
4022
1 C920110%
CERM50V
0.001UF
4022
1 C9200
10%
CERM50V
0.001UF
4022
1 C9212
50VCERM
10%
402
0.001UF
2
1 C921010%
CERM50V
402
0.001UF
2
1 C9208
CERM
10%50V
0.001UF
4022
1 C9234
0.001UF50VCERM
10%
4022
1 C9232
0.001UF10%
CERM50V
4022
1 C9230
402
0.001UF50VCERM
10%2
1 C9237
X5R6.3V20%10UF
6032
1C9205
1%249
MF-LF1/16W
4022
1R9204
CRITICAL
LQFPSIL1362ACLU
34
28
10
1413
2322
2019
1716
30
42
36
48
3
4539
45
3738
3233
4041
4647
4344
98
2
26
11
27
1
29
317
25
35
21
15
241812
6
U9200
0402-LF
FERR-120-OHM-1.5A21
L9205
0402-LF
FERR-120-OHM-1.5A21
L9204
0402-LF
FERR-120-OHM-1.5A21
L9203
0402-LF
FERR-120-OHM-1.5A21
L9206
0402-LF
FERR-120-OHM-1.5A21
L9200
0402-LF
FERR-120-OHM-1.5A21
L9201
10%
CERM50V
0.001UF
4022
1 C92360.1UF10%
X5R16V
4022
1C923810UF20%6.3VX5R603
2
1 C9240
402
10%
X5R
0.1UF
16V2
1 C9241
TMDS_HTPLG
R9201
1%1/16WMF-LF
2.94KR9202
1%1/16WMF-LF
2.94K
R9211
1%1/16WMF-LF
9.09K
MF-LF1/16W
1%
R92129.09K
402 2
1
402 2
1
402 2
1
402 2
1
69C8
69C8
69C8
69C8
69C8
69C8
69C2
69C2
69C2
69C2
69C8
69C2
69C2
69B7
69B7
69B7
69B7
69C2
69B7
69B7
68D8
68D8
68D8
68D8
69B7
68D8
68D8
68C8
68C8
68C8
68C8
68D8
68C8
68C8
68B7
68B7
68B7
68B7
68C8
68B2
68B7
68B2
68B2
68B2
68B2
68B7
68B1
68B8
68B1
69B2
69B2
69B2
69B2
69B2
69A2
69A2
69B2
69B2
68D6
71D3
71D3
69B2
68D6
71D3
71D3
68B1
69B2
69A2 69A2
68D6
68B1
68B1
68B1
68D6 69B2 68B4 69B2
69B2
68B2
71D3
71D3
71D3
71D3
71D3
7C4
15A3
23A6
7C4
68D3
68C1
68C3
68D1
68D3
68C3
68C1
68B2
68B2
7B7
14C3
14B3
68D1
68D3
68C7
68B1
68D3
14C3
68C6
68D6
14B3
68C4
68C4
7C4
68C4
27D1
68B2
68B2 68B2
68C4
68B4
7C4
7C4
7C4
7B7 68B2 68B1 68B4 68B2
68B2
7C4
14B3
14B3
14C3
14B3
15A3
14C3
69C6
VCC
125GND
A Y
VCC
125GND
A Y
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
DSG
DSG
GND
VCC
DAS1A
S2A
S1B
S2B
S1C
S2C
S1D
S2D IN
EN_L
DD
DC
DB
IO
IO
PART NUMBERALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_5_ITEM APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
DTABLE_5_ITEM
CRITICAL BOM OPTIONTABLE_5_HEAD
PART# DESCRIPTIONQTY REFERENCE DESIGNATOR(S)
NOTE: CRT_DDC_* ARE NOT 5V COMPLIANT
NC
PLACE R9452 R9453 CLOSE TO GMCH
PLACE R9454 R9455 CLOSE TO GMCH
PLACE R9450 R9451 CLOSE TO GMCH
NB VIDEO ALIASES
PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR THE CONNECTOR
TMDS(MINI DVI) INTERFACE
NC
Video Connectors
Isolation required for DVI power switch
EXTERNAL VIDEO (VGA) INTERFACE
PLACE THE RESISTOR CLOSE TO GMCH AND THE CAP NEAR CONNECTOR
AND GROUND A 1.3K OHM 1% RESISTOR IS REQUIRED BETWEEN CRT_IREF
DVI power DIODE on page 95 (D9500)
514-0376
F94041 2
0.5AMP-13.2V
CRITICAL
SM-LF
C94101
2 CERM50V10%
402
0.001UF
C94601
2402CERM10V20%0.1UF
R94621
2
2.2K5%
402MF-LF1/16W
R94631
2
5%2.2K
4021/16WMF-LF
C94421
240250VCERM
33PF5%
NOSTUFF
C94111
2402
5%CERM50V100PF
C94431
240250VCERM5%33PF
NOSTUFF
402X5R10%
C94211
2
0.1UF16V
U9404
5
47
8
3
USSN74LVC2G125DCU
CRITICAL
U9404
2
41
8
6
SN74LVC2G125DCUUS
CRITICAL
L9405
1
2 3
4
CRITICAL
1210-4SM190-OHM-100MA
L9406
1
2 3
4
1210-4SM190-OHM-100MA
CRITICAL
300-OHM-50MAL9404
1
2 3
4
1210-4SM
CRITICAL
L9407
1
2 3
4
CRITICAL
90-OHM-100MA1210-4SM1
Q9401
3
5
4
SSM6N15FESOT563 Q9401
6
2
1
SSM6N15FESOT563
R94221
2402
2.2K5%
MF-LF1/16W
R94611 2
MF-LF402
395%
1/16W
R94701 2
402
1/16WMF-LF
5%
39
R94711 2
402
395%
MF-LF1/16W
C94391
210%16VX5R
0.1UF
402
C94121
25%CERM
100PF50V
402
U94014
7
9
12
15
8
1
2
5
11
14
3
6
10
13
16
TS3V330
SOP
CRITICAL
R94511
2
75
402
1%
MF-LF1/16W
R94531
2
75
MF-LF1/16W1%
402
R94501
2
751%1/16WMF-LF402
R94521
2
751%
402MF-LF1/16W
R94551
2402MF-LF1/16W1%75
R94541
2402MF-LF1/16W1%75
R94661
2
1/16W
402
5%
MF-LF
2.2KR94671
2
5%1/16WMF-LF
2.2K
402
FL9400
2 7
3 6
4 5
1 8
CRITICAL
MEA2010P-SM210MHZ
D9401
12
1SS418SOD-723
CRITICAL
MINI-DVI-M42-BLKF-RT-TH
OMIT
31
27
19
36353433
24
29
22
16
15
14
13
12
11
32
30
28
10
9
25
18
26
1
2
3
4
5
6
7
8
20
17
J9401
C94041
2
0.1UF20%10VCERM402
L94441 2
600-OHM-300MA
0402
R94601 2
402
1/16WMF-LF
5%
39
R94691 2
1%
MF-LF1/16W
1.21K
402
R94211
24021/16WMF-LF
5%2.2K
740S0044 740S0028 F9404?
514-0481 FANCYCRITICALJ9401CONN,REC,MINI-DVI,32P,RA,TABS,BLK1
051-7455
MINI-DVI CONNECTORSYNC_DATE=05/21/05SYNC_MASTER=EUGENE
7669
01514-0480 NORMALCRITICALJ9401CONN,REC,MINI-DVI,32P,RA,TABS,MG31
=GND_CHASSIS_TMDS_DOWN
CRT_DDC_CLK
=PP3V3_S0_TMDS
TMDS_HTPLG
CRT_VSYNC_RMAKE_BASE=TRUE
=GND_CHASSIS_TMDS_UPPER
TMDS_TX_CONN_N<0>
TMDS_TX_CONN_CLK_P
TMDS_TX_CONN_CLK_N
VGA_BVGA_HSYNC
VGA_GVGA_VSYNC
VGA_R
TMDS_TX_CONN_P<2>
TMDS_TX_CONN_N<1>
TMDS_TX_CONN_P<0>
PP5V_S0_DVIPORT_D
CRT_REDMAKE_BASE=TRUE
CRT_BLUEMAKE_BASE=TRUE
TV_C_DAC
=TV_C_RTN
=CRT_GREEN_L
=TV_B_RTN
=CRT_BLUE_L
=TV_A_RTN
TV_A_DAC
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.5 MM
PP5V_S0_TMDS_FUSE
MAKE_BASE=TRUE
TV_A_DAC=CRT_TVO_IREF=TV_A_DAC
=TV_C_DAC
=CRT_VSYNC_RCRT_HSYNC_R
MAKE_BASE=TRUE
=CRT_RED
=CRT_GREEN CRT_GREENMAKE_BASE=TRUE
MAKE_BASE=TRUE
CRT_TVO_IREF
MAKE_BASE=TRUETV_C_DAC
CRT_HSYNC_LS_R
CRT_VSYNC_LS
CRT_HSYNC_R
SB_CRT_TVOUT_MUX_L
EXT_Y_G
EXT_C_R
CRT_GREEN
TMDS_TX_P<2>
TMDS_TX_P<1>
TMDS_TX_N<0>
TMDS_TX_P<0>
TMDS_TX_CLK_P
=CRT_RED_L
TMDS_TX_CLK_N
CRT_DDC_DATA
=GND_CHASSIS_TMDS_UPPER
VOLTAGE=5VMIN_LINE_WIDTH=0.5 MMMIN_NECK_WIDTH=0.25 MM
PP5V_S0_DVIPORT
TV_DCONSEL<1>
=PP3V3_S0_NB
CRT_TVO_IREF
VGA_HSYNC
VGA_VSYNC
=PP3V3_S0_TMDS
CRT_HSYNC_LS
CRT_VSYNC_R CRT_VSYNC_LS_R
CRT_BLUE
EXT_COMPVID_B
MIN_LINE_WIDTH=0.30 MM
=PP5V_S0_TMDSVOLTAGE=5V
MIN_NECK_WIDTH=0.20 MM
MAKE_BASE=TRUETV_B_DAC
TV_DCONSEL<0>
=CRT_BLUE
=PP3V3_S0_TMDS
CRT_RED
TV_B_DAC
=TV_B_DAC
TMDS_TX_N<1>
TMDS_TX_N<2>
TMDS_TX_CONN_P<1>
TMDS_TX_CONN_N<2>
=CRT_HSYNC_R
PP5V_S0_DVIPORT
GPU_CRT_DDC_CLK
GPU_CRT_DDC_DATA
69C2
69C8
69C8
69B7
69B7
69C2
68D8
68D8
68D8
68C8
68C8
68C8
68B7
68B7
68B7
68B2
68B2
68B2
68B1
71C3
69C4
71C3
71C3
71C3
71C3
71C3
71C3
71C3
71C3
71C3
71C3
71C3
68C3
68D3
68D1
68D3
68C3
68C1
69A4
71C3
68B1
71C3
71C3
68B1
71C3
71C3
68D1
68C1
8A6
14B5
7C4
68A8
69C3
8C8
69C1
69C1
69A8
69B8
69D7
14B5
14B5
14B5
14B5
14B5
69D7
69B8
14A5
14C5
14B5
14A5
69C3
14B5
14B5 69A8
69D8
69A8
69D5
24D2
69D5
68B2
68B2
68B2
68B2
68B2
14B5
68B2
14B5
8C8
69B4
14B5
7C4
69D7
69B4
69B4
7C4
69D5
69D5
7A7
14B5
14B5
7C4
69D5
69D7
14B5
68B2
68B2
14B5
69D4
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
(FSB_CPURST_L)
(See above)
specifying a target differential impedance.Intel says to route with 7 mil spacing withoutNOTE: 7 mil gap is for VCCSense pair, which
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4
(See above)
Most CPU signals with impedance requirements are 55-ohm single-ended.
ELECTRICAL_CONSTRAINT_SET
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3
CPU Signal Constraints
All FSB signals with impedance requirements are 55-ohm single-ended.
NOTE: Design Guide allows closer spacing if signal lengths can be shortened.
Some signals require 27.4-ohm single-ended impedance.
Design Guide recommends FSB signals be routed only on internal layers.
Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.
Design Guide recommends each strobe/signal group is routed on the same layer.
DG recommends at least 25 mils, >50 mils preferred
SPACING
NET_TYPE
PHYSICAL
CPU / FSB Net Properties
(See above)
(See above)
FSB (Front-Side Bus) Constraints
Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.
DSTB complementary pairs are spaced 1:1 and routed as differential pairs.
NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.
?=2:1_SPACINGFSB_ADDR2ADDR *
=1:1_DIFFPAIR=1:1_DIFFPAIRFSB_DSTB_55S =55_OHM_SE* =55_OHM_SEY =55_OHM_SE
?FSB_ADDR =3:1_SPACING*
FSB_ADDR2ADDR*FSB_ADDR FSB_ADDR
FSB_ADDR2ADSTBFSB_ADDR FSB_ADSTB *
FSB_DSTBFSB_DATA * FSB_DATA2DSTB
CPU_55S =55_OHM_SE=55_OHM_SE* =55_OHM_SEY =STANDARD =STANDARD
?*CPU_GTLREF 25 MIL
051-745576
CPU/FSB ConstraintsSYNC_DATE=06/08/2006SYNC_MASTER=WFERRY
70
01
?=3:1_SPACINGFSB_ADSTB *
FSB_DATA2DATAFSB_DATA *FSB_DATA
?=2:1_SPACING*CPU_ITP
25 MIL ?CPU_COMP *
=2:1_SPACING*FSB_DATA2DATA ?
?CPU_2TO1 * =2:1_SPACING
=3:1_SPACING*FSB_DSTB ?
* Y =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SECPU_27P4S 7 MIL 7 MIL
=3:1_SPACING*FSB_DATA2DSTB ??=3:1_SPACING*FSB_ADDR2ADSTB
?CPU_VCCSENSE * 25 MIL
?=2:1_SPACING*FSB_COMMON
=3:1_SPACINGFSB_DATA * ?
=STANDARDFSB_55S =55_OHM_SE* =55_OHM_SEY =55_OHM_SE =STANDARD
CPU_55S CPU_ITP XDP_TDIXDP_TDI
CPU_55S CPU_ITP XDP_TDOXDP_TDO
CPU_55S CPU_ITP XDP_TMSXDP_TMS
CPU_55S CPU_ITP XDP_TCKXDP_TCK
CPU_55S CPU_ITP XDP_TRST_LXDP_TRST_L
XDP_BPM_L<4..0>XDP_BPM_L CPU_ITPCPU_55S
IMVP6_VSEN_PCPU_VCCSENSECPU_27P4S
CPU_27P4S IMVP6_VSEN_NCPU_VCCSENSE
CPU_VCCSENSE CPU_VCCSENSE_PCPU_VCCSENSECPU_27P4S
CPU_VCCSENSE CPU_VCCSENSE_NCPU_VCCSENSECPU_27P4S
IMVP6_VID<6..0>CPU_2TO1CPU_55S
CPU_2TO1 CPU_VID<6..0>CPU_55S
ITP_CPURST_LCPU_ITPCPU_55S
XDP_CLK_PCLK_FSB_100D CLK_FSB
CLK_FSBCLK_FSB_100D XDP_CLK_N
CPU_55S CPU_ITPXDP_BPM_L5 XDP_BPM_L<5>
CPU_55S NB_BSEL<2>CPU_2TO1
CPU_COMP<3>CPU_COMP CPU_55S CPU_COMP
NB_BSEL<0>CPU_2TO1CPU_55S
CPU_55S CPU_GTLREF CPU_GTLREFCPU_GTLREF
CPU_55S CPU_2TO1 IMVP_DPRSLPVRPM_DPRSLPVRCPU_2TO1PM_DPRSLPVR CPU_55S
CPU_55SFSB_CPUSLP_L FSB_CPUSLP_LPM_THRMTRIP_LCPU_2TO1CPU_55SPM_THRMTRIP_L
CPU_IERR_LCPU_55SCPU_IERR_L
CPU_2TO1CPU_55SCPU_BSEL2 CPU_BSEL<2>
FSB_DATAFSB_DATA_GROUP2 FSB_D_L<47..32>FSB_55S
FSB_DATA_GROUP1 FSB_DATA FSB_D_L<31..16>FSB_55S
FSB_COMMON FSB_TRDY_LFSB_COMMONFSB_55S
FSB_COMMON FSB_55S FSB_BPRI_LFSB_COMMON
FSB_COMMON FSB_ADS_LFSB_COMMONFSB_55S
FSB_COMMON FSB_55S FSB_DBSY_LFSB_COMMON
FSB_COMMON FSB_55S FSB_BREQ0_LFSB_COMMON
FSB_DATA_GROUP0 FSB_55S FSB_DATA FSB_DINV_L<0>
FSB_COMMON FSB_RS_L<2..0>FSB_COMMONFSB_55S
FSB_COMMON FSB_LOCK_LFSB_COMMONFSB_55S
FSB_COMMON FSB_DRDY_LFSB_COMMONFSB_55S
FSB_COMMON FSB_DPWR_LFSB_COMMONFSB_55S
FSB_COMMON FSB_HITM_LFSB_COMMONFSB_55S
FSB_CPURST_L FSB_CPURST_LFSB_COMMONFSB_55S
FSB_COMMON FSB_DEFER_LFSB_COMMONFSB_55S
FSB_ADDRFSB_ADDR_GROUP0 FSB_55S FSB_REQ_L<4..0>
FSB_DSTB_L_P<3>FSB_DSTBFSB_DSTB3 FSB_DSTB_55S
FSB_D_L<63..48>FSB_DATA_GROUP3 FSB_55S FSB_DATA
FSB_DSTB FSB_DSTB_L_N<0>FSB_DSTB_55S
FSB_DSTB0 FSB_DSTB FSB_DSTB_L_P<0>FSB_DSTB_55S
FSB_COMMON FSB_BNR_LFSB_COMMONFSB_55S
FSB_DINV_L<3>FSB_DATA_GROUP3 FSB_55S FSB_DATA
FSB_DSTB_L_N<1>FSB_DSTBFSB_DSTB_55S
FSB_55SFSB_DATA_GROUP0 FSB_DATA FSB_D_L<15..0>
FSB_DSTB1 FSB_DSTB FSB_DSTB_L_P<1>FSB_DSTB_55S
FSB_DATA_GROUP1 FSB_DATAFSB_55S FSB_DINV_L<1>
FSB_COMMON FSB_HIT_LFSB_55S FSB_COMMON
FSB_DINV_L<2>FSB_DATA_GROUP2 FSB_DATAFSB_55S
FSB_DSTB_L_P<2>FSB_DSTBFSB_DSTB2 FSB_DSTB_55S
FSB_DSTB_L_N<2>FSB_DSTB_55S FSB_DSTB
FSB_DSTB_L_N<3>FSB_DSTBFSB_DSTB_55S
FSB_ADDR_GROUP0 FSB_55S FSB_A_L<16..3>FSB_ADDR
FSB_ADSTBFSB_ADSTB1 FSB_ADSTB_L<1>FSB_55S
FSB_A_L<35..17>FSB_ADDR_GROUP1 FSB_55S FSB_ADDR
FSB_55S FSB_ADSTB FSB_ADSTB_L<0>FSB_ADSTB0
CPU_FERR_L CPU_FERR_LCPU_55S
CPU_PROCHOT_L CPU_PROCHOT_LCPU_2TO1CPU_55S
CPU_PWRGD CPU_PWRGDCPU_55S
CPU_55S CPU_INTRCPU_FROM_SB
CPU_FROM_SB CPU_NMICPU_55S
CPU_INIT_L CPU_55S CPU_INIT_LCPU_FROM_SB CPU_SMI_LCPU_55S
CPU_COMPCPU_27P4S CPU_COMP<0>CPU_COMP
CPU_55S CPU_STPCLK_LCPU_FROM_SB
CPU_BSEL0 CPU_BSEL<0>CPU_2TO1CPU_55S
CPU_FROM_SB CPU_DPSLP_LCPU_55S
CPU_COMPCPU_COMP CPU_COMP<1>CPU_55S
CPU_COMP<2>CPU_COMP CPU_COMPCPU_27P4S
CPU_DPRSTP_L CPU_55S CPU_2TO1 CPU_DPRSTP_L
NB_BSEL<1>CPU_55S CPU_2TO1
CPU_FROM_SB CPU_A20M_LCPU_55S
CPU_FROM_SB CPU_IGNNE_LCPU_55S
CPU_2TO1 CPU_BSEL<1>CPU_BSEL1 CPU_55S
12B3
45B3
59C8
59C7
12B3
12B5
12B2
12B2
12B3
12B3
59A5
59A5
59D8
22C2
13C5
13C5
13A5
13A3
13B5
13D5
13D3
45C3
22C4
46B2
22C4
9C6
9C6
9C6
9C6
9C6
12B2
59A4
59A4
59C7
12B2
29B8
29C8
24C3
13A5
15A6
29A6
13B5
9C4
13B3
13C3
13C3
13B3
13B3
13B3
13A3
13B3
13B3
13B3
13B3
12B5
13B3
9D8
13A3
9C2
13B3
13B3
13C3
13B3
13B3
13C5
13B3
13B3
13B3
13B3
13A3
13B3
13B3
13C3
13C3
13C3
13C3
22C2
45B5
12B1
22C4
22C4
22C4
22C4
22C4
29C6
22C4
15B6
29B8
22C4
22C4
29B6
9B7
9A7
9B7
9A7
9A7
9C6
10A6
10A6
10B7
75C3
75C3
9C5
15B6
9B3
15C6
9B4
59C7
15A6
9A2
9C6
9D6
9A4
9C2
9B4
9D6
9D6
9D6
9D6
9D6
9C4
9D6
9D6
9D6
9B2
9C6
9D6
9D6
9C8
9B2
9B2
9C4
9C4
9D6
9B2
9B4
9C4
9B4
9B4
9C6
9C2
9C2
9C2
9B2
9D8
9C8
9C8
9D8
9C8
9C5
9B2
9B8
9B8
9D6
9B8
9B3
9B8
9B4
9B2
9B3
9B3
9B2
15C6
9C8
9C8
9A4
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
SPACING
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5
Video Signal Constraints
DG Says 30 mil spacing minimum
LVDS signals are 100-ohm +/- 20% differential impedence.
- 50-ohm +/- 15% from first to second termination resistor.- 55-ohm +/- 15% from second termination resistor to connector.
CRT & TVDAC signal single-ended impedence varies by location:
DG Says 40 mil spacing minimum
DG Says 40 mil spacing minimum
NET_TYPE
PHYSICALELECTRICAL_CONSTRAINT_SET
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.
CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.
- 37.5-ohm +/- 15% from GMCH to first termination resistor.
PCI-Express / DMI Bus Constraints
CRT_SYNC 25 MIL* ?
?* 25 MILTVDAC
*TVDAC TVDAC TVDAC_2TVDAC
?* 25 MILCRT
=STANDARD=STANDARDY* =55_OHM_SECRT_55S =55_OHM_SE =55_OHM_SE
LVDS_100D =100_OHM_DIFFY* =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* Y =100_OHM_DIFFDMI_100D =100_OHM_DIFF
CRT_50S =50_OHM_SE =STANDARD* Y =STANDARD=50_OHM_SE =50_OHM_SE
?*LVDS 20 MIL
01
SYNC_DATE=06/12/2006
NB ConstraintsSYNC_MASTER=WFERRY
71
051-745576
20 MIL ?*CRT_2CRT
?*PCIE 20 MIL
CRT_SYNC2SYNCCRT_SYNCCRT_SYNC *
*CRT CRT CRT_2CRT
20 MILCRT_SYNC2SYNC ?*
=100_OHM_DIFF=100_OHM_DIFFY*PCIE_100D =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF
* ?20 MILDMI
20 MIL ?*TVDAC_2TVDAC
PEG_D2R_P<1>PCIE_100D PCIE
PEG_D2R_N<1>PEG_R2D PCIE_100D PCIE
DMI_N2S_P<3..0>DMIDMI_N2S DMI_100D
DMI_N2S_N<3..0>DMIDMI_100D
DMI_S2N DMI_S2N_P<3..0>DMI_100D DMI
LVDS_100D LVDS LVDS_A_CLK_PLVDS_A_CLK
LVDS_100D LVDS_A_CLK_NLVDS_A_CLK LVDS
LVDSLVDS_100D LVDS_A_DATA_N<2..0>LVDS_A_DATA
LVDS_100D LVDS LVDS_A_DATA_P<3>LVDS_A_DATA3
LVDS_100D LVDS LVDS_A_DATA_N<3>LVDS_A_DATA3
LVDSLVDS_100D LVDS_A_DATA_P<2..0>LVDS_A_DATA
CRT_TVO_IREF CRT_TVO_IREFCRT
DMI_S2N_N<3..0>DMI_100D DMI
PEG_R2D_C_N<3..0>PCIE_100D PCIE
TV_B_DAC TVDAC TV_B_DACCRT_50S
CRT_HSYNC_RCRT_SYNC CRT_55S CRT_SYNC
PEG_R2D_C_P<3..0>PCIE_100D PCIE
LVDS LVDS_IBGLVDS_IBG
CRT_BLUECRT_50S CRTCRT_BLUE
CRT_GREENCRT_50S CRTCRT_GREEN
CRT_REDCRT_50S CRTCRT_RED
CRT_VSYNC_RCRT_SYNCCRT_55SCRT_SYNC
TV_A_DAC TV_A_DACTVDACCRT_50S
TV_C_DAC TVDAC TV_C_DACCRT_50S
68C6
23D2
68B6
68C6
68B6
68B6
23D2
23D2
23D2
67B3
67B3
67B2
67B2
69D8
15C3
14C3
69D7
69D5
68B6
67A8
69D5
69D5
69D5
69D5
69D7
69D7
14C3
14D3
15B3
15B3
15B3
14C5
14C5
14C5
14C5
69D7
15B3
14B3
69A8
69C3
14B3
14D5
69B8
69A8
69A8
69C3
69B8
69A8
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
AREA_TYPE SPACING_RULE_SETNET_SPACING_TYPE1 NET_SPACING_TYPE2TABLE_SPACING_ASSIGNMENT_HEAD
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_ASSIGNMENT_ITEM
Need to support MEM_*-style wildcards!
DDR2 Memory Bus ConstraintsPHYSICALELECTRICAL_CONSTRAINT_SET
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2
SPACING
NET_TYPE
Memory Net Properties
MEM_DATA2MEMMEM_DATA *MEM_DQS
MEM_DATA2MEMMEM_DATA *MEM_CMD
* MEM_CLK2MEMMEM_CTRLMEM_CLK
* MEM_CLK2MEMMEM_CLKMEM_CLK
*MEM_CMD MEM_CMD2MEMMEM_DATA
MEM_2OTHERMEM_CTRL * *
MEM_2OTHERMEM_CMD **
MEM_2OTHERMEM_DATA * *
MEM_2OTHERMEM_DQS **
MEM_2OTHERMEM_CLK ** MEM_DQS MEM_DQS2MEM*MEM_CLK
MEM_DQS MEM_DQS2MEM*MEM_DATA
* MEM_DQS2MEMMEM_DQS MEM_CMD
* MEM_DQS2MEMMEM_DQS MEM_DQS
* =4:1_SPACINGMEM_CLK2MEM ?
MEM_DATA2DATAMEM_DATAMEM_DATA *
MEM_DQS MEM_DQS2MEM*MEM_CTRL
MEM_CLK2MEMMEM_CLK *MEM_DATA
MEM_CTRL2CTRL =2:1_SPACING* ?
*MEM_CLK MEM_CLK2MEMMEM_DQS
*MEM_CMD MEM_CMD2MEMMEM_CTRL
MEM_CMD2MEM * =3:1_SPACING ?
MEM_DATA2MEM =3:1_SPACING* ?
MEM_DATA MEM_CTRL2MEM*MEM_CTRL
051-745572 76
01
Memory ConstraintsSYNC_MASTER=WFERRY SYNC_DATE=06/08/2006
MEM_DQSMEM_CTRL * MEM_CTRL2MEM
MEM_CTRL2CTRLMEM_CTRL *MEM_CTRL
MEM_CTRL MEM_CTRL2MEMMEM_CLK *
MEM_DQS2MEM * =3:1_SPACING ?
MEM_CMD * MEM_CTRL2MEMMEM_CTRL
* MEM_DATA2MEMMEM_DATA MEM_CLK
=1.5:1_SPACINGMEM_DATA2DATA * ?
MEM_CTRL2MEM * =3:1_SPACING ?
MEM_CMD2MEMMEM_CMD *MEM_DQS
25 MILMEM_2OTHER * ?
*MEM_CLK MEM_CLK2MEMMEM_CMD
=45_OHM_SE=45_OHM_SEY =STANDARD=45_OHM_SE =STANDARD*MEM_45S
*MEM_DATA MEM_DATA2MEMMEM_CTRL
MEM_CMD2CMD * =1.5:1_SPACING ?
*MEM_CMD MEM_CMD MEM_CMD2CMD
=55_OHM_SE =55_OHM_SE* YMEM_55S =STANDARD =STANDARD=55_OHM_SE
=70_OHM_DIFF =70_OHM_DIFFY* =70_OHM_DIFF =70_OHM_DIFF=70_OHM_DIFFMEM_70D
=85_OHM_DIFFYMEM_85D =85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFF*
MEM_CMD * MEM_CMD2MEMMEM_CLK
MEM_55S MEM_DATAMEM_B_DM3 MEM_B_DM<3>
MEM_A_CNTL MEM_45S MEM_CTRL MEM_CKE<1..0>
MEM_A_CMD MEM_A_CAS_LMEM_55S MEM_CMD
MEM_CMDMEM_A_CMD MEM_A_WE_LMEM_55S
MEM_DATAMEM_55SMEM_A_DQ_BYTE0 MEM_A_DQ<7..0>
MEM_55S MEM_DATAMEM_A_DQ_BYTE2 MEM_A_DQ<23..16>MEM_DATAMEM_55SMEM_A_DQ_BYTE1 MEM_A_DQ<15..8>
MEM_55S MEM_DATAMEM_A_DQ_BYTE6 MEM_A_DQ<55..48>MEM_A_DQ_BYTE7 MEM_A_DQ<63..56>MEM_55S MEM_DATA
MEM_55SMEM_A_DM1 MEM_DATA MEM_A_DM<1>MEM_DATAMEM_55SMEM_A_DM0 MEM_A_DM<0>
MEM_55S MEM_DATAMEM_A_DM2 MEM_A_DM<2>
MEM_A_DM<4>MEM_55S MEM_DATAMEM_A_DM4
MEM_55S MEM_DATAMEM_A_DM3 MEM_A_DM<3>
MEM_A_DM<6>MEM_55S MEM_DATAMEM_A_DM6
MEM_A_DQS_P<0>MEM_A_DQS0 MEM_DQSMEM_85D
MEM_A_DQS_N<0>MEM_DQSMEM_85D
MEM_A_DQS_N<1>MEM_DQSMEM_85D
MEM_A_DQS_P<1>MEM_A_DQS1 MEM_DQSMEM_85D
MEM_A_DQS3 MEM_A_DQS_P<3>MEM_DQSMEM_85D
MEM_A_DQS2 MEM_A_DQS_P<2>MEM_DQSMEM_85D
MEM_A_DQS_N<2>MEM_DQSMEM_85D
MEM_A_DQS4 MEM_A_DQS_P<4>MEM_DQSMEM_85D
MEM_A_DQS_N<3>MEM_DQSMEM_85D
MEM_A_DQS_N<5>MEM_DQSMEM_85D
MEM_A_DQS_N<4>MEM_DQSMEM_85D
MEM_A_DQS5 MEM_A_DQS_P<5>MEM_DQSMEM_85D
MEM_A_DQS6 MEM_A_DQS_P<6>MEM_DQSMEM_85D
MEM_70D MEM_CLK MEM_CLK_N<5..3>
MEM_CKE<4..3>MEM_CTRLMEM_45SMEM_B_CNTL
MEM_CTRLMEM_45S MEM_CS_L<3..2>MEM_B_CNTL
MEM_CMDMEM_55S MEM_B_A<14..0>MEM_B_CMD
MEM_CMDMEM_55S MEM_B_WE_LMEM_B_CMD
MEM_55S MEM_DATAMEM_B_DQ_BYTE1 MEM_B_DQ<15..8>MEM_DATAMEM_55SMEM_B_DQ_BYTE0 MEM_B_DQ<7..0>
MEM_55S MEM_DATAMEM_B_DQ_BYTE3 MEM_B_DQ<31..24>MEM_55S MEM_DATAMEM_B_DQ_BYTE2 MEM_B_DQ<23..16>
MEM_55S MEM_DATAMEM_B_DQ_BYTE4 MEM_B_DQ<39..32>
MEM_55S MEM_DATAMEM_B_DQ_BYTE6 MEM_B_DQ<55..48>MEM_55S MEM_DATAMEM_B_DQ_BYTE5 MEM_B_DQ<47..40>
MEM_DATAMEM_55SMEM_B_DM0 MEM_B_DM<0>
MEM_55S MEM_DATAMEM_B_DQ_BYTE7 MEM_B_DQ<63..56>
MEM_55S MEM_DATAMEM_B_DM2 MEM_B_DM<2>MEM_55S MEM_DATAMEM_B_DM1 MEM_B_DM<1>
MEM_55S MEM_DATAMEM_B_DM5 MEM_B_DM<5>MEM_55S MEM_DATAMEM_B_DM4 MEM_B_DM<4>
MEM_55S MEM_DATAMEM_B_DM6 MEM_B_DM<6>MEM_55S MEM_DATAMEM_B_DM7 MEM_B_DM<7>
MEM_DQSMEM_85DMEM_B_DQS0 MEM_B_DQS_P<0>
MEM_DQSMEM_85DMEM_B_DQS1 MEM_B_DQS_P<1>MEM_DQSMEM_85D MEM_B_DQS_N<0>
MEM_DQSMEM_85DMEM_B_DQS2 MEM_B_DQS_P<2>MEM_DQSMEM_85D MEM_B_DQS_N<1>
MEM_DQSMEM_85D MEM_B_DQS_N<2>
MEM_B_DQS_N<3>MEM_DQSMEM_85D
MEM_DQSMEM_85DMEM_B_DQS3 MEM_B_DQS_P<3>
MEM_DQSMEM_85D MEM_B_DQS_N<4>MEM_DQSMEM_85DMEM_B_DQS4 MEM_B_DQS_P<4>
MEM_DQSMEM_85DMEM_B_DQS5 MEM_B_DQS_P<5>
MEM_DQSMEM_85DMEM_B_DQS6 MEM_B_DQS_P<6>MEM_DQSMEM_85D MEM_B_DQS_N<5>
MEM_DQSMEM_85DMEM_B_DQS7 MEM_B_DQS_P<7>MEM_DQSMEM_85D MEM_B_DQS_N<6>
MEM_DQSMEM_85D MEM_B_DQS_N<7>
MEM_CLK_N<2..0>MEM_CLKMEM_70D
MEM_A_CNTL MEM_CS_L<1..0>MEM_45S MEM_CTRL
MEM_A_CNTL MEM_ODT<1..0>MEM_CTRLMEM_45S
MEM_55SMEM_A_CMD MEM_A_A<14..0>MEM_CMD
MEM_55SMEM_A_CMD MEM_A_BS<2..0>MEM_CMD
MEM_A_CMD MEM_A_RAS_LMEM_55S MEM_CMD
MEM_55S MEM_DATAMEM_A_DQ_BYTE3 MEM_A_DQ<31..24>MEM_A_DQ<39..32>MEM_55S MEM_DATAMEM_A_DQ_BYTE4
MEM_A_DQ<47..40>MEM_55S MEM_DATAMEM_A_DQ_BYTE5
MEM_A_DM<7>MEM_A_DM7 MEM_55S MEM_DATA
MEM_A_DM<5>MEM_55S MEM_DATAMEM_A_DM5
MEM_CLK_P<2..0>MEM_A_CLK MEM_70D MEM_CLK
MEM_A_DQS_N<7>MEM_85D MEM_DQS
MEM_70D MEM_CLKMEM_B_CLK MEM_CLK_P<5..3>
MEM_A_DQS7 MEM_A_DQS_P<7>MEM_DQSMEM_85D
MEM_A_DQS_N<6>MEM_DQSMEM_85D
MEM_CMDMEM_55S MEM_B_CAS_LMEM_B_CMD
MEM_CMDMEM_55S MEM_B_RAS_LMEM_B_CMD
MEM_CMDMEM_55SMEM_B_CMD MEM_B_BS<2..0>
MEM_CTRLMEM_45S MEM_ODT<3..2>MEM_B_CNTL
32B5 32A5
32C6
31C6
30C6
31C4
30C4
32D6
32D6
31B6
31B6
30B6
32C6
30D6
30B6
32A6
32D6
30A6
32D5
31B6
31B4
31B6
31B4
31A6
32D6
32D6
30B4
30C6
30D4
30B6
30B4
31C6
32D6
30C6
32B6
32B6
30D6
30C6
30D6
30A6
30A4
31D4
31C6
31B4
16C1
32A6
31D6
31D6
31C6
31C6
31B4
31A6
31A6
31A4
30D4
30B6
30B6
16C5
30B6
32B6
30C6
30B4
30A6
30D4
31D4
32A6
32A6
31B6
31B6
31C6
30C4
30B6
30B6
30D4
30C4
30D4
30A4
16B8
30D4
30D4
30C6
30B4
30C4
30A6
30D6
30D6
30D6
30D6
30C6
30C4
30C4
30B6
30C6
30B4
30B6
30B4
30A4
31A4
31C4
15D3
16B1
31B6
31D4
31D4
31C4
31C4
16C4
31A4
31A4
31D4
16B4
31C4
31D4
31A6
31B4
31A4
31A6
31D6
31D6
31D6
31C6
31D6
31C6
31C4
31C4
31B6
31B6
31A4
31A6
31B4
31A4
31A6
31A4
30A4
30B4
30B4
16B5
30B4
30B4
30C4
16C8
30A4
30A4
30B6
30A4
30A6
31A4
30A6
30A4
31B6
31B4
31B4
31B4
16C1
15D3
16D5
16B5
16D8
16C8
16C8
16B8
16A8
16D5
16D5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
16C5
15D3
15D3
15C3
15C6
16B1
16C4
16D4
16C4
16C4
16B4
16B4
16B4
16D1
16A4
16C1
16D1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
16C1
15D3
15D3
15C3
15C6
16D5
16B5
16C8
16B8
16B8
16C5
16C5
15D3
16C5
15D3
16C5
16C5
16D1
16B1
16D1
15C3
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
Disk Interface Constraints
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9
SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17
HD Audio Interface Constraints
SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1
Internal Interface Constraints
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2
PHYSICAL SPACING
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
DG says minimum spacing 50 mils to clocks
USB 2.0 Interface Constraints
* ?USB 20 MIL
HDA =1.8:1_SPACING ?*
Y =55_OHM_SE =55_OHM_SESPI_55S * =55_OHM_SE =STANDARD =STANDARD
=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF* YUSB_90D
USB_2CLK 25 MIL* ?
SMB_55S * Y =55_OHM_SE=55_OHM_SE =55_OHM_SE =STANDARD =STANDARD
01
7673
SYNC_DATE=06/12/2006
SB Constraints (1 of 2)SYNC_MASTER=WFERRY
051-7455
*SPI =1.8:1_SPACING ?
SATA * 20 MIL ?
=1.8:1_SPACINGIDE * ?
=3:1_SPACINGSMB * ?
SATA_55S =55_OHM_SE =STANDARDY =55_OHM_SE =55_OHM_SE* =STANDARD
* =55_OHM_SEIDE_55S =STANDARD=55_OHM_SE=55_OHM_SEY =STANDARD
HDA_55S =55_OHM_SE* Y =55_OHM_SE =55_OHM_SE =STANDARD=STANDARD
=100_OHM_DIFF* =100_OHM_DIFF=100_OHM_DIFFSATA_100D =100_OHM_DIFF =100_OHM_DIFFY
USB_60S =55_OHM_SE=55_OHM_SE=55_OHM_SE =STANDARD=STANDARD* Y
SPI_55S SPI SPI_CE_L<0>SPI_CE_R_L<1>SPI_CE_L1 SPISPI_55S
SPI_A_SO_RSPISPI_55S
SPISPI_55S SPI_SOSPI_SO
SPI_55S SPISPI_CE_L0 SPI_CE_R_L<0>
SPI_SI_RSPI_SI SPI_55S SPI
SPI_55S SPI SPI_A_SI_R
SPI_A_SCLK_RSPI_55S SPI
HDA_SDOUT_RHDA_55S HDA
HDA_SDOUT HDA_SDOUTHDAHDA_55S
HDA_SDIN0 HDAHDA_55S HDA_SDIN0HDA_55S HDA HDA_RST_L_R
HDA_55S HDA HDA_SYNC_R
HDA_BIT_CLK_RHDA_55S HDA
HDA_BIT_CLK HDA_55S HDA HDA_BIT_CLK
SATA SATA_A_D2R_C_NSATA_100D
HDA_SYNCHDA_55S HDAHDA_SYNC
HDA_55SHDA_RST_L HDA HDA_RST_L
USB_90D USB USB_EXTA_PUSB_EXTA
USB_EXTA_MUXED_NUSBUSB_90D
USB_MINI_NUSBUSB_90D
USB_90D USB USB_3G_PUSB_3G
USB_90D USB USB_3G_NUSB_CAMERA_PUSB_CAMERA USB_90D USB
USB_CAMERA_NUSB_90D USB
USB_BT_PUSB_BT USB_90D USB
USB_BT_NUSB_90D USB
USB_TPAD_PUSB_TPAD USB_90D USB
USB_IR_PUSB_IR USB_90D USB
USB_IR_NUSB_90D USB
USB_EXTB_NUSBUSB_90D
USB_EXCARD_PUSB_EXCARD USBUSB_90D
USB_EXCARD_NUSBUSB_90D
USB_EXTC_PUSB_EXTC USBUSB_90D
SMB_55S SMBSMB_SB_SCL SMB_CLKSMB_SB_SDA SMBSMB_55S SMB_DATA
SMB_55S SMB SMB_ME_DATASMB_SB_ME_SDA
SATA SATA_A_D2R_C_PSATA_100D
SATA_A_D2R_NSATASATA_100D
SATA_A_D2R SATA_A_D2R_PSATA_100D SATA
IDE_PDA<2..0>IDE_55SIDE_PDA IDE
IDE_PDCS1_LIDE_55S IDEIDE_PDCS
IDE_55S IDEIDE_PDIOR_L IDE_PDIOR_L
IDE_IRQ14IDE_IRQ14 IDE_55S IDE
SATA_A_R2D_C_NSATASATA_100D
SATA_A_R2D_PSATA_100D SATA
SATA_A_R2D_NSATASATA_100D
USB_90D USB USB_TPAD_N
USB_MINI_PUSB_MINI USB_90D USB
USB_EXTA_MUXED_PUSBUSB_90D
USB_90D USB USB_EXTA_N
ODD_RST_5VTOL_LIDE_RST_L IDE_55S IDE
IDE_PDIOW_LIDEIDE_55SIDE_CNTL
IDE_PDCS3_LIDE_55S IDEIDE_PDCS
IDE_PDDREQIDE_CNTL IDEIDE_55S
IDE_PDD<15..0>IDE_55S IDEIDE_PDD
IDE_PDIORDY IDE_PDIORDYIDE_55S IDE
SATA_A_R2D_C_PSATA_A_R2D SATA_100D SATA
IDE_CNTL IDE_55S IDE IDE_PDDACK_L
USB_EXTB_PUSB_EXTB USBUSB_90D
USB_90D USB_EXTC_NUSB
USB_RBIAS USB_RBIASUSB_60S
SMBSMB_55S SMB_ME_CLKSMB_SB_ME_SCL
SPI_SCLK SPI_55S SPI SPI_SCLK_R
39C5
23C2
23C2
23C2
23C2
39B5
39C3
52C3
52C7
52C3
22B8
22C8
22C8
22C8
22C8
23C2
23C2
23C2
23C2
8C2
8B2
23C2
8C2
8C2
23C2
23C2
23C2
23C2
47D8
47D8
47A8
40D4
40C4
39B3
39B5
39C3
39B5
40D4
23C2
23C2
23C2
39A8
39B5
39B3
39C3
22C4
39B5
40D4
39B3
23C2
23C2
47A8
52C7
52C6
52C4
23C5
23C5
23C5
52C4
52C5
22B6
8A6
8A6
22C6
22C6
22C6
8A6
40D7
8A6
8A6
8C1
8C1
8C1
8C1
8C1
8B1
8C1
8C1
8C1
8B1
8B1
8B1
8B1
24D5
24D5
24D5
40C7
22B6
22B6
22B4
22B4
22B4
22B4
22B6
40D7
40D7
8C1
8C1
8C1
23B6
22B4
22B4
22A4
22B4
22A4
22B6
22B4
8B1
8B1
23B3
24D5
23C5
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_PHYSICAL_RULE_ITEM
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30
Controller Link (AMT) ConstraintsSOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30
DG says 30 mils min separation.
Platform LAN (Nineveh) Constraints
ELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACINGPHYSICAL
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19
PCI Bus Constraints
?*ENET_CLK =2.5:1_SPACING
=55_OHM_SE =STANDARD* =55_OHM_SE =STANDARD=55_OHM_SEYCLINK_55S
?PCI * =2:1_SPACING
?*CLINK_VREF 12 MILS
?CLINK * =1.8:1_SPACING
25 MILSENET_MDI * ?
LAN_55S =55_OHM_SE =STANDARD* =55_OHM_SEY =55_OHM_SE =STANDARD
GLAN_100D =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFFY*
?*ENET_LAN =1.5:1_SPACING
* ?ENET_GLAN 20 MILS
Y =55_OHM_SE =STANDARD=55_OHM_SE*PCI_55S =55_OHM_SE =STANDARD
* YENET_100D =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF
01
7674
SYNC_DATE=06/12/2006SYNC_MASTER=WFERRY
SB Constraints (2 of 2)
051-7455
=STANDARD* =STANDARDY 12 MILS 5 MILS 300 MILSCLINK_12MIL
PCIE_E_R2D_C_PPCIE_E_R2D PCIEPCIE_100D
PCIE_E_R2D_C_NPCIEPCIE_100D
GLAN_COMPGLAN_COMP
ENET_LANLAN_55S LAN_RSTSYNCENET_LAN
ENET_LANENET_LAN LAN_55S LAN_R2D<2..0>
ENET_LANLAN_55SENET_LAN LAN_D2R<2..0>
INT_PIRQF_LPCI_55SINT_PIRQF_L PCI
INT_PIRQE_LPCI_55SINT_PIRQE_L PCI
INT_PIRQD_LINT_PIRQD_L PCI_55S PCI
INT_PIRQC_LINT_PIRQC_L PCI_55S PCI
INT_PIRQB_LINT_PIRQB_L PCI_55S PCI
INT_PIRQA_L PCI_55S PCI INT_PIRQA_LPCI_GNT2_L PCI_55S PCI PCI_GNT2_LPCI_REQ2_L PCI_55S PCI PCI_REQ2_LPCI_GNT1_L PCI_55S PCI PCI_GNT1_L
PCI_55S PCI PCI_FW_GNT_LPCI_FW_GNT_L
PCI_55S PCI PCI_FW_REQ_LPCI_FW_REQ_L
PCI_CNTL PCI_55S PCI PCI_FRAME_L
PCI_REQ1_L PCI_55S PCI PCI_REQ1_L
PCIE_E_D2R_PPCIE_E_D2R PCIE_100D PCIE
PCIE_100D PCIE PCIE_E_D2R_N
PCI_AD PCIPCI_55S PCI_AD<18..0>PCI_AD19 PCI_55S PCI PCI_AD<19>
PCI_AD20 PCI_55S PCI PCI_AD<20>
PCI_AD PCI_55S PCI PCI_PAR
PCI_C_BE_L PCI_55S PCI PCI_C_BE_L<3..0>PCI_CNTL PCI_55S PCI PCI_IRDY_L
PCI_CNTL PCIPCI_55S PCI_SERR_L
PCI_CNTL PCI_55S PCI PCI_STOP_L
PCI_CNTL PCI_55S PCI PCI_DEVSEL_L
PCI_LOCK_L PCI_55S PCI PCI_LOCK_L
PCI_CNTL PCI_55S PCI PCI_TRDY_L
ENET_MDI_P<2>ENET_MDI2 ENET_100D ENET_MDI
ENET_MDI3 ENET_MDI_P<3>ENET_MDIENET_100D
CLINK_NB CLINK_NB_DATACLINK_55S CLINK
CLINK_WLAN CLINK_WLAN_CLKCLINK_55S CLINK
CLINK_55S CLINKCLINK_WLAN CLINK_WLAN_DATA
CLINK_VREFCLINK_12MIL NB_CLINK_VREFNB_CLINK_VREF
ENET_CLK ENET_GLAN_CLKLAN_55S
ENET_MDI1 ENET_MDI ENET_MDI_P<1>ENET_100D
ENET_100D ENET_MDI_N<1>ENET_MDI
SB_CLINK_VREF1CLINK_12MIL CLINK_VREFSB_CLINK_VREF1
SB_CLINK_VREF0CLINK_12MIL CLINK_VREFSB_CLINK_VREF0
CLINKCLINK_WLAN_RESET_L CLINK_55S CLINK_WLAN_RESET_L
CLINK_NB_RESET_L CLINK_NB_RESET_LCLINKCLINK_55S
CLINK_55SCLINK_NB CLINK CLINK_NB_CLK
ENET_MDI_N<3>ENET_MDIENET_100D
ENET_MDI_N<2>ENET_MDIENET_100D
ENET_MDIENET_100D ENET_MDI_N<0>ENET_MDI0 ENET_100D ENET_MDI ENET_MDI_P<0>
PCI_AD PCI_55S PCI PCI_AD<31..21>
PCI_CNTL PCI_55S PCI PCI_PERR_L
ENET_GLAN_CLK ENET_CLK ENET_GLAN_CLK_RLAN_55S
37C5
37A5
37A5
37A5
37B5
37A5
37A5
37A5
37A5
37A5
37A5
33B6
33B6
23A6
23A6
23A8
23A8
23A8
23A8
23B6
37A5
23B6
23A6
23B6
33C5
23B8
37B6
37B5
37B5
37B5
23A6
23A6
23A6
23A6
23A6
23A6
36B7
36C7
24C3
36C7
36C7
24C3
24C3
36C7
36C7
36B7
36B7
37B5
23A6
33B5
33B5
22C6
23A4
23A4
23A4
23A4
23A4
23A4
23A4
23B5
23A4
23A4
23A4
33B5
33B5
23A8
23A8
23A8
23A6
23B6
23A4
23A4
23A4
23A4
23A4
23A4
34B8
34B8
15A3
24C3
24C3
15A4
34B8
34B8
24C3
24C3
24D5
15A3
15A3
34B8
34B8
34B8
34B8
23A8
23A4
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_SPACING_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6
(CK505_CPU)(CK505_CPU)
Clock Net Properties
(CK505_NB)(CK505_ITP)
(CK505_PCI2)(CK505_PCI1)
(CK505_DOT96)(CK505_DOT96)
(CPU_BSEL0)(CPU_BSEL2)
(CK505_PCI3)
(CK505_SRC5)
(CK505_SRC3)
(CK505_SRC4)
(CK505_SRC2)(CK505_SRC2)(CK505_SRC3)
(CK505_SRC4)
(CK505_SRC5)(CK505_SRC6)(CK505_SRC6)
(CK505_LVDS)(CK505_LVDS)
(CPU_BSEL2)
(CK505_SRC1)(CK505_SRC1)
(CPU_BSEL0)
(CK505_ITP)
(CK505_PCIF0)(CK505_PCIF1)
(CK505_NB)
CK505 SRC7 is project-specific
CK505 SRC8 is project-specific
CK505 PCI4 is project-specific
PHYSICAL
(CPU_BSEL0)(CPU_BSEL2)
Clock Signal ConstraintsELECTRICAL_CONSTRAINT_SET
NET_TYPE
SPACING
CK505 PCI5 is project-specific
051-7455
SYNC_DATE=06/12/2006
01
7675
SYNC_MASTER=WFERRY
Clock Constraints
=55_OHM_SE* Y =55_OHM_SE =STANDARD =STANDARD=55_OHM_SECLK_SLOW_55S
=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* YCLK_FSB_100D
=STANDARD=55_OHM_SE=55_OHM_SECLK_MED_55S Y =STANDARD=55_OHM_SE*
=100_OHM_DIFFCLK_PCIE_100D =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF* Y =100_OHM_DIFF
10 MIL* ?CLK_SLOW
20 MILCLK_PCIE ?*
20 MIL*CLK_MED ?
25 MIL*CLK_FSB ?
CLK_PCIE_100DCK505_SRC8 CLK_PCIE CK505_SRC8_PCLK_PCIE CK505_SRC8_NCLK_PCIE_100D
CLK_PCIECK505_SRC6 CLK_PCIE_100D CK505_SRC6_P
CLK_PCIE_100D CLK_PCIE CK505_SRC4_NCK505_SRC4 CLK_PCIE_100D CLK_PCIE CK505_SRC4_P
CLK_PCIE CK505_SRC5_NCLK_PCIE_100D
CLK_PCIECLK_PCIE_100D CK505_SRC6_NCLK_PCIECK505_SRC7 CLK_PCIE_100D CK505_SRC7_P
CLK_FSB_100D CLK_FSB FSB_CLK_CPU_PCLK_FSB_100D CLK_FSB FSB_CLK_CPU_N
CLK_FSB_100D CLK_FSB FSB_CLK_NB_PCLK_FSB_100D CLK_FSB FSB_CLK_NB_N
XDP_CLK_PCLK_FSBCLK_FSB_100D
CLK_MED_55S CLK_MED PCI_CLK33M_TPM
CLK_MEDCLK_MED_55S CK505_FSC
SB_CLK100M_DMI_NCLK_PCIECLK_PCIE_100D
SB_CLK14P3M_TIMERCLK_MEDCLK_MED_55S
CLK_PCIECLK_PCIE_100D NB_CLK96M_DOT_PCLK_PCIECLK_PCIE_100D NB_CLK96M_DOT_N
CLK_PCIE PEG_CLK100M_PCLK_PCIE_100D
CLK_PCIE_100D CLK_PCIE PCIE_CLK100M_MINI_N
CLK_PCIECLK_PCIE_100D NB_CLK100M_PCIE_NCLK_PCIECLK_PCIE_100D PCIE_CLK100M_MINI_P
CLK_PCIE_100D CLK_PCIE SB_CLK100M_SATA_NCLK_PCIE_100D CLK_PCIE NB_CLK100M_PCIE_P
CLK_PCIECLK_PCIE_100D SB_CLK100M_SATA_P
PCIE_CLK100M_EXCARD_PCLK_PCIE_100D CLK_PCIE
PCIE_CLK100M_EXCARD_NCLK_PCIECLK_PCIE_100D
CLK_PCIE_100D CLK_PCIE SB_CLK100M_DMI_PCLK_PCIE_100D CLK_PCIE PEG_CLK100M_N
NB_CLK100M_DPLLSS_NCLK_PCIECLK_PCIE_100D
CLK_PCIE_100D CLK_PCIE NB_CLK100M_DPLLSS_P
CLK_MEDCLK_MED_55S CK505_FSA
CLK_MED_55S SB_CLK48M_USBCTLRCLK_MED
CLK_MED_55S CLK_MED PCI_CLK33M_SMC
CLK_MED_55S CLK_MED PCI_CLK33M_FW
CLK_MED_55S CLK_MED PCI_CLK33M_LPCPLUSCLK_MED_55S CLK_MED PCI_CLK33M_SB
CLK_PCIE_100D CLK_PCIE CK505_SRC3_N
CLK_PCIECK505_SRC5 CLK_PCIE_100D CK505_SRC5_P
CK505_LVDS CLK_PCIE_100D CLK_PCIE CK505_LVDS_P
CK505_SRC1 CLK_PCIE_100D CLK_PCIE CK505_SRC1_P
CLK_MED_55S CK505_PCIF0_CLKCK505_PCIF0 CLK_MED
CK505_PCIF1 CK505_PCIF1_CLKCLK_MED_55S CLK_MED
CK505_PCI1 CK505_PCI1_CLKCLK_MED_55S CLK_MED
CK505_PCI2_CLKCLK_MED_55SCK505_PCI2 CLK_MED
CK505_PCI3_CLKCK505_PCI3 CLK_MED_55S CLK_MED
CK505_PCI4_CLKCK505_PCI4 CLK_MED_55S CLK_MED
CK505_PCI5_FCTSEL1CLK_MED_55SCK505_PCI5 CLK_MED
CK505_SRC1_NCLK_PCIE_100D CLK_PCIE
CLK_PCIE_100D CLK_PCIE CK505_LVDS_N
CK505_DOT96_27M_NCLK_PCIECLK_PCIE_100D
CK505_USB48_FSACLK_MED_55S CLK_MED
CK505_NB CLK_FSB CK505_CPU1_NCLK_FSB_100D
CK505_CPU2_ITP_SRC10_PCLK_FSBCLK_FSB_100DCK505_ITP
CLK_FSB CK505_CPU2_ITP_SRC10_NCK505_ITP CLK_FSB_100D
CK505_CPU CLK_FSB CK505_CPU0_NCLK_FSB_100D
CLK_FSB CK505_CPU1_PCLK_FSB_100DCK505_NB
CK505_CPU CK505_CPU0_PCLK_FSBCLK_FSB_100D
CLK_MED_55S CLK_MED CK505_CLK14P3M_TIMER
CK505_DOT96 CLK_PCIE_100D CLK_PCIE CK505_DOT96_27M_P
CLK_PCIE_100D CLK_PCIE CK505_SRC2_NCK505_SRC2 CLK_PCIE_100D CLK_PCIE CK505_SRC2_P
CLK_PCIE_100D CLK_PCIECK505_SRC3 CK505_SRC3_P
CLK_PCIE_100D CLK_PCIE CK505_SRC7_N
XDP_CLK_NCLK_FSB_100D CLK_FSB
29B6
29B6
29C6
29C6
29C6
29C6
29B6
29D6
29D6
44C8
37A5
46C4
29B3
29C6
29C6
29B6
29C6
29B6
29D6
29D6
29D6
29D6
29D6
29D6
29B6
29C6
29C6
28A4
28A4
28B4
28B4
28B4
28B4
28B4
29D3
29D3
29D3
29D3
29D6
29C3
29A5
29B3
29B3
33C5
29C3
33C5
29C3
29C3
29C3
29C3
29C3
29C3
29D6
29A5
29A5
29B3
29B3
29A5
28B4
28B4
29B6
28B6
29B6
28B6
29A6
28B6
29B2
28B4
28A4
29D8
28C4
28C4
28C4
28C4
28C4
28C4
29D8
28A4
28B4
28B4
6B7
6B7
6C7
6C7
6C7
6C7
6C7
9B6
9B6
13B3
13B3
70A3
29A8
23D2
24D3
8B1
8B1
29B3
15C3
29C3
22B6
15C3
22B6
23C2
8A1
8B1
29C8
24D3
29A3
29A5
6C2
23A6
6C7
6C7
28B8
6C7
28B6
8C4
28B6
8C4
28B6
6C7
6C7
28A4
6C7
6C7
6C7
6C7
6C7
6C7
28A4
6C7
6C7
6C7
70A3
TABLE_PHYSICAL_RULE_ITEM
TABLE_SPACING_RULE_ITEM
MINIMUM LINE WIDTHALLOW ROUTEON LAYER? LAYER MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAPPHYSICAL_RULE_SET
TABLE_PHYSICAL_RULE_HEAD
TABLE_PHYSICAL_RULE_ITEM
LINE-TO-LINE SPACINGLAYERSPACING_RULE_SET WEIGHTTABLE_SPACING_RULE_HEAD
TABLE_SPACING_RULE_ITEM
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARYPROPERTY OF APPLE COMPUTER, INC. THE POSSESSORAGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT OF
SIZE
D
FireWire Interface ConstraintsELECTRICAL_CONSTRAINT_SET
NET_TYPE
PHYSICAL
FireWire Net PropertiesSPACING
SPACINGPHYSICAL
NET_TYPE
ELECTRICAL_CONSTRAINT_SET
SMC SMBus Net Properties
Port 2 Not Used
FW_LPS FW_LPSFWFW_55S
FW_55S FW FW_LREQFW_LREQ
FW_55S FWFW_PINT FW_PINT
CLK_MED_55S CLK_MEDFWPHY_CLK98P304M_XI CLK98P304M_FW_XI_R
FW_D_CTL FW_55S FW FW_LINK<7..0>
CLK_MED_55S CLK_MED CLKFW_PHY_PCLKFW_PCLK CLK_MEDCLK_MED_55S CLKFW_LINK_PCLK
CLK_MEDCLK_MED_55S CLKFW_PHY_LCLKFW_LCLK CLK_MEDCLK_MED_55S CLKFW_LINK_LCLK
FWFW_55S FW_CTL<1..0>FW_D_CTL
FW_55S FW FW_LKONFW_LKON
FWFW_55S FW_LKON_R
FW_TPFW_110DFW_0_TPA FW_0_TPA_P
SMB_55S SMBSMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SDA
SMB_55S SMBSMBUS_SMC_0_S0_SDA SMBUS_SMC_0_S0_SDA
SMB_55S SMBSMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SDA
SMB_55S SMBSMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SCL
SMBSMB_55SSMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SCL
SMBSMB_55SSMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SCL
SMBSMB_55SSMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SCL
SMB_55S SMBSMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SDA
SMBSMB_55SSMBUS_SMC_MGMT_SDA SMBUS_SMC_MGMT_SDASMB_55S SMBSMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SCL
FW_110D FW_0_TPB_NFW_TP
FW_110D FW_TPFW_0_TPA FW_0_TPA_N
FW_TPFW_110D FW_1_TPB_NFW_TPFW_110DFW_1_TPB FW_1_TPB_P
FW_TPFW_110D FW_1_TPA_PFW_1_TPA
FW_TPFW_110D FW_1_TPA_NFW_1_TPA
FW_110D FW_TP FW_0_TPB_PFW_0_TPB
CLK_MEDCLK_MED_55S CLK98P304M_FW_XI
=55_OHM_SE =STANDARD=STANDARD=55_OHM_SE=55_OHM_SEFW_55S * Y
?*FW =2:1_SPACING
* Y =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFFFW_110D =110_OHM_DIFF =110_OHM_DIFF
* =3:1_SPACING ?FW_TP
051-745576
01
76
SYNC_MASTER=WFERRY SYNC_DATE=06/12/2006
FireWire & SMC Constraints
47C5
47C5
6B2
47D5
47C2
47D2
6B2
47D5
47C2
47D2
47B2
47B2