kailua-kona, 05.11.2002 marcel trimpl, bonn university readout concept for future pixel detectors...

Kailua-Kona, 05.11.2002

L ABSiliz ium Labor Bonn

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Marcel Trimpl, Bonn University

Readout Concept for Future Pixel Detectors based on Current Mode Signal Processing

Marcel TrimplBonn University

Vertex 2002 Kailua-Kona, November 2002

Bonn University / MPI Munich (HLL)L.Andricek, G.Lutz, P.Lechner, R.H.Richter, L.Strüder P.Fischer, I.Peric, M.Trimpl, J.Ulrici, N.Wermes



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DEPFET-Performance

2 4 6

0

1000

2000

3000

4000

5000

6000

Escape - Peak

K

K

# Z

ähle

r

Energie [keV]

single-pixel spectra:

ENC = 4.8 +/- 0.1 e-

55Fe-spectra @ 300K

• low power consumption (< 1W for whole TESLA vtx-sensor) (row-wise operation)

spatial resolution: ~ 9µm(with 50x50 µm2 pixel)

~ 3.2 mm

Matrix-picture with 55Fe:

[J.Ulrici, Bonn]

fast and low noise readout needed !!

• excellent energy resolution (low noise needed for thinned detector)

• thinnable (50µm proposed for TESLA)

• small pixelsize possible (25x25µm2)

• good spatial resolution (charge sharing)



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Proposed concept for TESLA

• thin detector-area down to 50µm• frame for mechanical stability carries readout- and steering-chips

first thinned samples:

[L.Andricek, MPI Munich]

steering chips

readout chips

520 x 4000 pixelDEPFET-Matrix

(25 x 25 µm pixel)

readout chips

matrix is read out row-wise



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n x mpixel

IDRAIN

DEPFET- matrix

VGATE, OFF

off

off

on

off

VGATE, ON

gate

drain VCLEAR, OFF

off

off

reset

off

VCLEAR, ON

reset

output

0 suppression

VCLEAR-Control

Reset row i

Gate row i

Current of pixel i,j

sample Iped+Isig sample Iped

• continue with next row ...• Collected charge in internal gate ~ (Difference of both currents)• Reset one row and measure pedestal currents• Select one row via external Gates and measure Pedestal + Signal current

Matrixoperation

Readout-scheme:Matrix-scheme:

Advantages of readout:

• pedestals need not to be stored• 1/f noise is reduced (CDS)

But:

complete reset (clear) needed



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Readout Architecture V1.0

Regulated Cascode keeps drain potential constant

(Signal+Pedestal) are stored in fast current memory cell (20ns, inverting)

Pedestal-Current after Reset is subtracted automatically

Hit-Identification with fast current comparator

Hit-Information + analog value are stored in mixed-signal FIFO

FIFO is emptied row by row Fast digital scanner identifies hits in a row (up to 2 hits per cycle) and multiplexes the corresponding analog currents to the outputs (no external trigger)

DEPFET provides current + fast readout needed current readout



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... and ... it is easy to add new features

• on chip (algorithmic) ADC at the end (only needs to digitize hits – saves power)

• larger buffer to store several rows at front end possible (if reset is not fast enough)

• analog signals: row-wise common-mode-rejection reduces common noise pickup remarkably

• digital signals: neighbour logic (mark neighbour pixel of hit for readout even if they are below threshold)

• more hit scanners can easily be added (if occupancy is higher than at TESLA)



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IBias

input output

sample

I DEPFET

CGate

Basic Storage Principle

Storage phase: input- and sample-switch are closed. (storage capacitance is „parasitic“ gate-capacitance of nmos)

I = IDEPFET + IBias

IDEPFET

Transfer phase: Output switch is closed. IDEPFET is flowing out. (done immediately after sampling)

Sampling phase: sample and input switch are opened ( voltage at capacitance „unchanged“ → current unchanged )

I = IDEPFET + IBias



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Prototype-Chip

• TSMC 0.25 µm process with radiation-tolerant layout• contains all basic parts of proposed design (various memory-cells, fast hit-finder, current comparator structures)

1.5m

m

4 mm



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high speed and high accurancy ...

IBias

input output

sample

I DEPFETI DEPFET

CGate

1. Bandwidth (speed – intrinsically high because of small capacitance)

2. Output conductance (negligible with cascode techniques)

3. charge injection (offset and signal depending)

4. Noise (sampling noise dominant)

5. Radiation tolerant design limits transistor parameters (geometry has to be angular)



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reduce charge injection

If two successive sample-stages are used (like in readout-architecture) the offset is eliminated as well:

Iout1 = - Iin + I Iout2 = - Iin + I = Iin + I – I = Iin

IBias

input

coarse

I DEPFET

CGate

IBias

output

fine

CGate

coarse stage fine stage

shift

Use of 2 stages: coarse and fine sampling

Error of coarse stage is resampled by fine stage Signal depending charge injection reduced



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Testsetup for Memory Cells

Memory Cellsteering

U2I

I2UU2I

ADC

inpu

t

I2U



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measured linearity

0 10 20 30 40 50 60 700,2

0,4

0,6

0,8

1,0

1,2

1,4

1,6

1,8

2,0

< 10nA

Deviation of memory cell

Iout

- Ii

n [µ

A]

Iinput [µA]

0 10 20 30 40 50 60 70

0

10

20

30

40

50

60

70

IBias

= 70µA

Measured linearity of memory cell

Iou

tpu

t [µ

A]

Iinput [µA]

0.1% accurancy reached @ 25MHz !!

dynamic range depends on bias-current of memory cell (range vs. power) (10µA for DEPFET-readout needed)

2 memory cells with regulated cascode input

(like in readout architecture)



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Bandwith (speed)

Simple model:

m

Gate

g

C

m

Gate

gCs

sH

1

1)(

High speed : small Cgate, large gm

1/gm

Iin Iin

CGate

CGate

gm

Realistic model:

sm

BUSG

m

BUSG

gg

CCs

g

CCs

sH21

1)(

careful design neededto avoid oscillation ...

1/gS

CG

CBUS

Still : small Cgate

large gm

for high speed



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CRSwitch

Vinput

Noise from current sampling

voltage sample-stage:

(independent of RSwitch)

C

KTvc 2

RKTvth 42

current sample-stage:

BUSG

GBUS

Gc CC

CC

C

KTv

322

222Cm vgi

Low noise:Large C, small gm

(contrary to high speed requirement)

1/gS

CG

CBUS

Iinput



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sampling noise

~ 30 electrons sampling noise ( assuming gQ = 1nA /e- ) more than other noise contributions (e.g. pmos current source)

400 600 800 1000 1200 1400 1600 1800 20000

100

200

300

400

500

600

700

800

900

1000

@ room temperature

CBUS

= 1 pF

Cg [fF]

gm [

µS

] 0

15,00

30,00

45,00

60,00

75,00

90,00

105,0

120,0Noise [ nA]

present design(23 ... 29nA)

gm and CGate are not independent:

• linked via geometry• speed requirement gives ratio (line indicating 50MHz)



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measured noise

2 4 6 8 10 1250

100

150

200

250

300

350

m = 27,74 +/- 0,44 e- / sample

c = 15,82 +/- 3,6 e-

@ room-temperature 25 MHz - Samplefrequency

nois

e [e

lect

rons

]

sqrt (samples)

• low noise expected (< 30 electrons)• difficult to measure with simple testsetup

→ cascade of sampling stages on chip

1 2 (n-1) n

I in I out

corresponds to calculation !!



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Summary of performance

analog part (memory cell):speed: 25MHzaccurancy : 0.1 %noise : < 30 electrons

very encouraging result

digital part: fast hit-finder and current-comparator-block work with desired speed (50MHz)



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next step ....

• full 128 channel readout-chip working with DEPFET-Matrix at 50MHz

• Internal ADC optional

16-MBitSRAM

external ADC

128 x 128 pixelDEPFET-Matrix

DAQ PC

128-channelSteering Chip

(for Gate + Clear)

128-channel Readout Chip

Timing at TESLA :• 1ms Trainbunch• 200ms Trainpause

Hits are stored in RAMduring train and read out in pause

TESLA prototype-system:



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Summary / Outlook

• Concept with fast readout for HEP-Experiment (e.g. TESLA) with current mode signal processing presented

• Architecture of current mode operating prototype-chip has a lot of advantages (low power, high linearity, high speed, wide dynamic range) and is versatile

• First prototype shows encouraging results with nearly TESLA requirements: Speed has to be improved by better choice of cell parameters : 50MHz possible

• TESLA Prototype-System working with DEPFET-Matrix expected within 2003

kailua-kona, 05.11.2002 marcel trimpl, bonn university readout concept for future pixel detectors...

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