kvm project book - university of southern california

“KVM EAS”

KVM Project Book

Version 0.7

“KVM EAS”

2 INTEL CONFIDENTIAL

Table of Content 1. INTRODUCTION:............................................................................................................................................................... 4

2. HIGH LEVEL LAYOUT: ................................................................................................................................................... 4

3. DATA FLOW ....................................................................................................................................................................... 6 3.1 INITIALIZATION ............................................................................................................................................................. 6 3.2 ROUTINE FLOW.............................................................................................................................................................. 6

4. DRIVER................................................................................................................................................................................ 7

5. DVI RECEIVER – SII1171 ................................................................................................................................................. 8 5.1 PIN FUNCTION .............................................................................................................................................................. 10

5.1.1 Output pins description ........................................................................................................................................ 11 5.1.2 Configuration pins description............................................................................................................................. 12 5.1.3 Output timing........................................................................................................................................................ 13

6. SAMPLE&COMPARE UNIT .......................................................................................................................................... 14 6.1 SAMPLE&COMPARE UNIT BLOCK DIAGRAM .............................................................................................................. 14 6.2 DATA SAMPLING MECHANISM ..................................................................................................................................... 15 6.3 FUNCTIONALITY & OPERATIVE METHODOLOGY...................................................................................................... 16

7. COMPRESSION UNIT ..................................................................................................................................................... 17 7.1 COMPRESSION UNIT BLOCK DIAGRAM ...................................................................................................................... 17 7.2 FUNCTIONALITY & OPERATIVE METHODOLOGY...................................................................................................... 18

8. DMA UNIT ......................................................................................................................................................................... 19 8.1 COMPRESSION UNIT BLOCK DIAGRAM ...................................................................................................................... 19 8.2 FUNCTIONALITY & OPERATIVE METHODOLOGY...................................................................................................... 20

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Table of Figures Figure 1 – High level layout........................................................................................................................................... 5 Figure 2 – SiI1171 DVI receiver block diagrams........................................................................................................... 9 Figure 3 – SiI1171 DVI receiver pin diagram .............................................................................................................. 10 Figure 4 – block diagram for ODCK_INV pin .............................................................................................................. 12 Figure 5 – Output Data, DE and control signals Setup/Hold times to ODCK.............................................................. 13 Figure 6 – Output signals disabled timing from PD Active.......................................................................................... 13 Figure 7 – 2-pixels/Clock staggered output diagram .................................................................................................. 13 Figure 8 – Sampling Unit high level block diagram..................................................................................................... 14 Figure 9 – screen image on card and data transfer method....................................................................................... 15 Figure 14 – Compression Unit high level block diagram............................................................................................. 18 Figure 14 – Compression Unit high level block diagram............................................................................................. 19

“KVM EAS”


1. INTRODUCTION: This is an EAS for LAD’s KVM Project. The idea is to build a technology that once proves its capability, can be productized to support different running projects. This document will be a live one. As such, additions and changes will be done.

2. HIGH LEVEL LAYOUT: The following figure is a very high level layout of the block as we see it today. The units that are marked need to be implemented.

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Figure 1 – High level layout

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3. DATA FLOW The data flow can be shown by the figure above and is controlled and regulated by control signals from the KVM Driver (that should be replaced by an ARC in future LAD projects) that receives its orders and sends the final data to the client using the LAN Driver that controls the TCP stack and packets transfer.

The flow that will be described in this section is general flow between the units, the part of each unit and the detailed data flow will be given in more details later on in the document.

3.1 Initialization a. The LAN Driver opens a dedicated socket and waits for a connection request to arrive.

b. Once the client connects to the our socket he may ask for a screen update when ever he wishes.

c. Initially the Driver sends a control signal to the sample&compare Unit to measure the �� by counting the number of clocks between HSYNC assertions (for width) and the number of HSYNC between VSYNC assertions (for Height).

d. Then the Driver request for a screen sample (from the sample unit) for the first screen shot and gives the sample unit a pointer to the correct location on the RAM.

e. Once the sample is done the HW signals the FW that the first screen is ready to be sent to the client (either compressed or not)

3.2 Routine flow a. Update request - The Driver receives an update request packet from the client and sends a sample

control signal to the sample&compare unit.

b. The sample&compare unit samples the screen, compare each data sampled to the previous data from the same location on the screen and saves the data on the RAM if there was a change in this data or in any data in the suitable tile. The unit uses a pointer for the correct location and then sends a “finished” signal to the driver. (the information between the FW and the HW is done by a system of regfiles and interrupts) If an error was found - the Compare unit sends a “change-found” signal to the driver and also a bus where each bit represents a tile that need to be resent to the client.

c. The Driver then send a control signal to the Compress unit to compress this tile and informs the FW the tile is ready to be sent.

d. After all packets were sent the entire KVM block returns to idle and waits for the next “update request”.

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4. DRIVER

The Driver is a firmware that controls the entire process by sending control signals in appropriate timings to the Units using regfiles and interrupt signals.

It is also responsible for getting the instructions from the client and alerting the LAN Driver when the compressed data is ready for transmitting.

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5. DVI RECEIVER – SII1171

The SiI1171 is a single-link TMDS receiver which supports DVI bandwidth from 25 to 225 MHz – that is from VGA (640x480) to QXGA (2048x1536). The SiI1171 outputs the data in either 24-bit or 48-bit (1 or 2 pixels/clock modes). We will use only 16-bits per pixel from the 24. (32-bits on the 2-pixel/clock)

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Figure 2 – SiI1171 DVI receiver block diagrams

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5.1 Pin function The siI1171 is 100-pin package.

All the data and figures below are from another DVI receiver with the same features and interface, when we will have the correct datasheet we will replace everything.

Figure 3 – SiI1171 DVI receiver pin diagram

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5.1.1 Output pins description Pin Name Type Description QE[23:0] Out Output even data corresponds to 24-bit pixel data for 1-pixel/clock mode and the first 24-

bit pixel data for 2-pixel/clock mode. Output data is synchronized with output data clock (ODCK). (see table below)

QO[23:0] Out Output odd data corresponds to the second 24-bit pixel data for 2-pixel/clock mode. During 1-pixel/clock mode, these outputs are driven low. Output data is synchronized with output data clock (ODCK). (see table below)

ODCK Out Output Data Clock. This output can be inverted using OCK_INV pin. DE Out Output Data Enable. This signal qualifies the active data area. A HIGH level signifies

active display time and a LOW level signifies blanking time. This output signal is synchronized with the output data.

HSYNC VSYNC CTL1 CTL2 CTL3

Out Out Out Out Out

Horizontal Sync input control signal. Vertical Sync input control signal. General output control signal 1. General output control signal 2. General output control signal 3.

Color 2-Pixel/Clock Blue[7:0] - 0 QE[7:0] Green[7:0] - 0 QE[15:8] Red[7:0] - 0 QE[23:16] Blue[7:0] - 1 QO[7:0] Green[7:0] - 1 QO[15:8] Red[7:0] - 1 QO[23:16]

Color 1-Pixel/Clock Blue[7:0] QE[7:0] Green[7:0] QE[15:8] Red[7:0] QE[23:16]

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5.1.2 Configuration pins description Pin Name Type Description OCK_INV In ODCK Polarity. A LOW level selects normal ODCK output. A HIGH level selects

inverted ODCK output. All other output signals are not affected by this pin. They will maintain the same timing no matter the setting of OCK_INV pin (Figure 4). NOTE OCK_INV cannot be set HIGH (inverted) when operating in Dual Link Mode

PIXS/M_S In Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using QE[23:0]. A HIGH level indicates two pixels (up to 48-bits) per clock mode using QE[23:0] for first pixel and QO[23:0] for second pixel. Master/Slave. When S_D pin is HIGH (Dual Link), this pin becomes M_S. When HIGH, it is in Master mode. When LOW, it is in Slave mode.

STAG_OUT/SYNC

In Staggered Output. A HIGH level selects normal simultaneous outputs on all odd and even data lines. A LOW level selects staggered output drive. This function is only available in 2-pixels per clock mode. Synchronization. When S_D pin is HIGH (Dual Link), this pin is used to synchronize the Slave receiver to the Master receiver.

ST In Output Drive. A HIGH level selects HIGH output drive strength. A LOW level selects LOW output drive strength.

S_D In Single/Dual Link Mode. When HIGH, it is in Dual Link Mode. When LOW it is in Single Link Mode. The Slave receiver is always in Dual Link mode. The Master receiver switches between Single and Dual Link mode depending upon the SCDT output of the Slave receiver that is connected to the S_D input of the Master receiver.

Figure 4 – block diagram for ODCK_INV pin

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5.1.3 Output timing

Figure 5 – Output Data, DE and control signals Setup/Hold times to ODCK

The signals are relative to ODCK falling edge when ODCK_INV=0, or ODCK rising edge when ODCK_INV=1.

Figure 6 – Output signals disabled timing from PD Active

Figure 7 – 2-pixels/Clock staggered output diagram

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6. SAMPLE&COMPARE UNIT

The sample&compare unit is in charge of measuring of the screen, sampling of the data itself, comparing the new data to the old data in the same location on the screen and positioning the sampled the data in the correct location on the RAM.

6.1 Sample&compare Unit block diagram In the figure below is the sample&compare unit block diagram.

Figure 8 – Sampling Unit high level block diagram

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6.2 Data sampling mechanism The following drawing describes how video raster is placed in card’s memory and how pixel’s data looks (example of 24-bits pixel representation), how a Tile appears in the memory and how a Tile’s data appear in the last compared Tile Array memory.

Figure 9 – screen image on card and data transfer method

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6.3 Functionality & Operative Methodology The sample&compare unit receives control signals from the Driver through registers writing using the auxiliary regfile and acts accordingly.

When measure_scr is asserted the sample&compare unit counts the number of ODCK toggles between two HSYNC assertions (for the Width measure) and counts the number of HSYNC assertions between two VSYNC assertions (for the Height measure). It then sends the information back to the driver and saves it for its own use.

When sample is asserted the sampling process begins: (based on figure 7)

a. Waiting for DE to rise.

b. Since QO is changing on posedge ODCK we will sample it on negedge ODCK. (need to check time constraints)

c. Since QE is changing on posedge ODCK +Tst we will sample it on negedge ODCK as well (Tst is guarantied by design to be 0.25 ODCK cycle time) (need to check time constraints)

d. Removing LSB in each color to reduce resolution from 24-bits per pixel to 16-bits per pixel.

e. Checking if the data in the pixel was changed since sampled or if the tile should be replaced, if not then do nothing if yes then:

a. Writing the data to memory

i. Using several counters to decide where to write the information.

f. When the entire screen is done the sample&compare unit asserts the smpcmp_done signal to the driver through interrupt signal or through the registers.

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7. COMPRESSION UNIT

The Compression Unit role is to take the tile that was identified by the sample&compare Unit as changed, and compress it using a known algorithm that can be opened on the other end.

We will implement the ZRLE compression algorithm.

7.1 Compression Unit Block Diagram

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Figure 10 – Compression Unit high level block diagram

7.2 Functionality & Operative Methodology The Compression Unit receives control signals from the Driver and acts accordingly.

When compress is asserted start the compressing process:

a. Read from the memory the relevant tile lines, according to the location received from the Driver, into a ‘compress register’.

b. Compress the register using a compression algorithm.

c. Send the done signal to the driver so the tile could be sent.

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8. DMA UNIT

The DMA Unit role is to take the tile that need to be transmitted to the client after (or without) compression from the SRAM and move it into a separate designated memory from which the LAN Driver will take the data into the packets that are sent to the client.

8.1 Compression Unit Block Diagram

Figure 11 – Compression Unit high level block diagram

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8.2 Functionality & Operative Methodology The DMA Unit receives control signals from the Driver and acts accordingly.

When move_tile is asserted start the DMA process:

a. Read from the memory the relevant tile lines and move them one by one to the designated memory through FIFO (synchronization) according to the location received from the Driver.

kvm project book - university of southern california

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