lar40 cold electronics wbs 130.05.03.04 craig thorn 1far site review, december 6-9, 2011

Far Site Review, December 6-9, 2011

1

LAr40 Cold Electronics WBS 130.05.03.04

Craig Thorn


Outline Scope & Requirements Electronics specifications Technical overview

Data rates Zero-suppression Electronics overview Front-end (analog) ASIC Digital (ADC, buffer, mux) ASIC Cryogenic operation of CMOS ASICs Electronics details and specifications

Schedule Summary

Craig Thorn


Scope & Requirements Scope: Can use WBS definitions (

http://lbne2-docdb.fnal.gov:8080/cgi-bin/ShowDocument?docid=2163) for scope. Note that WBS#’s are out of date, also be sure text reflects current reference design choice.

Requirements: Get from Anne Heavey, DOORS output. (http://lbne2-docdb.fnal.gov:8080/cgi-bin/ShowDocument?docid=3747) Anne should have the outputs by Dec. 1st.)

Craig Thorn

WBS Name WBS Dictionary

130.05.03.04 Cold Electronics Detector electronics inside the cryostat including the front end preamp, shaper, ADC, MUX and optical driver. Most of these components are ASIC's. Also includes in-vessel circuit boards and interconnects. Includes design, procurement, fabrication and cold testing of all components and shipment to the underground site.

130.05.03.04.01 Cold electronics conceptual design Cold electronics conceptual design.

130.05.03.04.02 Cold electronics preliminary design Cold electronics preliminary design.

130.05.03.04.03 Cold electronics preliminary design review

Cold electronics preliminary design review.

130.05.03.04.04 Cold electronics reliability test Test of long term reliability by operating a large number of front end boards near LAr temperature. This could be done in an existing LAr cryostat such as the membrane prototype if it is available, or it could be done in an existing or new LN cryostat.

130.05.03.04.05 Cold electronics final design Cold electronics final design.

130.05.03.04.06 Cold electronics final design review Cold electronics final design review.

130.05.03.04.07 Cold electronics construction Includes procurement, fabrication, assembly, cold testing and shipping to the APA assembly site.

http://lbne2-docdb.fnal.gov:8080/cgi-bin/ShowDocument?docid=2163





Electronics ParametersParameter Value Units Req ID Notes

ENC @ 90K 563 electrons LAr-TPC-11 BNL ASIC measured

Electron lifetime assumption 1.4 ms LAr-TPC-11 Set to achieve minimum S/N = 9

ADC sampling rate 2 MHz LAr-TPC-11 Same as ICARUS, MicroBooNE and ArgoNeuT

Num MIP dynamic range 15 LAr-TPC-12 15 MIP ionization is a reasonable maximum value

ADC resolution - min 10 bits LAr-TPC-11 Minimum value required

Readout redundancy 4

Front end amplifier shaping time 1.0 micro-sec Choices are 0.5, 1 and 2 micro-sec

Analog front end power 10 mW/chan Design goal

Digital front end power 5 mW/chan includes line driver power

Craig Thorn

White (Series) Noise: SNR• Noise is 600 e rms• MIP is 10000 e (1 attn length , 5 mm spacing)• Threshold at 0.3 MIP: noise is 5 sigma• (for these conditions 0.1% of points on a MIP track are

lost)• Probability of > 5 sigma is 2.8 x 10-7

• Read nearest neighbor wires + 2 leading & trailing samples

• Rate per APA is 3 x 5 x 2560 x 150 kHz x 12 x 2.8 x 10-7

= 0.02 Mb/s

Total Event Rate For NoiseWith Zero-suppression

Far Site Review, December 6-9, 2011 Craig Thorn

• Ar39: Mean beta energy of 220 keV, endpoint 565 keV, 1.4 kBq/m3

• Kr85: Mean beta energy of 251 keV, endpoint 687 keV, 0.16 – 0.48 kBq/m3

• K40, Co60, Th232, U238: in construction materials, gammas only, atten length <15 cm•Ar spallation by cosmics: no cross section data, but not significant in WARP data

Practical Maximum Data Rate of LAr20Radioactive contaminants

The energy spectrum observed with the 2.3 liter WARP detector (Data) can be reproduced by 1. an internal component

dominated by Ar39 and Kr85b emission inside the liquid argon.

2. an external component dominated by interactions of g-rays coming from U238, Th232, Co60 and K40 radioactivity of the materials surrounding the liquid argon

P. Benetti et al., NIM A 574 (2007) 83Craig Thorn

Practical Maximum Data Rate of LAr20Radioactive contaminants

•Ar39

• Decay rate is 122 kHz/APA • Mean ionization is ~0.3 MIP• Threshold @ 0.5 MIP, detected rate is 34 kHz• Mean range of betas is 0.28 mm• Read 3 wires and 10 samples• Mean rate is 3 x 8 x 34,000 x 12 = 9.8 Mb/s

•Kr85

• Decay rate is ~28 kHz/APA • Mean ionization is ~0.4 MIP• Threshold @ 0.5 MIP, detected rate is 8 kHz• Mean range of betas is 0.39 mm• Read 3 wires and 5 samples• Mean rate is 3 x 8 x 8,000 x 12 = 2.3 Mb/s

•Co60

• Only near SS APA frames since attenuation length is ~10 cm

• add ~0.2Mb/s (range of Compton electron is 1.3 cm)

Calculation of 220 keV electrons in LAr from CASINO

www.gel.usherbrooke.ca/casino/index.html


http://www.gel.usherbrooke.ca/casino/index.html



8

• Zero-suppression at FE reduces total volume of data to transmit• Buffering on FE ASIC allows data to be transmitted at lower rate than

sampling rate• Readout rate must be high enough to avoid event “collisions” in one

FE buffer• With optimal zero-suppression, radioactivity, cosmics, and series FE

noise give rates of

• 9.8 Mb/s for Ar39 betas• 2.3 Mb/s for Kr85 betas• 0.6 Mb/s for Co60, Th & U gammas• 0.02 Mb/s for FE series noise*• 0.8 Mb/s for cosmic muons (1 Gb/s near surface**)• Total is ~14 Mb/s (2 Gb) per APA at 800 (0) feet (cf. limit of

300Mb/s for copper, 3Gb/s for optical transmission per line)

*For an enc of 600 RMS e-, a threshold at 3000 e- and 1 us shaping (zero-crossing rate of 150kHz). For a 1/e drift time of 2.4 ms, a drift of 3.7 m and a wire pitch of 5 mm, this threshold is 0.3 MIP.

**Cosmic muon rate is 12 kHz (26 muon per drift, mean track length 2 m)

Data Rates - Summary

Far Site Review, December 6-9, 2011Craig Thorn

• Trigger derived from the logic OR of all collecting wires on an APA

• All channels on an APA continuously writing to the buffer until no signal from any collecting wire

• Baseline samples are compacted into smaller words (4bits)

Not efficient: little data reduction

Data volume is not sensitive to “noise” (thermal, induced, radioactivity, cosmics, …)


Zero Suppression – APA Trigger

Craig Thorn

• Trigger derived from the logic OR of all channels in a chip

• All channels on a chip continuously writing to the buffer until no signal from any channel of a chip

• Baseline samples are compacted into smaller words (4bits)

Data volume is sensitive to “noise”

Zero Suppression – Chip Trigger

Craig Thorn

• Trigger is derived from a single channel

• Write enable is applied to the i, i+1, and i-1 wires to cover any shared, below threshold signals

• Read ahead and after the write enable gate to capture the below threshold leading/trailing edges of a waveform

Minimum data volume

Data volume is less sensitive to “noise”

Zero Suppression – Channel Trigger

Craig Thorn


FEE Design Guidelines & Constraints

some factors relevant to the design of final in-LAr readout architecture

reliabilitylifetime

dead timenumber of feed-throughs

power dissipation

flexibility

back-end redundancy

low multiplexing, low clock frequency

↕ (conflict)

high multiplexing, high clock frequency

token-passing(design option)

programmability (design, operation)

compressionsparsificationneighboringsmart thresholdderandomization (deep memory)

zero suppression

Craig Thorn

LAr TPC - Cold CMOS ElectronicsBlock Diagram – Lar40 Reference Design


LAr TPC - Cold CMOS ElectronicsBlock Diagram – LAr40 Alternate Design


~ 7 mm

~ 5

mm

Layoutchg amp filter ac reg ADC cmp

pulser BGR, bias, temp. sens. reg control logic

mu

xbuffer

• 16 channels• charge amplifier (adj. gain)• high-order filter (adj. time constant)• ac/dc, adjustable baseline• test capacitor, channel mask• ADC (12-bit, 2 MS/s)• compression, discrimination• multiplexing and digital buffering• LV or CM digital interface• pulse generator, analog monitor• temperature sensor•LAr environment (> 20 years at 88K)• estimated total size ~ 6 x 8 mm²• estimated power ~ 10 mW/channel

dual-stage charge amplifier filter ac/dc

common register

channel register

gain &mode bypass

peaking time & mode

16 channels

mode

wire

mode & couplingtest

ADC12-bit, 2 MS/s

BGR, common bias, temp. sensor control logicpulse generator

compression muxdigital

interface(LV or CM)

CK

CS

DI

DO

AO

buffer

Block Diagram

LAr TPC Front-End ASIC

16

• 16 channels• charge amplifier, high-order filter• adjustable gain: 4.7, 7.8, 14, 25 mV/fC (charge 55, 100, 180, 300 fC)• adjustable filter time constant (peaking time 0.5, 1, 2, 3 µs)• selectable collection/non-collection mode (baseline 200, 800 mV)• selectable dc/ac coupling (100µs)

dual-stage charge amplifier filter ac/dc

common register

channel register

gain &mode bypass

peaking time & mode

16 channels

mode

wire

mode & couplingtest

BGR, common bias, temp. sensordigital

interface

Block Diagram

analogoutputs

• rail-to-rail analog signal processing• band-gap referenced biasing• temperature sensor (~ 3mV/°C)• 136 registers with digital interface• 5.5 mW/channel (input MOSFET 3.9 mW)• single MOSFET test structures• ~ 15,000 MOSFETs•designed for room (300K) and cryogenic (77K) operation• technology CMOS 0.18 µm, 1.8 V

6.0 mm

5.7

mm

Analog ASIC


170 10 20 30 40 50

Am

plit

ud

e [a

.u.]

Time [µs]

Peak time [µs] 0.5 1.0 2.0 3.0

collecting mode

non-collecting mode

gain [mV/fC]25147.84.7Adjustable gain, peaking time and baseline

maximum charge 55, 100, 180, 300 fC

-4 -2 0 2 4 6 8

0.0

0.2

0.4

0.6

0.8

Am

plitu

de [V

]

Time [µs]

T=300K T=77K

Gain 25 mV/fCPeaking time 1µs

Pole-zero cancellation at 77K to be addressed in next revision

K77atV164.1

K300atV185.1VBGR

Bandgap Reference

variation ≈ 1.8 %

K77atVm3.259

K300atmV0.867VTMP

Temperature Sensor

~ 2.86 mV / °K

Signal Measurements



Noise ~ 250e- w/o Cdet w. tp=1μs @RT

Crosstalk < 0.7%

Noise < 1000e- w. Cdet=150pF & tp=1μs @ RT

Analog ASIC - Signal MeasurementsAnalog ASIC - Signal Measurements

Warm tests for MicroBooNE


FEE ASIC EvaluationNoise, Gain, and Shaping Time

Measurements affected by:

• input line parasitic resistance• ~ 150 e- at 77 K (~ 590 e- at 300K )• addressed in next revision

Layout Detail

Input MOSFETL = 270 nmW = 10 mm(50µm x 200)gm,77K ≈ 90 mS (11 Ω)gm,300K ≈ 45 mS (22 Ω)

Input LineL ≈ 1 mmW = 3.5 µm(M3 + M4)R77K ≈ 3 ΩR300K ≈ 12 Ω

• CIN dielectric noise (not present in wire)

• ~ 60 e- at 77 K

MICAfore60

NPOfore200

tgkTC2dENC IN

0 1 2 3500

600

700

800

900

EN

C (el

ectron

s r.m

.s.)

Peaking Time (µs)

Dielectric: MICA NP0

T=77KC

IN=220pF

0 1 2 30

200

400

600

800

1000

1200

1400

1600

1800

simulated input MOSFET

target at 90K

measured

simulated whole front-end

EN

C (e

lect

rons

r.m

.s.)

Peaking Time (µs)

T=300K T=77K

CDET

=220pF

Analog ASIC - Noise Measurements

ASIC version #3 designed and fabricated, currently being tested

Dynamic Range > 3,000

Qmax=300fC

Issues Addressed in Version 2

• Analog front-end• input MOSFET optimization → MOSFET width doubled• noise from resistance of input lines → line width doubled

• Start-up failures in some bias circuit → start-up circuits added (due to new BGR biasing circuits)

Craig Thorn

Residual Issues in Version 2

• CMP damage in AC/DC circuit (found in a few samples)

• Some packaging issues

• DC PSR can be improved

from charge

amplifierto ac/dc

and buffer

Vdd

VBGR VBGRVBGR

no baseline stabilization possible, due to constraint on measurement time

DC

AC

to bufferfrom filter100pF

1MΩ

Vdd

VB

GR/R

Craig Thorn

to buffer(metal 6)

from filter

switchmetal 5 interconnect line

CapacitorResistor

1,100µm

280µm


1MΩ

Vdd

VB

GR/R


1MΩ

Vdd

VB

GR/R

Only possible explanation: high series resistance (up to open)

DC

ACm

etal

6

met

al

5

risk of CMP damage

CMP Damage

23

Damage due to discharge from Chemical-Mechanical Polishing (CMP) during fabrication

DC

goodchannel

goodchannel

damagedchannel

damagedchannel

CMP Damage


LArASIC3 sent for fabrication on July 25th

Received and under evaluation

LArASIC2 LArASIC3

size 6010 x 5707 µm²

FE ASIC Version 3

bias circuit for high PSR

Craig Thorn

n p

e ne

logic

n p e ne

share

cu

rre

nt s

ou

rce

shaped pulse (current signal I)

I v1

sa1

i1

sb1 dsc1

v2

sa2

i2

sb2 dsc2

vm-1

sam-1

im-1

sbm-1 dscm-1

d1 d2 dm-2 dm-1

V

Current mode ADC•dual stage6-MSBs in 150ns, 6-LSBs in 250ns• single trigger conversion per stage•12-bit resolution•2 MS/s conversion rate • power dissipation 3.6 mW at 2 MS/s•power-down option for low rate applications

• wake up in few tens of ns• layout size: 0.23 mm x 1.25 mm

ADC cell

Clockless low power ADC stageDemonstrated in ASIC for SNS, see De Geronimo, et al., IEEE Trans NSS, 54 (2007) 541

ADC - Architecture


• operation verified at room and cryogenic temperatures•differential non-linearity limited by timing design error in control circuit•integral non-linearity limited by mismatch (linear → common centroid)

ADC - Preliminary Results

ASIC revision designed and fabricated; under evaluation

ADC output - 500mV dc

σ=1.1LSB

77 KADC output - 1.4 V sine

300 K16-channelADC+buffer

6m

m

4.3 mm

Craig Thorn


Schedule (install by others) Schedule provided by KenFY10 FY11 FY12 FY13 FY14 FY15 FY16 FY17 FY18 FY19 FY20 FY21 FY22

CD-0: 1/2010

Beneficial Occupancy: 10/2018

CD-1: 6/2012 CD-2:

9/2013 CD-3: 12/2014

Designs

Construction

Checkout

Craig Thorn


Milestones

Craig Thorn


Summary

Craig Thorn

• CMOS performs better at cryogenic temperatures• Defined and predictable design for cryogenic T is possible• Low-noise at cryogenic T demonstrated

• ENC < 1,000 e- at 200pF ~5mW/ch.• characterization and modeling of CMOS 180nm

• Long lifetime at cryogenic T possible with guidelines• Critical building blocks - front-end & ADC - developed

• Future work• Improve cryogenic static models• Optimize ADC• Merge, add zero-suppression & buffering, and finalize


Backup Information

• two independent 8-channel sections (a and b)• ADC max 2MS/s, 12-bit, calibrated for zero at baseline• mem can store one full-depth event (3K) per channel

8xanalo

g

8xADC

thr/trig

cmp

mem3K

mux

8:1

8xanalo

g

8xADC

thr/trig

cmp

mem3K

mux

8:1

bias, pulser, logic, registers

ae re ck flg wi

wo

db

tba,tbb

da

taa,tabsection a

section b

ASIC Architecture

• da, db = data out• taa, tab, tba, tbb = triggers in/out (edge channels)

• ae = acquisition enable (sync/reset acquisition at positive edge)• re = readout enable• ck = clock 32 or 64 MHz

• rck (readout clock) 32 or 64 MHz• tck (timestamp & ADC clock) 2MHz• cck (test pulse clock) 8 kHz• wck (write clock) 8 MHz

• flg = flag (full indicator, stops acquisition, restarts at 3/4 buffer empty)• wi, wo = configuration in/out

• event stored in mem if: (i) above threshold or (ii) external trigger from neighbor (or FPGA)

mode ae re ck t d flag

write 0 0 wck - - -

acquire 1 0 tck, cck trig i/o - full

acquire &readout

1 1 tck, cck, rck trg i/o data out full

readout 0 1 rck - data out -

0 (16)

amplitude datatime1 (10)

addr (12)

1 (16)

max block size 4096-bit

• variable block length, max 4096 bitstartend

id (4)

Data Format

• block-start: 16 ones

• block-end: 16 zeros

• address 12-bit• 5-bit hard-assigned + 7-bit soft-assigned• all 0 and all 1 not allowed

• timestamp 20-bit (2 x 10-bit)• associated to threshold crossing• Gray-code, 500 ns (2 MHz), ~500 ms full scale• all 0 and all 1 not allowed

• block id (same timestamp) 4-bit• resets at each new timestamp• all 0 and all 1 not allowed

• amplitude data 14-bit or n-bit• compress if below compression-threshold (programmable)• first bit: compression id (0 = compressed data, 1 = full data)• second bit: polarity (0 = negative, 1 = positive)• next bits: amplitude (12 for uncompressed, n-2 for compressed)• max amplitude length 4096 - 68 = 4028 bit (~288x14-bit)• can be broken to next block as needed• all 0 and all 1 not allowed

time2 (10)

Craig Thorn


Cost Estimate

$341,270

$14,838,800

$10,408,939

$4,292,751

$1,290,914

$1,126,040 $148,168

$3,842,435 13005.04.01 LAr TPC Conceptual Design (incl TPC/APA/CPA/Infras-truct) ($341,270)13005.04.02 LAr TPC Anode plane assemblies (APA) ($14,838,800)13005.04.03 LAr TPC Cold Electronics ($10,408,939)13005.04.04 LAr TPC Cathode plane assemblies (CPA) ($4,292,751)13005.04.05 LAr TPC Field Cage ($1,290,914)13005.04.06 LAr TPC Infrastructure ($1,126,040)13005.04.07 LAr TPC Checkout ($148,168)13005.04.08 LAr TPC Management ($3,842,435)

Cost Drivers:APA's - 41% of totalCold Electronics - 28% of totalCPA's - 12% of total

Craig Thorn


Labor vs M&S

$22,761,024

$13,843,953

Total Labor - 62%Total M&S - 38%

Craig Thorn

lar40 cold electronics wbs 130.05.03.04 craig thorn 1far site review, december 6-9, 2011

Documents

suppression electronics

lar40 cold electronics

cold testing

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cgi binshowdocument

scope requirements scope

end boards

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