ldo linear regulator - micropower, delay, adjustable reset ... · delay time h l trr cd = 100 nf...
TRANSCRIPT
© Semiconductor Components Industries, LLC, 2015
September, 2019 − Rev. 31 Publication Order Number:
NCV4269C/D
NCV4269C
LDO Linear Regulator -Micropower, DELAY,Adjustable RESET,Sense Output
5.0 V, 150 mA
The NCV4269C is a 5.0 V precision micropower voltage regulatorwith an output current capability of 150 mA.
The output voltage is accurate within ±2.0% with a maximumdropout voltage of 0.5 V at 100 mA. Low quiescent current is a featuredrawing only 125 �A with a 1.0 mA load. This part is ideal for any andall battery operated microprocessor equipment.
Microprocessor control logic includes an active reset output ROwith delay and a SI/SO monitor which can be used to provide an earlywarning signal to the microprocessor of a potential impending resetsignal. The use of the SI/SO monitor allows the microprocessor tofinish any signal processing before the reset shuts the microprocessordown.
The active Reset circuit operates correctly at an output voltage aslow as 1.0 V. The Reset function is activated during the power upsequence or during normal operation if the output voltage dropsoutside the regulation limits.
The reset threshold voltage can be decreased by the connection of anexternal resistor divider to the RADJ lead. The regulator is protectedagainst reverse battery, short circuit, and thermal overload conditions.The device can withstand load dump transients making it suitable foruse in automotive environments. The device has also been optimizedfor EMC conditions.
Features• 5.0 V ± 2.0% Output
• Low 125 �A Quiescent Current
• Active Reset Output Low Down to VQ = 1.0 V
• Adjustable Reset Threshold
• 150 mA Output Current Capability
• Fault Protection♦ +60 V Peak Transient Voltage♦ −40 V Reverse Voltage♦ Short Circuit♦ Thermal Overload
• Early Warning through SI/SO Leads
• Internally Fused Leads in SO−14 Package
• Integrated Pullup Resistor at Logic Outputs (To Use ExternalResistors, Select the NCV4279C)
• Very Low Dropout Voltage
• Electrical Parameters Guaranteed Over Entire Temperature Range
• AEC−Q100 Grade 1 Qualified and PPAP Capable
• These are Pb−Free Devices
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MARKINGDIAGRAM
ORDERING INFORMATIONSee detailed ordering and shipping information in the packagedimensions section on page 13 of this data sheet.
SO−14D2 SUFFIXCASE 751A
114
1
NCV4269C5GAWLYWW
14
1
8
4269C5ALYW
�1
8
SO−8EXPOSED PAD
PD SUFFIXCASE 751AC
SO−8D1 SUFFIXCASE 7511
84269C5ALYW
�1
8
A = Assembly LocationWL, L = Wafer LotY = YearWW, W = Work WeekG, � = Pb Free
V4269C50
ALYW�
�
TSSOP−14 EPPA SUFFIX
CASE 948AW
(Note: Microdot may be in either location)
1
14
NCV4269C
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I
RO
Q
SO
RADJ
D
Figure 1. Block Diagram
GNDSI
Referenceor
RRO
RSO
ErrorAmplifier
Referenceand Trim
Current andSaturation
Control
+
−
PIN CONNECTIONS
SOROQGNDGNDGNDGNDGND
1 14
GNDGNDIDSIRADJ
SO−14
GNDD
1 8
RORADJ
SOSI
QI
SO−8 TSSOP−14 EP
SORONCNCNCNCQGND
1 14
NCDINCSIRADJ
PACKAGE PIN DESCRIPTION
Package Pin NumberPin
Symbol FunctionSO−8 SO−8 EP SO−14 TSSOP14
3 3 1 1 RADJ Reset Threshold Adjust; if not used to connect to GND.
4 4 2 3 D Reset Delay; To Set Time Delay, Connect to GND with Capacitor
5 5 3, 4, 5, 6,10, 11, 12
4 GND Ground
− − − 2, 5, 6, 9,10, 12
NC No connection to these pins from the IC.
6 6 7 7 RO Reset Output; The Open−Collector Output has a 20 k� Pullup Resistor toQ. Leave Open if Not Used.
7 7 8 8 SO Sense Output; This Open−Collector Output is Internally Pulled Up by 20 k�pullup resistor to Q. If not used, keep open.
8 8 9 11 Q 5 V Output; Connect to GND with a 10 �F Capacitor, ESR < 2.5 �.
1 1 13 13 I Input; Connect to GND Directly at the IC with Ceramic Capacitor.
2 2 14 14 SI Sense Input; If not used, Connect to Q.
− EPAD − EPAD EPAD Connect to ground potential or leave unconnected
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MAXIMUM RATINGS (TJ = −40°C to 150°C)
Parameter Symbol Min Max Unit
Input to Regulator VIII
−40Internally Limited
45Internally Limited
V
Input Transient to Regulator (Note 3) VI − 60 V
Sense Input VSIISI
−40−1
451
VmA
Reset Threshold Adjust VRADJIRADJ
−0.3−10
710
VmA
Reset Delay VDID
−0.3Internally Limited
7Internally Limited
V
Ground Iq 50 − mA
Reset Output VROIRO
−0.3Internally Limited
7Internally Limited
V
Sense Output VSOISO
−0.3Internally Limited
7Internally Limited
V
Regulated Output VQIQ
−0.5−10
7−
VmA
Junction TemperatureStorage Temperature
TJTSTG
−−50
150150
°C°C
Input Voltage Operating RangeJunction Temperature Operating Range
VITJ
−−40
45150
V°C
LEAD TEMPERATURE SOLDERING AND MSL
Parameter Symbol Value
MSL, 8−Lead, 14−Lead, LS Temperature 265°C Peak (Note 4) MSL 1
MSL, 8−Lead EP, LS Temperature 260°C MSL 2
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM) ≤ 4.0 kV per AEC−Q100−002.Machine Model (MM) ≤ 200 V per AEC−Q100−003.
2. Latchup tested per AEC−Q100−004.3. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class A according to ISO16750−1.4. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.
THERMAL CHARACTERISTICS
Characteristic Test Conditions (Typical Values) Unit
SO−8 Package (Note 5)
Junction−to−Pin 6 (� − JL6, �L6) 58.3 °C/W
Junction−to−Ambient Thermal Resistance (R�JA, �JA) 151.1 °C/W
SO−8 EP Package (Note 5)
Junction−to−Pin 8 (� − JL8, �L8) 47 °C/W
Junction−to−Ambient Thermal Resistance (R�JA, �JA) 131.6 °C/W
Junction−to−Pad (� − JPad) 16.3 °C/W
SO−14 Package (Note 5)
Junction−to−Pin 4 (� − JL4, �L4) 19.5 °C/W
Junction−to−Ambient Thermal Resistance (R�JA, �JA) 100.9 °C/W
TSSOP−14 EP Package (Note 5)
Junction−to−Pin 3 (� − JL3, �L3) 19.3 °C/W
NCV4269C
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THERMAL CHARACTERISTICS
Characteristic UnitTest Conditions (Typical Values)
TSSOP−14 EP Package (Note 5)
Junction−to−Ambient Thermal Resistance (R�JA, �JA) 77.3 °C/W
Junction−to−Pad (� − JPad) 12.6 °C/W
5. 2 oz copper, 150 mm2 copper area, 1.5 mm thick FR4
NCV4269C
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ELECTRICAL CHARACTERISTICS (TJ = −40°C ≤ TJ ≤ 150°C, VI = 13.5 V unless otherwise specified)
Characteristic Symbol Test Conditions Min Typ Max Unit
REGULATOR
Output Voltage VQ 1 mA � IQ � 100 mA 6 V � VI � 16 V 4.90 5.00 5.10 V
Current Limit IQ − 150 430 500 mA
Current Consumption; Iq = II – IQ Iq IQ = 1 mA, RO, SO High − 125 250 �A
Current Consumption; Iq = II – IQ Iq IQ = 10 mA, RO, SO High − 230 450 �A
Current Consumption; Iq = II – IQ Iq IQ = 50 mA, RO, SO High − 0.9 3.0 mA
Dropout Voltage Vdr VI = 5 V, IQ = 100 mA − 0.23 0.5 V
Load Regulation �VQ IQ = 5 mA to 100 mA − 1 20 mV
Line Regulation �VQ VI = 6 V to 26 V IQ = 1 mA − 1 30 mV
RESET GENERATOR
Reset Switching Threshold VRT − 4.50 4.65 4.80 V
Reset Adjust Switching Threshold VRADJ,TH VQ > 3.5 V 1.26 1.35 1.44 V
Reset Pullup Resistance RRO,INT − 10 20 40 k�
Reset Output Saturation Voltage VRO,SAT VQ < VRT, RRO, INT − 0.03 0.4 V
Upper Delay Switching Threshold VUD − 1.4 1.8 2.2 V
Lower Delay Switching Threshold VLD − 0.3 0.45 0.60 V
Saturation Voltage on Delay Capacitor VD,SAT VQ < VRT − − 0.1 V
Charge Current ID,C VD = 1 V 3.0 6.5 9.5 �A
Delay Time L � H td CD = 100 nF 17 28 73 ms
Delay Time H � L tRR CD = 100 nF − 1.5 − �s
INPUT VOLTAGE SENSE
Sense Threshold High VSI,High − 1.24 1.31 1.38 V
Sense Threshold Low VSI,Low − 1.16 1.20 1.28 V
Sense Output Saturation Voltage VSO,Low VSI < 1.20 V; VQ > 3 V; RSO,INT − 0.03 0.4 V
Sense Resistor Pullup RSO,INT − 10 20 40 k�
Sense Input Current ISI − −1.0 0.1 1.0 �A
THERMAL SHUTDOWN
Thermal Shutdown Temperature (Note 6) TSD Iout = 1 mA 150 − 200 °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.6. Values based on design and/or characterization.
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Figure 2. Measuring Circuit
RADJ1
VI
II
IRADJ
IQ
VSI
CD100 nF
VD
ID Iq VRO VSOVRADJ
RADJ2
CI470 nF
1000 �F
ISI
VQ
CQ22 �F
I
SI
D GND RO SO
RADJ
Q
VI
VQ
VD
VLD
VRT
VRO,SAT
VRO
t
t
< tRR
dVdt
�IDCD
VUD
t
Power−on−Reset ThermalShutdown
Voltage Dipat Input
Undervoltage SecondarySpike
Overloadat Output
ttRRtd
Figure 3. Reset Timing Diagram
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Sense Input Voltage
VSI,High
VSI,Low
High
Low
t
t
Sense Output Voltage
Figure 4. Sense Timing Diagram
TYPICAL PERFORMANCE CHARACTERISTICS
3.2
−40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (°C)
VD
, DE
LAY
TH
RE
SH
OLD
(V)
0
2
4
6
8
10
12
14
16
−40 0 40 80 120 160
Figure 5. Charge Current ID,C vs. Temperature TJ Figure 6. Switching Voltage VUD and VLD vs.Temperature TJ
TJ, JUNCTION TEMPERATURE (°C)
I D,C
, CH
AR
GE
CU
RR
EN
T (�A
) VI = 13.5 VVD = 1.0 V
VI = 13.5 V
VUD
VLD
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
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TYPICAL PERFORMANCE CHARACTERISTICS
14
0
I q, C
UR
RE
NT
CO
NS
UM
PT
ION
(m
A)
VI, INPUT VOLTAGE (V)
10 20 30 40 45
RL = 33 �
RL = 50 �
RL = 100 �
RL = 200 �
1.7
−40
VR
AD
J,T
H, R
ES
ET
AD
JUS
T
SW
ITC
HIN
G T
HR
ES
HO
LD (
V) 1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
TJ, JUNCTION TEMPERATURE (°C)
0 40 80 120 160
IQ, OUTPUT CURRENT (mA)
Vdr
, DR
OP
OU
T V
OLT
AG
E (
mV
)
TJ = 125°C
TJ = 25°C
TJ = −40°C
Figure 7. Drop Voltage Vdr vs. Output Current IQ
0
100
200
300
400
500
0 30 60 90 120 150 180
Figure 8. Reset Adjust Switching Threshold,VRADJ,TH vs. Temperature TJ
Figure 9. Current Consumption Iq vs. InputVoltage VI
Figure 10. Output Voltage VQ vs. Input Voltage VI
12
0
VQ
, OU
TP
UT
VO
LTA
GE
(V
)
VI, INPUT VOLTAGE (V)
2 4 6 8 10
10
8
6
4
2
0
RL = 50 �
12
10
8
6
4
2
0
Figure 11. Sense Threshold VSI vs. Temperature TJ Figure 12. Output Voltage VQ vs. Temperature TJ
1.6
−40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (°C)
VS
I, S
EN
SE
INP
UT
TH
RE
SH
OLD
(V
)
VI = 13.5 V
1.5
1.4
1.3
1.2
1.1
1.0
VSI, High
VSI, Low
5.2
−40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (°C)
VQ
, OU
TP
UT
VO
LTA
GE
(V
) VI = 13.5 VIQ = 1 mA
5.1
5.0
4.9
4.8
4.7
4.6
5 15 25 35
TJ = 25°C TJ = 25°C
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TYPICAL PERFORMANCE CHARACTERISTICS
250
6
I q, C
UR
RE
NT
CO
NS
UM
PT
ION
(�A
)
VI, INPUT VOLTAGE (V)
IQ = 100 �A
8 10 12 14 16 18 20 22 24 26
1.6
0 10 20 40 50
IQ, OUTPUT CURRENT (mA)
I q, C
UR
RE
NT
CO
NS
UM
PT
ION
(m
A)
30
3.0
6
I q, C
UR
RE
NT
CO
NS
UM
PT
ION
(m
A)
VI, INPUT VOLTAGE (V)
IQ = 100 mA
2.5
2.0
1.5
1.0
0.5
0
IQ = 50 mA
IQ = 10 mA
VI, INPUT VOLTAGE (V)
I Q, O
UT
PU
T C
UR
RE
NT
(m
A) TJ = 125°C
TJ = 25°C
350
0 10 20 30 40 50
300
250
200
150
100
50
0
4.0
0 20 40 80 120
IQ, OUTPUT CURRENT (mA)
I q, C
UR
RE
NT
CO
NS
UM
PT
ION
(m
A)
VI = 13.5 VTJ = 25°C
3.5
2.5
2.0
1.5
0.5
0
Figure 13. Output Current IQ vs. Input Voltage VI Figure 14. Current Consumption Iq vs. OutputCurrent IQ
Figure 15. Current Consumption Iq vs.Output Current IQ
Figure 16. Quiescent Current Iq vs. Input Voltage VI
60
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
VI = 13.5 VTJ = 25°C
100
8 10 12 14 16 18 20 22 24 26
Figure 17. Quiescent Current Iq vs. Input Voltage VI Figure 18. Output Stability, Capacitance ESRvs. Output Load Current
200
150
100
50
TJ = 25°C100
0
ES
R (�
)
IQ, OUTPUT CURRENT (mA)
Unstable Region
10
1
0.0125 50 75 100 125 150
Stable Region for2.2 �F to 10 �F
TJ = 125°C
400
5 15 25 35 45
3.0
1.0
0.1
VQ = 0 V
NCV4269C
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TYPICAL THERMAL CHARACTERISTICS
SO−8 Std Package NCV4269C, 1.0 ozSO−8 Std Package NCV4269C, 2.0 ozTSSOP−14 EP Package NCV4269C, 1.0 ozTSSOP−14 EP Package NCV4269C, 2.0 ozSO−8 EP Package NCV4269C, 1.0 ozSO−8 EP Package NCV4269C, 2.0 ozSO−14 w/6 Thermal Leads NCV4269C, 1.0 ozSO−14 w/6 Thermal Leads NCV4269C, 2.0 oz
Figure 19. Junction−to−Ambient Thermal Resistance (�JA) vs. Heat Spreader Area
Figure 20. R(t) vs. Pulse Time
�JA
(°C
/W)
COPPER HEAT−SPREADER AREA (mm2)
700600400300200100 5000
200
180
160
140
120
100
80
60
40
20
0
Single Pulse (SO−8 Std Package) PCB = 150 mm2, 2.0 ozSingle Pulse (TSSOP−14 EP Package) PCB = 150 mm2, 2.0 ozSingle Pulse (SO−8 EP Package) PCB = 150 mm2, 2.0 ozSingle Pulse (SO−14 w/6 TL Package) PCB = 150 mm2, 2.0 oz
R(t
) (°
C/W
)
PULSE TIME (s)
0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
1000
100
10
1
0.1
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APPLICATION DESCRIPTION
OUTPUT REGULATORThe output is controlled by a precision trimmed reference.
The PNP output has base drive quiescent current control forregulation while the input voltage is low, preventing oversaturation. Current limit and voltage monitors complementthe regulator design to give safe operating signals to theprocessor and control circuits.
RESET OUTPUT (RO)A reset signal, Reset Output, RO, (low voltage) is
generated as the IC powers up. After the output voltage VQincreases above the reset threshold voltage VRT, the delaytimer D is started. When the voltage on the delay timer VDpasses VUD, the reset signal RO goes high. A discharge ofthe delay timer VD is started when VQ drops and stays belowthe reset threshold voltage VRT. When the voltage of thedelay timer VD drops below the lower threshold voltage VLDthe reset output voltage VRO is brought low to reset theprocessor.
The reset output RO is an open collector NPN transistorwith an internal 20 k� pullup resistor connected to theoutput Q, controlled by a low voltage detection circuit. Thecircuit is functionally independent of the rest of the IC,thereby guaranteeing that RO is valid for VQ as low as 1.0 V.
RESET ADJUST (RADJ)The reset threshold VRT can be decreased from a typical
value of 4.65 V to as low as 3.5 V by using an externalvoltage divider connected from the Q lead to the pin RADJ,as shown in Figure 21. The resistor divider keeps the voltageabove the VRADJ,TH (typical 1.35 V) for the desired inputvoltages, and overrides the internal threshold detector.Adjust the voltage divider according to the followingrelationship:
VRT � VRADJ, TH � (RADJ1 � RADJ2)�RADJ2 (eq. 1)
If the reset adjust option is not needed, the RADJ pinshould be connected to GND causing the reset threshold togo to its default value (typically 4.65 V).
RESET DELAY (D)The reset delay circuit provides a delay (programmable by
capacitor CD) on the reset output lead RO. The delay lead Dprovides charge current ID,C (typically 6.5 �A) to theexternal delay capacitor CD during the following times:
1. During Powerup (once the regulation threshold hasbeen exceeded).
2. After a reset event has occurred and the device isback in regulation. The delay capacitor is set todischarge when the regulation (VRT, resetthreshold voltage) has been violated. When thedelay capacitor discharges to VLD, the reset signalRO pulls low.
SETTING THE DELAY TIMEThe delay time is set by the delay capacitor CD and the
charge current ID. The time is measured by the delaycapacitor voltage charging from the low level of VDSAT tothe higher level VUD. The time delay follows the equation:
td � [CD (VUD � VD, SAT)]�ID, C (eq. 2)
Example:Using CD = 100 nF.Use the typical value for VD,SAT = 0.1 V.Use the typical value for VUD = 1.8 V.Use the typical value for Delay Charge Current ID = 6.5 �A.
td � [100 nF(1.8 � 0.1 V)]�6.5 �A � 26.2 ms (eq. 3)
Q
GND
I
RADJ
NCV4269C
CQ**10 �F(2.2 �F)
RO
0.1 �F
Mic
rop
roce
sso
r
D
CD
VBAT VDD
SO
Figure 21. Application Diagram
SI
I/OI/O
RADJ2
RADJ1
RSI1
RSI2
CI*
*CI required if regulator is located far from the power supply filter.** CQ − minimum cap required for stability is 2.2 �F while higher over/under−shoots may be
expected. Cap must operate at minimum temperature expected.
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SENSE INPUT (SI) / SENSE OUTPUT (SO) VOLTAGEMONITOR
An on−chip comparator is available to provide earlywarning to the microprocessor of a possible reset signal(Figure 4). The output is from an open collector driver withan internal 20 k� pull up resistor to output Q. The reset signaltypically turns the microprocessor off instantaneously. Thiscan cause unpredictable results with the microprocessor. Thesignal received from the SO pin will allow the microprocessortime to complete its present task before shutting down. Thisfunction is performed by a comparator referenced to the bandgap voltage. The actual trip point can be programmedexternally using a resistor divider to the input monitor SI(Figure 21). The values for RSI1 and RSI2 are selected for atypical threshold of 1.20 V on the SI Pin.
SIGNAL OUTPUTFigure 22 shows the SO Monitor timing waveforms as a
result of the circuit depicted in Figure 21. As the outputvoltage (VQ) falls, the monitor threshold (VSI,Low), iscrossed. This causes the voltage on the SO output to go lowsending a warning signal to the microprocessor that a resetsignal may occur in a short period of time. TWARNING is thetime the microprocessor has to complete the function it iscurrently working on and get ready for the resetshutdown signal. When the voltage on the SO goes low andthe RO stays high the current consumption is typically530 �A at 1 mA load current.
Figure 22. SO Warning Waveform Time Diagram
VQ
SI
VRO
VSI,Low
TWARNING
SO
STABILITY CONSIDERATIONSThe input capacitor CI in Figure 21 is necessary for
compensating input line reactance. Possible oscillations causedby input inductance and input capacitance can be damped byusing a resistor of approximately 1.0 � in series with CI.
The output or compensation capacitor helps determinethree main characteristics of a linear regulator: startup delay,load transient response and loop stability.
The capacitor value and type should be based on cost,availability, size and temperature constraints. Thealuminum electrolytic capacitor is the least expensivesolution, but, if the circuit operates at low temperatures
(−25°C to −40°C), both the value and ESR of the capacitorwill vary considerably. The capacitor manufacturer’s datasheet usually provides this information.
The 10 �F output capacitor CQ shown in Figure 21 shouldwork for most applications; however, it is not necessarily theoptimized solution. Stability is guaranteed at CQ is min2.2��F and max ESR is 2.5 �. There is no min ESR limitwhich was proved with MURATA’s ceramic capsGRM31MR71A225KA01 (2.2 �F, 10 V, X7R, 1206) andGRM31CR71A106KA01 (10 �F, 10 V, X7R, 1206) directlysoldered between output and ground pins.
CALCULATING POWER DISSIPATION IN A SINGLEOUTPUT LINEAR REGULATOR
The maximum power dissipation for a single outputregulator (Figure 21) is:
PD(max) � [VI(max) � VQ(min)] IQ(max) � VI(max) Iq (eq. 4)
where:VI(max) is the maximum input voltage,VQ(min) is the minimum output voltage,IQ(max) is the maximum output current for the application,and Iq is the quiescent current the regulator consumes atIQ(max).
Once the value of PD(max) is known, the maximumpermissible value of R�JA can be calculated:
(eq. 5)R�JA = (150°C – TA) / PD
The value of R�JA can then be compared with those in thepackage section of the data sheet. Those packages withR�JA’s less than the calculated value in equation 2 will keepthe die temperature below 150°C. In some cases, none of thepackages will be sufficient to dissipate the heat generated bythe IC, and an external heatsink will be required. The currentflow and voltages are shown in the Measurement CircuitDiagram.
HEATSINKSA heatsink effectively increases the surface area of the
package to improve the flow of heat away from the IC andinto the surrounding air.
Each material in the heat flow path between the IC and theoutside environment will have a thermal resistance. Likeseries electrical resistances, these resistances are summed todetermine the value of R�JA:
R�JA � R�JC � R�CS � R�SA (eq. 6)
where:R�JC = the junction−to−case thermal resistance,R�CS = the case−to−heat sink thermal resistance, andR�SA = the heat sink−to−ambient thermal resistance.
R�JC appears in the package section of the data sheet. LikeR�JA, it too is a function of package type. R�CS and R�SA arefunctions of the package type, heatsink and the interfacebetween them. These values appear in data sheets ofheatsink manufacturers. Thermal, mounting, andheatsinking considerations are discussed in theON Semiconductor application note AN1040/D, availableon the ON Semiconductor website.
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ORDERING INFORMATION
Device Output Voltage Package Shipping†
NCV4269CD150R2G
5.0 V
SO−8(Pb−Free) 2500 / Tape & Reel
NCV4269CPD50R2G SO−8 EP(Pb−Free) 2500 / Tape & Reel
NCV4269CD250R2G SO−14(Pb−Free) 2500 / Tape & Reel
NCV4269CPA50R2G TSSOP−14(Pb−Free) 2500 / Tape & Reel
†For information on tape and reel specifications,including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.
SOIC−8 NBCASE 751−07
ISSUE AKDATE 16 FEB 2011
SEATINGPLANE
14
58
N
J
X 45�
K
NOTES:1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.
A
B S
DH
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIMA
MIN MAX MIN MAXINCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244
−X−
−Y−
G
MYM0.25 (0.010)
−Z−
YM0.25 (0.010) Z S X S
M� � � �
XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package
GENERICMARKING DIAGRAM*
1
8
XXXXXALYWX
1
8
IC Discrete
XXXXXXAYWW
�1
8
1.520.060
7.00.275
0.60.024
1.2700.050
4.00.155
� mminches
�SCALE 6:1
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXXAYWW
1
8
(Pb−Free)
XXXXXALYWX
�1
8
IC(Pb−Free)
XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42564BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−8 NBCASE 751−07
ISSUE AKDATE 16 FEB 2011
STYLE 4:PIN 1. ANODE
2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE
STYLE 1:PIN 1. EMITTER
2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER
STYLE 2:PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1
STYLE 3:PIN 1. DRAIN, DIE #1
2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1
STYLE 6:PIN 1. SOURCE
2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE
STYLE 5:PIN 1. DRAIN
2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE
STYLE 7:PIN 1. INPUT
2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd
STYLE 8:PIN 1. COLLECTOR, DIE #1
2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1
STYLE 9:PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON
STYLE 10:PIN 1. GROUND
2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND
STYLE 11:PIN 1. SOURCE 1
2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1
STYLE 12:PIN 1. SOURCE
2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN
STYLE 14:PIN 1. N−SOURCE
2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN
STYLE 13:PIN 1. N.C.
2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN
STYLE 15:PIN 1. ANODE 1
2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON
STYLE 16:PIN 1. EMITTER, DIE #1
2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1
STYLE 17:PIN 1. VCC
2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC
STYLE 18:PIN 1. ANODE
2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE
STYLE 19:PIN 1. SOURCE 1
2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1
STYLE 20:PIN 1. SOURCE (N)
2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN
STYLE 21:PIN 1. CATHODE 1
2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6
STYLE 22:PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND
STYLE 23:PIN 1. LINE 1 IN
2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT
STYLE 24:PIN 1. BASE
2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE
STYLE 25:PIN 1. VIN
2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT
STYLE 26:PIN 1. GND
2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC
STYLE 27:PIN 1. ILIMIT
2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN
STYLE 28:PIN 1. SW_TO_GND
2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN
STYLE 29:PIN 1. BASE, DIE #1
2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1
STYLE 30:PIN 1. DRAIN 1
2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42564BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−14 NBCASE 751A−03
ISSUE LDATE 03 FEB 2016
SCALE 1:11
14
GENERICMARKING DIAGRAM*
XXXXXXXXXGAWLYWW
1
14
XXXXX = Specific Device CodeA = Assembly LocationWL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
STYLES ON PAGE 2
NOTES:1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSIONSHALL BE 0.13 TOTAL IN EXCESS OF ATMAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDEMOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PERSIDE.
H
14 8
71
M0.25 B M
C
hX 45
SEATINGPLANE
A1
A
M
�
SAM0.25 B SC
b13X
BA
E
D
e
DETAIL A
L
A3
DETAIL A
DIM MIN MAX MIN MAXINCHESMILLIMETERS
D 8.55 8.75 0.337 0.344E 3.80 4.00 0.150 0.157
A 1.35 1.75 0.054 0.068
b 0.35 0.49 0.014 0.019
L 0.40 1.25 0.016 0.049
e 1.27 BSC 0.050 BSC
A3 0.19 0.25 0.008 0.010A1 0.10 0.25 0.004 0.010
M 0 7 0 7
H 5.80 6.20 0.228 0.244h 0.25 0.50 0.010 0.019
� � � �
6.50
14X0.58
14X
1.18
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
0.10
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42565BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2SOIC−14 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−14CASE 751A−03
ISSUE LDATE 03 FEB 2016
STYLE 7:PIN 1. ANODE/CATHODE
2. COMMON ANODE3. COMMON CATHODE4. ANODE/CATHODE5. ANODE/CATHODE6. ANODE/CATHODE7. ANODE/CATHODE8. ANODE/CATHODE9. ANODE/CATHODE
10. ANODE/CATHODE11. COMMON CATHODE12. COMMON ANODE13. ANODE/CATHODE14. ANODE/CATHODE
STYLE 5:PIN 1. COMMON CATHODE
2. ANODE/CATHODE3. ANODE/CATHODE4. ANODE/CATHODE5. ANODE/CATHODE6. NO CONNECTION7. COMMON ANODE8. COMMON CATHODE9. ANODE/CATHODE
10. ANODE/CATHODE11. ANODE/CATHODE12. ANODE/CATHODE13. NO CONNECTION14. COMMON ANODE
STYLE 6:PIN 1. CATHODE
2. CATHODE3. CATHODE4. CATHODE5. CATHODE6. CATHODE7. CATHODE8. ANODE9. ANODE
10. ANODE11. ANODE12. ANODE13. ANODE14. ANODE
STYLE 1:PIN 1. COMMON CATHODE
2. ANODE/CATHODE3. ANODE/CATHODE4. NO CONNECTION5. ANODE/CATHODE6. NO CONNECTION7. ANODE/CATHODE8. ANODE/CATHODE9. ANODE/CATHODE
10. NO CONNECTION11. ANODE/CATHODE12. ANODE/CATHODE13. NO CONNECTION14. COMMON ANODE
STYLE 3:PIN 1. NO CONNECTION
2. ANODE3. ANODE4. NO CONNECTION5. ANODE6. NO CONNECTION7. ANODE8. ANODE9. ANODE
10. NO CONNECTION11. ANODE12. ANODE13. NO CONNECTION14. COMMON CATHODE
STYLE 4:PIN 1. NO CONNECTION
2. CATHODE3. CATHODE4. NO CONNECTION5. CATHODE6. NO CONNECTION7. CATHODE8. CATHODE9. CATHODE
10. NO CONNECTION11. CATHODE12. CATHODE13. NO CONNECTION14. COMMON ANODE
STYLE 8:PIN 1. COMMON CATHODE
2. ANODE/CATHODE3. ANODE/CATHODE4. NO CONNECTION5. ANODE/CATHODE6. ANODE/CATHODE7. COMMON ANODE8. COMMON ANODE9. ANODE/CATHODE
10. ANODE/CATHODE11. NO CONNECTION12. ANODE/CATHODE13. ANODE/CATHODE14. COMMON CATHODE
STYLE 2:CANCELLED
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42565BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2SOIC−14 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−8 EPCASE 751AC
ISSUE DDATE 02 APR 2019
GENERICMARKING DIAGRAM*
XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package1
8
SCALE 1:11
8
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”, mayor may not be present and may be in eitherlocation. Some products may not follow theGeneric Marking.
XXXXXAYWW�
�
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON14029DDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1SOIC−8 EP
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
TSSOP−14 EPCASE 948AW
ISSUE CDATE 09 OCT 2012SCALE 1:1
NOTES:1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.2. CONTROLLING DIMENSION: MILLIMETERS.3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL BE0.07 mm MAX. AT MAXIMUM MATERIAL CONDITION.DAMBAR CANNOT BE LOCATED ON THE LOWER RADI-US OF THE FOOT. MINIMUM SPACE BETWEEN PRO-TRUSION AND ADJACENT LEAD IS 0.07.
4. DIMENSION D DOES NOT INCLUDE MOLD FLASH,PROTRUSIONS OR GATE BURRS. MOLD FLASH,PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED0.15 mm PER SIDE. DIMENSION D IS DETERMINED ATDATUM H.
5. DIMENSION E1 DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSIONS. INTERLEAD FLASH ORPROTRUSIONS SHALL NOT EXCEED 0.25 mm PERSIDE. DIMENSION E1 IS DETERMINED AT DATUM H.
6. DATUMS A AND B ARE DETERMINED AT DATUM H.7. A1 IS DEFINED AS THE VERTICAL DISTANCE FROM
THE SEATING PLANE TO THE LOWEST POINT ON THEPACKAGE BODY.
8. SECTION B−B TO BE DETERMINED AT 0.10 TO 0.25 mmFROM THE LEAD TIP.
XXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package
DIM MIN MAXMILLIMETERS
A −−−− 1.20
b 0.19 0.30
c 0.09 0.20
A1 0.05 0.15
L 0.45 0.75
M 0 8 ��
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
GENERICMARKING DIAGRAM*
6.70
14X0.42
14X1.15
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
E 6.40 BSC
L2 0.25 BSC
RECOMMENDED
(Note: Microdot may be in either location)
1
14
3.06
3.40XXXXXXXXALYW�
�
1
14
ÇÇÇÇÇÇ
SECTION B−Bc
c1
b
b1
ÉÉÉÉ
A2 0.80 1.05
b1 0.19 0.25
c1 0.09 0.16D 4.90 5.10D2 3.09 3.62
E1 4.30 4.50E2 2.69 3.22
0.65 BSCe
SEATINGPLANE
A2
M
L
DETAIL A
END VIEW
PIN 1 71
14 8
TOP VIEW
E1
SIDE VIEW
REFERENCE 0.20 C
NOTE 5
2X 14 TIPS
B
0.10 C
C
A
14X c
DETAIL A
A1
B
B
E2
BOTTOM VIEW
D2
b0.10 C
NOTE 3
B A14X
0.05 C
DNOTE 4
GAUGEPLANECNOTE 7
HL2
E
eB A
NOTE 6
NOTE 8
ANOTE 6
SS
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON66474EDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1TSSOP−14 EP, 5.0X4.4
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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