ldo voltage regulator - adjustable output, load dump ...300 0 25 50 75 100 125 io = 50 ma-v io,...
TRANSCRIPT
© Semiconductor Components Industries, LLC, 2013
April, 2021 − Rev. 271 Publication Order Number:
LM2931/D
LDO Voltage Regulator -Adjustable Output, LoadDump Protection60 V, 100 mA
LM2931, NCV2931 SeriesThe LM2931 series consists of positive fixed and adjustable output
voltage regulators that are specifically designed to maintain properregulation with an extremely low input−to−output voltage differential.These devices are capable of supplying output currents in excess of100 mA and feature a low bias current of 0.4 mA at 10 mA output.
Designed primarily to survive in the harsh automotive environment,these devices will protect all external load circuitry from input faultconditions caused by reverse battery connection, two battery jumpstarts, and excessive line transients during load dump. This series alsoincludes internal current limiting, thermal shutdown, and additionally,is able to withstand temporary power−up with mirror−image insertion.
Due to the low dropout voltage and bias current specifications, theLM2931 series is ideally suited for battery powered industrial andconsumer equipment where an extension of useful battery life isdesirable. The ‘C’ suffix adjustable output regulators feature an outputinhibit pin which is extremely useful in microprocessor−based systems.
Features• Input−to−Output Voltage Differential of < 0.6 V @ 100 mA
• Output Current in Excess of 100 mA
• Low Bias Current
• 60 V Load Dump Protection
• −50 V Reverse Transient Protection
• Internal Current Limiting with Thermal Shutdown
• Temporary Mirror−Image Protection
• Ideally Suited for Battery Powered Equipment
• Economical 5−Lead TO−220 Package with Two Optional Leadforms
• Available in Surface Mount SOP−8, D2PAK and DPAK Packages
• High Accuracy (±2.5%) Reference (LM2931AC) Available
• NCV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC−Q100Qualified and PPAP Capable
• Pb−Free Packages are Available
Applications• Battery Powered Consumer Products
• Hand−held Instruments
• Camcorders and Cameras
TO−92Z SUFFIX
CASE 29−10
FIXED OUTPUT VOLTAGE
Pin 1. Output2. Ground3. Input
TO−220T SUFFIX
CASE 221AB
Pin 1. Input2. Ground3. Output
DPAKDT SUFFIXCASE 369C
D2PAKD2T SUFFIXCASE 936
TO−220TH SUFFIXCASE 314A
ADJUSTABLE OUTPUT VOLTAGE
Pin 1. Adjust2. Output
Inhibit3. Ground4. Input5. Output
TO−220TV SUFFIXCASE 314B
TO−220T SUFFIX
CASE 314D
D2PAKD2T SUFFIXCASE 936A
See detailed ordering and shipping information in the packagedimensions section on page 12 of this data sheet.
ORDERING INFORMATION
See general marking and heatsink information in the devicemarking section on page 15 of this data sheet.
DEVICE MARKING INFORMATION
123
13
13
15
1
1
5
1
5
1
5
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13
SOT−223ST SUFFIXCASE 318H
123
1
LM2931, NCV2931 Series
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FIXED
(Top View)
N.C.
GND
Input
N.C.
GND
Output18
5 4
ADJUSTABLE
(Top View)
OutputInhibit
GND
Input
Adjust
GND
Output18
5 4
SOIC−8D SUFFIXCASE 751
1
8
Representative Schematic Diagram
*Deleted on Adjustable Regulators
Input
Output
30 k *
Adjust
92.8 k *
Ground
350
500
6.0 k
6.0
30 k
OutputInhibit
EPIBias
50 k
5.8 V
10 k11.5 k
3.0 k
3.94 k
30 k 30 k
180 k 184 k
6.8 V
35 k
48 k
This device contains 26 active transistors.
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MAXIMUM RATINGS
Rating Symbol Value Unit
Input Voltage Continuous VI 40 Vdc
Transient Input Voltage (� ≤ 100 ms) VI(�) 60 Vpk
Transient Reverse Polarity Input Voltage −VI(�) −50− Vpk
1.0% Duty Cycle, � ≤ 100 ms
Electrostatic Discharge Sensitivity (ESD) Human Body Model (HBM) Class 2, JESD22 A114−C Machine Model (MM) Class A, JESD22 A115−A Charged Device Model (CDM), JESD22 C101−C
−−−
20002002000
VVV
Power DissipationCase 29 (TO−92 Type)
TA = 25°C PD Internally Limited WThermal Resistance, Junction−to−Ambient R�JA 178 °C/WThermal Resistance, Junction−to−Case R�JC 83 °C/W
Case 221A, 314A, 314B and 314D (TO−220 Type)TA = 25°C PD Internally Limited WThermal Resistance, Junction−to−Ambient R�JA 65 °C/WThermal Resistance, Junction−to−Case R�JC 5.0 °C/W
Case 318H (SOT−223)TA = 25°C PD Internally Limited WThermal Resistance, Junction−to−Ambient R�JA 242 °C/WThermal Resistance, Junction−to−Case R�JC 21 °C/W
Case 369A (DPAK) (Note 1)TA = 25°C PD Internally Limited WThermal Resistance, Junction−to−Ambient R�JA 92 °C/WThermal Resistance, Junction−to−Case R�JC 6.0 °C/W
Case 751 (SOP−8) (Note 2)TA = 25°C PD Internally Limited WThermal Resistance, Junction−to−Ambient R�JA 160 °C/WThermal Resistance, Junction−to−Case R�JC 25 °C/W
Case 936 and 936A (D2PAK) (Note 3)TA = 25°C PD Internally Limited WThermal Resistance, Junction−to−Ambient R�JA 70 °C/WThermal Resistance, Junction−to−Case R�JC 5.0 °C/W
Operating Ambient Temperature Range TA −40 to +125 °C
Operating Die Junction Temperature TJ +150 °C
Storage Temperature Range Tstg −65 to +150 °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. DPAK Junction−to−Ambient Thermal Resistance is for vertical mounting. Refer to Figure 25 for board mounted Thermal Resistance.2. SOP−8 Junction−to−Ambient Thermal Resistance is for minimum recommended pad size. Refer to Figure 24 for Thermal Resistance
variation versus pad size.3. D2PAK Junction−to−Ambient Thermal Resistance is for vertical mounting. Refer to Figure 26 for board mounted Thermal Resistance.4. NCV rated devices are subjected to and meet the AECQ−100 quality standards.
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ELECTRICAL CHARACTERISTICS (Vin = 14 V, IO = 10 mA, CO = 100 �F, CO(ESR) = 0.3 �, TA = 25°C [Note 5])
Characteristic Symbol
LM2931−5.0/NCV2931−5.0 LM2931A−5.0/NCV2931A−5.0
UnitMin Typ Max Min Typ Max
FIXED OUTPUT
Output Voltage VO V
Vin = 14 V, IO = 10 mA, TA = 25°C 4.75 5.0 5.25 4.81 5.0 5.19
Vin = 6.0 V to 26 V, IO ≤ 100 mA,TA = −40° to +125°C
4.50 − 5.50 4.75 − 5.25
Line Regulation Regline mV
Vin = 9.0 V to 16 V − 2.0 10 − 2.0 10
Vin = 6.0 V to 26 V − 4.0 30 − 4.0 30
Load Regulation (IO = 5.0 mA to 100 mA) Regload − 14 50 − 14 50 mV
Output Impedance ZO m�
IO = 10 mA, �IO = 1.0 mA, f = 100 Hz to10 kHz
− 200 − − 200 −
Bias Current IB mA
Vin = 14 V, IO = 100 mA, TA = 25°C − 5.8 30 − 5.8 30
Vin = 6.0 V to 26 V, IO = 10 mA, TA = −40° to+125°C
− 0.4 1.0 − 0.4 1.0
Output Noise Voltage (f = 10 Hz to 100 kHz) Vn − 700 − − 700 − �Vrms
Long Term Stability S − 20 − − 20 − mV/kHR
Ripple Rejection (f = 120 Hz) RR 60 90 − 60 90 − dB
Dropout Voltage VI−VO V
IO = 10 mA − 0.015 0.2 − 0.015 0.2
IO = 100 mA − 0.16 0.6 − 0.16 0.6
Over−Voltage Shutdown Threshold Vth(OV) 26 29.5 40 26 29.5 40 V
Output Voltage with Reverse Polarity Input(Vin = −15 V)
−VO −0.3 0 − −0.3 0 − V
5. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.6. NCV devices are qualified for automotive use.
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ELECTRICAL CHARACTERISTICS (Vin = 14 V, IO = 10 mA, CO = 100 �F, CO(ESR) = 0.3 �, TA = 25°C [Note 7])
LM2931C/NCV2931C LM2931AC/NCV2931AC
Characteristic Symbol Min Typ Max Min Typ Max Unit
ADJUSTABLE OUTPUT
Reference Voltage (Note 8, Figure 18) Vref VIO = 10 mA, TA = 25°C 1.14 1.20 1.26 1.17 1.20 1.23IO ≤ 100 mA, TA = −40 to +125°C 1.08 − 1.32 1.15 − 1.25
Output Voltage Range VO range 3.0 to24
2.7 to29.5
− 3.0 to24
2.7 to29.5
− V
Line Regulation (Vin = VO + 0.6 V to 26 V) Regline − 0.2 1.5 − 0.2 1.5 mV/V
Load Regulation (IO = 5.0 mA to 100 mA) Regload − 0.3 1.0 − 0.3 1.0 %/V
Output Impedance ZO m��VIO = 10 mA, �IO = 1.0 mA, f = 10 Hz to 10 kHz − 40 − − 40 −
Bias Current IB mAIO = 100 mA − 6.0 − − 6.0 −IO = 10 mA − 0.4 1.0 − 0.4 1.0Output Inhibited (Vth(OI) = 2.5 V) − 0.2 1.0 − 0.2 1.0
Adjustment Pin Current IAdj − 0.2 − − 0.2 − �A
Output Noise Voltage (f = 10 Hz to 100 kHz) Vn − 140 − − 140 − �Vrms/V
Long−Term Stability S − 0.4 − − 0.4 − %/kHR
Ripple Rejection (f = 120 Hz) RR 0.10 0.003 − 0.10 0.003 − %/V
Dropout Voltage VI−VO VIO = 10 mA − 0.015 0.2 − 0.015 0.2IO = 100 mA − 0.16 0.6 − 0.16 0.6
Over−Voltage Shutdown Threshold Vth(OV) 26 29.5 40 26 29.5 40 V
Output Voltage with Reverse Polarity Input(Vin = −15 V)
−VO −0.3 0 − −0.3 0 − V
Output Inhibit Threshold Voltages Vth(OI) VOutput “On”: TA = 25°C − 2.15 1.90 − 2.15 1.90
TA = −40° to +125°C − − 1.20 − − 1.20Output “Off”: TA = 25°C 2.50 2.26 − 2.50 2.26 −
TA = −40° to +125°C 3.25 − − 3.25 − −
Output Inhibit Threshold Current (Vth(OI) = 2.5 V) Ith(OI) − 30 50 − 30 50 �A
7. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible.8. The reference voltage on the adjustable device is measured from the output to the adjust pin across R1.
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IO = 100 mA
IO = 10 mA
, OU
TPU
T VO
LTAG
E (V
)OV
-Vin
O, D
RO
POU
T VO
LTAG
E (m
V)V
Vin, INPUT VOLTAGE (V)-20 -10 0 10 20 30 40 50 600
1.0
2.0
3.0
4.0
5.0
6.0
Vout = 5.0 VRL = 500 �TA = 25°C
, OU
TPU
T C
UR
REN
T (m
A)O
Vin, INPUT VOLTAGE (V)
50
150
250
350
0 5.0 10 15 20 25 30
I
TJ = -40°CTJ = 25°C
TJ = 85°C
V in
(10
V/D
IV)
V O(5
.0 V
/DIV
)
0
0
t, TIME (50 ms/DIV)
, IN
PUT
VOLT
AGE
, OU
TPU
T VO
LTAG
E, O
UTP
UT
VOLT
AGE
(V)
O
Vin, INPUT VOLTAGE (V)
0
1.0
2.0
3.0
4.0
5.0
6.0
0 1.0 2.0 3.0 4.0 5.0 6.0
V
TJ, JUNCTION TEMPERATURE (°C)
0
100
200
300
0 25 50 75 100 125
IO = 50 mA
-Vin
O
IO, OUTPUT CURRENT (mA)
0 20 40 60 80 1000
40
80
120
160
200
Vin = 14 V�Vout = 100 mVTJ = 25°C
, DR
OPO
UT
VOLT
AGE
(mV)
V
Vout = 5.0 VRL = 50 �CO = 100 �F� = 150 msTA = 25°C
VCC = 15 VVFB1 = 5.05 V
Dashed lines below Vin = 5.0 Vare for Adjustable output devices only.
Figure 1. Dropout Voltage versus Output Current
Vin = 14 V�Vout = 100 mV
Vout = 5.0 VTA = 25°C
RL = 50 � IO = 100 mA
Figure 1. Dropout Voltage versus Output Current Figure 2. Dropout Voltage versusJunction Temperature
Figure 3. Peak Output Current versus Input Voltage Figure 4. Output Voltage versus Input Voltage
Figure 5. Output Voltage versus Input Voltage Figure 6. Load Dump Characteristics
LM2931, NCV2931 Series
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I B, B
IAS
CU
RR
ENT
(mA)
I B, B
IAS
CU
RR
ENT
(mA)
I B
Vin, INPUT VOLTAGE (V)
0
2.0
4.0
6.0
8.0
10
12
-20 -10 0 10 20 30 40 50 60
RL = 50 �
, BIA
S C
UR
REN
T (m
A)
TJ, JUNCTION TEMPERATURE (°C)-55 -25 0 25 50 75 100 1250
2.0
4.0
6.0
8.0
IO = 100 mA
RR
, RIP
PLE
REJ
ECTI
ON
RAT
IO (d
B)
f, FREQUENCY (Hz)
55
65
75
85
95
10 100 1.0 k 1.0 M 10 M
CO(ESR) = 0.15 �Tantulum
RR
, RIP
PLE
REJ
ECTI
ON
RAT
IO (d
B)
85
95
0 20 40 60 80 100IO, OUTPUT CURRENT (mA)
Ω
f, FREQUENCY (Hz)
, OU
TPU
T IM
PED
ANC
E (
� )O
0
0.4
0.8
1.2
1.6
2.0
10 100 1.0 k 10 k 100 k 1.0 M 10 M
I
CO(ESR) = 0.3 �Electrolytic
CO(ESR) = 0.15 �Tantulum
0
2.0
4.0
6.0
8.0
0 20 40 60 80 100
IO, OUTPUT CURRENT (mA)
IO = 0 mA
IO = 50 mA
Vout = 5.0 VTJ = 25°C
Vin = 14 VVout = 5.0 VIO = 10 mADIO = 1.0 mACO = 100 �FTJ = 25°C
Vin = 14 VVout = 5.0 V
65
75
Vin = 14 VVout = 5.0 Vf = 120 HzTJ = 25°C
Vin = 14 VVout = 5.0 VDVin = 100 mVRL = 500 �CO = 100 �FTJ = 25°C
CO(ESR) = 0.3 �Electrolytic
10 k 100 k
Figure 7. Bias Current versus Input Voltage Figure 8. Bias Current versus Output Current
Figure 9. Bias Current versus Junction Temperature Figure 10. Output Impedance versus Frequency
Figure 11. Ripple Rejection versus Frequency Figure 12. Ripple Rejection versus Output Current
RL = 100 �
RL = 500 �
Vin = 14 VVout = 5.0 VTJ = 25°C
LM2931, NCV2931 Series
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, REF
EREN
CE
VOLT
AGE
(V)
ref
VO, OUTPUT VOLTAGE (V)
1.160
1.180
1.200
1.220
1.240
0 3.0 6.0 9.0 12 15 18 21 24
V
18.5
14
t, TIME (10 �s/DIV)
Vout = 5.0 VRL = 500 �CO = 100 �FCO(ESR) = 0.3 �TA = 25°C
100
0
t, TIME (10 �s/DIV)
VO, OUTPUT VOLTAGE (V)
Vth
(on/
off)
, OU
TPU
T IN
HIB
IT‐T
HR
ESH
OLD
S (V
)
2.0
2.1
2.2
0 3.0 6.0 9.0 12 15 18 21 24
Output “On"
Output “Off"
2.4
2.5
2.6
2.3
LM2931C AdjustableIO = 10 mAVin = Vout + 1.0 VTA = 25°C
Vin = 14 VVout = 5.0 VCin = 1000 �F
CO = 100 �FCO(ESR) = 0.3 �TA = 25°C
LM2931C AdjustableIO = 10 mAVin = Vout + 1.0 VTA = 25°C
OU
TPU
T C
UR
REN
T,I
(
mA)
out
ΔO
UTP
UT
VOLT
AGE
DEV
IATI
ON
,O
, (2.
0 m
V/D
IV)
V
INPU
T VO
LTAG
E,V
, (V
)in
ΔO
UTP
UT
VOLT
AGE
DEV
IATI
ON
,O
, (2.
0 m
V/D
IV)
V
Figure 13. Line Regulation Figure 14. Load Regulation
Figure 15. Reference Voltage versus Output Voltage Figure 16. Output Inhibit−Thresholds versus Output Voltage
APPLICATIONS INFORMATION
The LM2931 series regulators are designed with manyprotection features making them essentially blow−outproof. These features include internal current limiting,thermal shutdown, overvoltage and reverse polarity inputprotection, and the capability to withstand temporarypower−up with mirror−image insertion. Typical applicationcircuits for the fixed and adjustable output device are shownin Figures 17 and 18.
The input bypass capacitor Cin is recommended if theregulator is located an appreciable distance (≥ 4″) from thesupply input filter. This will reduce the circuit’s sensitivityto the input line impedance at high frequencies.
This regulator series is not internally compensated andthus requires an external output capacitor for stability. Thecapacitance value required is dependent upon the loadcurrent, output voltage for the adjustable regulator, and thetype of capacitor selected. The least stable condition isencountered at maximum load current and minimum outputvoltage. Figure 22 shows that for operation in the “Stable”region, under the conditions specified, the magnitude of theoutput capacitor impedance |ZO| must not exceed 0.4 �. This
limit must be observed over the entire operating temperaturerange of the regulator circuit.
With economical electrolytic capacitors, cold temperatureoperation can pose a serious stability problem. As theelectrolyte freezes, around −30°C, the capacitance willdecrease and the equivalent series resistance (ESR) willincrease drastically, causing the circuit to oscillate. Qualityelectrolytic capacitors with extended temperature ranges of−40° to +85°C and −55° to +105°C are readily available.Solid tantalum capacitors may be a better choice if small sizeis a requirement, however, the maximum ⏐ZO⏐ limit overtemperature must be observed.
Note that in the stable region, the output noise voltage islinearly proportional to ⏐ZO⏐. In effect, CO dictates the highfrequency roll−off point of the circuit. Operation in the areatitled “Marginally Stable” will cause the output of theregulator to exhibit random bursts of oscillation that decayin an under−damped fashion. Continuous oscillation occurswhen operating in the area titled “Unstable”. It is suggestedthat oven testing of the entire circuit be performed withmaximum load, minimum input voltage, and minimumambient temperature.
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Figure 17. Fixed Output Regulator Figure 18. Adjustable Output Regulator
Figure 19. (5.0 A) Low DifferentialVoltage Regulator
Figure 20. Current Boost Regulator withShort Circuit Projection
Figure 21. Constant Intensity Lamp Flasher
Vin
Input OutputVout
COIBGND
Cin0.1
LM2931-5.0FixedOutput
Switch Position 1 = Output “On", 2 = Output “Off"
LM2931CAdjustable
Output
Vin
Cin0.1
Vout
CO
OutputInput
51 k
1
2OutputInhibit Adjust
GND
IAdj
R1
R2IB
The LM2931 series can be current boosted with a PNP transistor. TheD45VH7, on a heatsink, will provide an output current of 5.0 A with an inputto output voltage differential of approximately 1.0 V. Resistor R inconjunction with the VBE of the PNP determines when the pass transistorbegins conducting. This circuit is not short circuit proof.
Input≥ 6.0 V
D45VH7
5.0 V @ 5.0 A
Output100
+100
+
68
LM2931-5.0
LM2931C
Input6.4 V to 30 V
2.0 k
8.2 k
100
+
CM#345
100+ 33 k
6.2 V
fosc = 2.2 Hz0
22.5�k� ��R1�R2
R1� �� R2Vout� �� Vref��1� ��
R2R1�� �� IAdj�R2
R
The circuit of Figure 19 can be modified to provide supply protection againstshort circuits by adding the current sense resistor RSC and an additional PNPtransistor. The current sensing PNP must be capable of handling the shortcircuit current of the LM2931. Safe operating area of both transistors must beconsidered under worst case conditions.
Input
R
RSC
OutputLM2931-5.0
100 100+ +
LM2931, NCV2931 Series
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0.20
0.30
0.00
ESR
(Ohm
s)
Figure 22. Output Noise Voltage vs.Output Capacitor Impedance
Figure 23. Output Capacitor ESR Stability vs.Output Load Current
OUTPUT CURRENT (mA)10 50 90 100
0.50
0.60
Note - Optimum stability uses a 22 �Foutput capacitor. Output capacitor valuesbelow 10 �F are not recommended.
Unstable
Stable
0.1
1.0
0.01
V n, O
UTP
UT
NO
ISE
VOLT
AGE
(mVr
ms)
|ZO|, MAGNITUDE OF CAPACITOR IMPEDANCE (m�)10 100 1.0 k 10 k
10
100Vin = 5.6 VVout = 5.0 VIO = 100 mAVnrms 10 Hz to 10 MHz|ZO| @ 40 kHzTA = 25°C
Unstable
MarginallyStable
Stable
0
0.10
0.40
20 6030 7040 80
22 �F10 �F
47 �F100 �F
40
50
60
70
80
90
100
0
0.4
0.8
1.2
1.6
2.0
2.4
0 10 20 3025155.0
L, LENGTH OF COPPER (mm)
PD(max) for TA = 50°C
MinimumSize Pad
P D
L
L
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
, MAX
IMU
M P
OW
ER D
ISSI
PATI
ON
(W)
Free AirMountedVertically
30
50
70
90
110
130
150
0.4
0.8
1.2
1.6
2.0
2.4
2.8
0 20 30 504010
L, LENGTH OF COPPER (mm)
170 3.2
R�JA P D
R, T
HER
MAL
RES
ISTA
NC
EJAθ JU
NC
TIO
N-T
O-A
IR (
C/W
)°
, MAX
IMU
M P
OW
ER D
ISSI
PATI
ON
(W)
ÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎ
2.0 oz.Copper
Graph represents symmetrical layout
3.0 mmL
L
R�JA
2.0 oz. Copper
R, T
HER
MAL
RES
ISTA
NC
EJAθ JU
NC
TIO
N-T
O-A
IR (
C/W
)°
Figure 24. SOP−8 Thermal Resistance and MaximumPower Dissipation versus P.C.B. Copper Length
Figure 25. DPAK Thermal Resistance and MaximumPower Dissipation versus P.C.B. Copper Length
PD(max) for TA = 50°C
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0
50
100
150
200
250
300
0.0
0.6
1.0
1.2
1.4
1.8
0 10 20 3025155.0
L, LENGTH OF COPPER (mm)
PD(max) for TA = 50°C
R�JA
, TH
ER
MA
L R
ES
ISTA
NC
E,
JUN
CT
ION−
TO−
AIR
(°C
W)
PD
, MA
XIM
UM
PO
WE
R D
ISS
IPA
TIO
N (
W)
R�JA
L
L
2.0 oz. Copper
ÎÎÎÎÎÎÎÎÎ
0.4
1.6
0.2
0.8
30
40
50
60
70
80
1.0
1.5
2.0
2.5
3.0
3.5
0 10 20 3025155.0
L, LENGTH OF COPPER (mm)
PD(max) for TA = 50°C
MinimumSize Pad
2.0 oz. CopperL
L
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Free AirMountedVertically
P D, M
AXIM
UM
PO
WER
DIS
SIPA
TIO
N (W
)
R�JAR
, TH
ERM
AL R
ESIS
TAN
CE
JAθ JUN
CTI
ON
-TO
-AIR
( C
/W)
°
Figure 26. 3−Pin and 5−Pin D2PAKThermal Resistance and Maximum PowerDissipation versus P.C.B. Copper Length
Figure 27. SOT−223 Thermal Resistance and MaximumPower Dissipation vs. P.C.B. Copper Length
DEFINITIONS
Dropout Voltage − The input/output voltage differentialat which the regulator output no longer maintains regulationagainst further reductions in input voltage. Measured whenthe output decreases 100 mV from nominal value at 14 Vinput, dropout voltage is affected by junction temperatureand load current.
Line Regulation − The change in output voltage for achange in the input voltage. The measurement is made underconditions of low dissipation or by using pulse techniquessuch that the average chip temperature is not significantlyaffected.
Load Regulation − The change in output voltage for achange in load current at constant chip temperature.
Maximum Power Dissipation − The maximum totaldevice dissipation for which the regulator will operatewithin specifications.
Bias Current − That part of the input current that is notdelivered to the load.
Output Noise Voltage − The rms AC voltage at theoutput, with constant load and no input ripple, measuredover a specified frequency range.
Long−Term Stability − Output voltage stability underaccelerated life test conditions with the maximum ratedvoltage listed in the devices electrical characteristics andmaximum power dissipation.
LM2931, NCV2931 Series
www.onsemi.com12
ORDERING INFORMATION
Device
Output
Package Shipping†Voltage Tolerance
LM2931AD−5.0 5.0 V �3.8% SOIC−8 98 Units / Rail
LM2931AD−5.0G5.0 V �3.8%
SOIC−8(Pb−Free)
98 Units / Rail
LM2931AD−5.0R2 5.0 V �3.8% SOIC−8 2500 / Tape & Reel
LM2931AD−5.0R2G5.0 V �3.8%
SOIC−8(Pb−Free)
2500 / Tape & Reel
LM2931ADT−5.0 5.0 V �3.8% DPAK 75 Units / Rail
LM2931ADT−5.0G5.0 V �3.8%
DPAK(Pb−Free)
75 Units / Rail
LM2931ADT−5.0RK 5.0 V �3.8% DPAK 2500 / VacPk Reel
LM2931ADT−5.0RKG5.0 V �3.8%
DPAK(Pb−Free)
2500 / VacPk Reel
LM2931AD2T−5.0 5.0 V �3.8% D2PAK 50 Units / Rail
LM2931AD2T−5.0G5.0 V �3.8%
D2PAK(Pb−Free)
50 Units / Rail
LM2931AD2T−5.0R4 5.0 V �3.8% D2PAK 800 / VacPk Reel
LM2931AD2T−5R4G5.0 V �3.8%
D2PAK(Pb−Free)
800 / VacPk Reel
LM2931AT−5.0 5.0 V �3.8% TO−220 50 Units / Rail
LM2931AT−5.0G5.0 V �3.8%
TO−220(Pb−Free)
50 Units / Rail
LM2931AZ−5.0 5.0 V �3.8% TO−92 2000 / Inner Bag
LM2931AZ−5.0G5.0 V �3.8%
TO−92(Pb−Free)
2000 / Inner Bag
LM2931AZ−5.0RA 5.0 V �3.8% TO−92 2000 / Tape & Reel
LM2931AZ−5.0RAG5.0 V �3.8%
TO−92(Pb−Free)
2000 / Tape & Reel
LM2931AZ−5.0RP 5.0 V �3.8% TO−92 2000 / Ammo Pack
LM2931AZ−5.0RPG5.0 V �3.8%
TO−92(Pb−Free)
2000 / Ammo Pack
LM2931D−5.0 5.0 V �5.0% SOIC−8 98 Units / Rail
LM2931D−5.0G5.0 V �5.0%
SOIC−8(Pb−Free)
98 Units / Rail
LM2931D−5.0R2 5.0 V �5.0% SOIC−8 2500 / Tape & Reel
LM2931D−5.0R2G5.0 V �5.0%
SOIC−8(Pb−Free)
2500 / Tape & Reel
LM2931D2T−5.0 5.0 V �5.0% D2PAK 50 Units / Rail
LM2931D2T−5.0G5.0 V �5.0%
D2PAK(Pb−Free)
50 Units / Rail
LM2931D2T−5.0R4 5.0 V �5.0% D2PAK 800 / VacPk Reel
LM2931D2T−5.0R4G5.0 V �5.0%
D2PAK(Pb−Free)
800 / VacPk Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-cifications Brochure, BRD8011/D.
*NCV2931: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV Prefix for Automotive and Other Applications Requiring Unique Siteand Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.
LM2931, NCV2931 Series
www.onsemi.com13
ORDERING INFORMATION
Output
Device Shipping†PackageToleranceVoltage
LM2931DT−5.0 5.0 V �5.0% DPAK 75 Units / Rail
LM2931DT−5.0G5.0 V �5.0%
DPAK(Pb−Free)
75 Units / Rail
LM2931T−5.0 5.0 V �5.0% TO−220 50 Units / Rail
LM2931T−5.0G5.0 V �5.0%
TO−220(Pb−Free)
50 Units / Rail
LM2931Z−5.0 5.0 V �5.0% TO−92 2000 / Inner Bag
LM2931Z−5.0G5.0 V �5.0%
TO−92(Pb−Free)
2000 / Inner Bag
LM2931Z−5.0RA 5.0 V �5.0% TO−92 2000 / Tape & Reel
LM2931Z−5.0RAG5.0 V �5.0%
TO−92(Pb−Free)
2000 / Tape & Reel
LM2931Z−5.0RP 5.0 V �5.0% TO−92 2000 / Ammo Pack
LM2931Z−5.0RPG5.0 V �5.0%
TO−92(Pb−Free)
2000 / Ammo Pack
LM2931CD Adjustable �5.0% SOIC−8 98 Units / Rail
LM2931CDGAdjustable �5.0%
SOIC−8(Pb−Free)
98 Units / Rail
LM2931CDR2 Adjustable �5.0% SOIC−8 2500 / Tape & Reel
LM2931CDR2GAdjustable �5.0%
SOIC−8(Pb−Free)
2500 / Tape & Reel
LM2931CD2T Adjustable �5.0% D2PAK 50 Units / Rail
LM2931CD2TGAdjustable �5.0%
D2PAK(Pb−Free)
50 Units / Rail
LM2931CD2TR4 Adjustable �5.0% D2PAK 800 / VacPk Reel
LM2931CD2TR4GAdjustable �5.0%
D2PAK(Pb−Free)
800 / VacPk Reel
LM2931CT Adjustable �5.0% TO−220 50 Units / Rail
LM2931CTGAdjustable �5.0%
TO−220(Pb−Free)
50 Units / Rail
LM2931ACD Adjustable �2.0% SOIC−8 98 Units / Rail
LM2931ACDGAdjustable �2.0%
SOIC−8(Pb−Free)
98 Units / Rail
LM2931ACDR2 Adjustable �2.0% SOIC−8 2500 / Tape & Reel
LM2931ACDR2GAdjustable �2.0%
SOIC−8(Pb−Free)
2500 / Tape & Reel
LM2931ACD2TR4 Adjustable �2.0% D2PAK 800 / VacPk Reel
LM2931ACD2TR4GAdjustable �2.0%
D2PAK(Pb−Free)
800 / VacPk Reel
LM2931ACTV Adjustable �2.0% TO−220 50 Units / Rail
LM2931ACTVGAdjustable �2.0%
TO−220(Pb−Free)
50 Units / Rail
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-cifications Brochure, BRD8011/D.
*NCV2931: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV Prefix for Automotive and Other Applications Requiring Unique Siteand Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.
LM2931, NCV2931 Series
www.onsemi.com14
ORDERING INFORMATION
Output
Device Shipping†PackageToleranceVoltage
NCV2931ACDR2* Adjustable �2.5% SOIC−8 2500 / Tape & Reel
NCV2931ACDR2G*Adjustable �2.5%
SOIC−8(Pb−Free)
2500 / Tape & Reel
NCV2931AD−5.0R2* 5.0 V �3.8% SOIC−8 2500 / Tape & Reel
NCV2931AD−5.0R2G*5.0 V �3.8%
SOIC−8(Pb−Free)
2500 / Tape & Reel
NCV2931AST−5.0T3* 5.0 V �3.8% SOT−223 4000 / Tape & Reel
NCV2931AST−5.0T3G*5.0 V �3.8%
SOT−223(Pb−Free)
4000 / Tape & Reel
NCV2931AZ−5.0G*5.0 V �3.8%
TO−92(Pb−Free)
2000 / Inner Bag
NCV2931AZ−5.0RAG*5.0 V �3.8%
TO−92(Pb−Free)
2000 / Tape & Reel
NCV2931CDR2* Adjustable �5.0% SOIC−8 2500 / Tape & Reel
NCV2931CDR2G*Adjustable �5.0%
SOIC−8(Pb−Free)
2500 / Tape & Reel
NCV2931D−5.0R2* 5.0 V �5.0% SOIC−8 2500 / Tape & Reel
NCV2931D−5.0R2G*5.0 V �5.0%
SOIC−8(Pb−Free)
2500 / Tape & Reel
NCV2931ADT−5.0RK* 5.0 V �3.8% DPAK 2500 / Tape & Reel
NCV2931ADT5.0RKG*5.0 V �3.8%
DPAK(Pb−Free)
2500 / Tape & Reel
NCV2931DT−5.0RK* 5.0 V �5.0% DPAK 2500 / Tape & Reel
NCV2931DT−5.0RKG*5.0 V �5.0%
DPAK(Pb−Free)
2500 / Tape & Reel
NCV2931ACD2TR4G* Adjustable �2.5%D2PAK
(Pb−Free) 800 / VacPk Reel
NCV2931D2T−5.0R4* 5.0 V �5.0% D2PAK 800 / VacPk Reel
NCV2931D2T5.0R4G*5.0 V �5.0%
D2PAK(Pb−Free)
800 / VacPk Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Spe-cifications Brochure, BRD8011/D.
*NCV2931: Tlow = −40°C, Thigh = +125°C. Guaranteed by design. NCV Prefix for Automotive and Other Applications Requiring Unique Siteand Control Change Requirements; AEC−Q100 Qualified and PPAP Capable.
LM2931, NCV2931 Series
www.onsemi.com15
SOIC−8D SUFFIXCASE 751
A = Assembly LocationWL, L = Wafer LotYY, Y = YearWW, W = Work WeekG or � = Pb−Free Device
MARKING DIAGRAMS
AWLYWWG
LM2931AT−5
TO−220T SUFFIX
CASE 221A
2931T−5.0LM
TO−220T SUFFIX
CASE 221A
AWLYWWG
931A5GALYWW
DPAKDT SUFFIXCASE 369A
2931GALYWW
DPAKDT SUFFIXCASE 369A
LM2931AD2T−5.0
AWLYWWG
D2PAKD2T SUFFIXCASE 936
LM2931AD2T−5AWLYWWG
D2PAKD2T SUFFIXCASE 936
LM2931D2T−5AWLYWWG
D2PAKD2T SUFFIXCASE 936
TO−220T SUFFIX
CASE 314D
ALYWW
LM2931ACTVAWLYWWG
D2PAKD2T SUFFIXCASE 936A
LM2931ACD2TAWLYWWG
D2PAKD2T SUFFIXCASE 936A
LM2931CT
AWLYWWG
2931AZ−5.0ALYW
TO−92Z SUFFIXCASE 029
2931Z−5.0
ALYW
TO−92Z SUFFIXCASE 029
Heatsink surface connected to Pin 2.
Heatsink surface (shown as terminal 4 in case outline drawing) is connected to Pin 2.
Heatsink surface (shown as terminal 6 incase outline drawing) is connected to Pin 3.
Heatsink surfaceconnected to Pin 3.
*
*This marking diagram also applies to NCV2931.
* *
*
SOT−223ST SUFFIXCASE 318H
ALYW2931A�
�
1 2 3
SOIC−8D SUFFIXCASE 751
SOIC−8D SUFFIXCASE 751
SOIC−8D SUFFIXCASE 751
*
2931AALYW
�1
8
2931AALYW5
�1
8
2931CALYW
�1
8
2931ALYW5
�1
8
TO−220, SINGLE GAUGECASE 221AB−01
ISSUE ADATE 16 NOV 2010
SCALE 1:1
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: INCHES.3. DIMENSION Z DEFINES A ZONE WHERE ALL BODY AND
LEAD IRREGULARITIES ARE ALLOWED.4. PRODUCT SHIPPED PRIOR TO 2008 HAD DIMENSIONS
S = 0.045 - 0.055 INCHES (1.143 - 1.397 MM)
STYLE 1:PIN 1. BASE
2. COLLECTOR3. EMITTER4. COLLECTOR
STYLE 2:PIN 1. BASE
2. EMITTER3. COLLECTOR4. EMITTER
STYLE 3:PIN 1. CATHODE
2. ANODE3. GATE4. ANODE
STYLE 4:PIN 1. MAIN TERMINAL 1
2. MAIN TERMINAL 23. GATE4. MAIN TERMINAL 2
STYLE 7:PIN 1. CATHODE
2. ANODE3. CATHODE4. ANODE
STYLE 10:PIN 1. GATE
2. SOURCE3. DRAIN4. SOURCE
STYLE 5:PIN 1. GATE
2. DRAIN3. SOURCE4. DRAIN
STYLE 8:PIN 1. CATHODE
2. ANODE3. EXTERNAL TRIP/DELAY4. ANODE
STYLE 6:PIN 1. ANODE
2. CATHODE3. ANODE4. CATHODE
STYLE 9:PIN 1. GATE
2. COLLECTOR3. EMITTER4. COLLECTOR
STYLE 11:PIN 1. DRAIN
2. SOURCE3. GATE4. SOURCE
DIM MIN MAX MIN MAXMILLIMETERSINCHES
A 0.570 0.620 14.48 15.75B 0.380 0.405 9.66 10.28C 0.160 0.190 4.07 4.82D 0.025 0.035 0.64 0.88F 0.142 0.147 3.61 3.73G 0.095 0.105 2.42 2.66H 0.110 0.155 2.80 3.93J 0.018 0.025 0.46 0.64K 0.500 0.562 12.70 14.27L 0.045 0.060 1.15 1.52N 0.190 0.210 4.83 5.33Q 0.100 0.120 2.54 3.04R 0.080 0.110 2.04 2.79S 0.020 0.024 0.508 0.61T 0.235 0.255 5.97 6.47U 0.000 0.050 0.00 1.27V 0.045 --- 1.15 ---Z --- 0.080 --- 2.04
B
Q
H
Z
L
V
G
N
A
K
F
1 2 3
4
D
SEATINGPLANE−T−
CST
U
R
J
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON23085DDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1TO−220, SINGLE GAUGE
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TO−92 (TO−226) 1 WATTCASE 29−10
ISSUE DDATE 05 MAR 2021
STYLES AND MARKING ON PAGE 3
SCALE 1:1
1 23
12
BENT LEADSTRAIGHT LEAD3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON52857EDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 3TO−92 (TO−226) 1 WATT
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TO−92 (TO−226) 1 WATTCASE 29−10
ISSUE DDATE 05 MAR 2021
STYLES AND MARKING ON PAGE 3
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON52857EDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 3TO−92 (TO−226) 1 WATT
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TO−92 (TO−226) 1 WATTCASE 29−10
ISSUE DDATE 05 MAR 2021
STYLE 1:PIN 1. EMITTER
2. BASE3. COLLECTOR
STYLE 6:PIN 1. GATE
2. SOURCE & SUBSTRATE3. DRAIN
STYLE 11:PIN 1. ANODE
2. CATHODE & ANODE3. CATHODE
STYLE 16:PIN 1. ANODE
2. GATE3. CATHODE
STYLE 21:PIN 1. COLLECTOR
2. EMITTER3. BASE
STYLE 26:PIN 1. VCC
2. GROUND 23. OUTPUT
STYLE 31:PIN 1. GATE
2. DRAIN3. SOURCE
STYLE 2:PIN 1. BASE
2. EMITTER3. COLLECTOR
STYLE 7:PIN 1. SOURCE
2. DRAIN3. GATE
STYLE 12:PIN 1. MAIN TERMINAL 1
2. GATE3. MAIN TERMINAL 2
STYLE 17:PIN 1. COLLECTOR
2. BASE3. EMITTER
STYLE 22:PIN 1. SOURCE
2. GATE3. DRAIN
STYLE 27:PIN 1. MT
2. SUBSTRATE3. MT
STYLE 32:PIN 1. BASE
2. COLLECTOR3. EMITTER
STYLE 3:PIN 1. ANODE
2. ANODE3. CATHODE
STYLE 8:PIN 1. DRAIN
2. GATE3. SOURCE & SUBSTRATE
STYLE 13:PIN 1. ANODE 1
2. GATE3. CATHODE 2
STYLE 18:PIN 1. ANODE
2. CATHODE3. NOT CONNECTED
STYLE 23:PIN 1. GATE
2. SOURCE3. DRAIN
STYLE 28:PIN 1. CATHODE
2. ANODE3. GATE
STYLE 33:PIN 1. RETURN
2. INPUT3. OUTPUT
STYLE 4:PIN 1. CATHODE
2. CATHODE3. ANODE
STYLE 9:PIN 1. BASE 1
2. EMITTER3. BASE 2
STYLE 14:PIN 1. EMITTER
2. COLLECTOR3. BASE
STYLE 19:PIN 1. GATE
2. ANODE3. CATHODE
STYLE 24:PIN 1. EMITTER
2. COLLECTOR/ANODE3. CATHODE
STYLE 29:PIN 1. NOT CONNECTED
2. ANODE3. CATHODE
STYLE 34:PIN 1. INPUT
2. GROUND3. LOGIC
STYLE 5:PIN 1. DRAIN
2. SOURCE3. GATE
STYLE 10:PIN 1. CATHODE
2. GATE3. ANODE
STYLE 15:PIN 1. ANODE 1
2. CATHODE3. ANODE 2
STYLE 20:PIN 1. NOT CONNECTED
2. CATHODE3. ANODE
STYLE 25:PIN 1. MT 1
2. GATE3. MT 2
STYLE 30:PIN 1. DRAIN
2. GATE3. SOURCE
STYLE 35:PIN 1. GATE
2. COLLECTOR3. EMITTER
XXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.
GENERICMARKING DIAGRAM*
XXXXXXXXXXALYW�
�
(Note: Microdot may be in either location)
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON52857EDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 3 OF 3TO−92 (TO−226) 1 WATT
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
CASE 314B−05ISSUE L
DATE 01/07/1994TO−220 5 LEAD OFFSET
SCALE 1:1
STYLE 5:PIN 1. GATE
2. MIRROR3. DRAIN4. KELVIN5. SOURCE
V
STYLE 1 THRU 4:CANCELLED
Q
K F
UA
B
G
−P−
M0.10 (0.254) P MT
5X JM0.24 (0.610) T
OPTIONAL CHAMFER
S LW
E
C
H
N
−T− SEATINGPLANE
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.DIMENSION D INCLUDING PROTRUSION SHALLNOT EXCEED 0.043 (1.092) MAXIMUM.
DIM MIN MAX MIN MAXMILLIMETERSINCHES
A 0.572 0.613 14.529 15.570B 0.390 0.415 9.906 10.541C 0.170 0.180 4.318 4.572D 0.025 0.038 0.635 0.965E 0.048 0.055 1.219 1.397F 0.850 0.935 21.590 23.749G 0.067 BSC 1.702 BSCH 0.166 BSC 4.216 BSCJ 0.015 0.025 0.381 0.635K 0.900 1.100 22.860 27.940L 0.320 0.365 8.128 9.271N 0.320 BSC 8.128 BSCQ 0.140 0.153 3.556 3.886S --- 0.620 --- 15.748U 0.468 0.505 11.888 12.827V --- 0.735 --- 18.669W 0.090 0.110 2.286 2.794
5X D
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42218BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1TO−220 5 LEAD OFFSET
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
TO−220 5−LEADCASE 314D−04
ISSUE HDATE 29 JAN 2010
SCALE 1:1
STYLE 1 THRU 4:1. OBSOLETE
A = Assembly LocationWL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package
GENERICMARKING DIAGRAM*
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
XXXXXXXXXXXAWLYWWG
1
−Q−
1 2 3 4 5
U
K
DG
A
B1
5 PL
JH
L
EC
MQM0.356 (0.014) T
SEATINGPLANE−T−
DIM MIN MAX MIN MAXMILLIMETERSINCHES
A 0.572 0.613 14.529 15.570B 0.390 0.415 9.906 10.541
C 0.170 0.180 4.318 4.572D 0.025 0.038 0.635 0.965E 0.048 0.055 1.219 1.397G 0.067 BSC 1.702 BSCH 0.087 0.112 2.210 2.845J 0.015 0.025 0.381 0.635K 0.977 1.045 24.810 26.543L 0.320 0.365 8.128 9.271Q 0.140 0.153 3.556 3.886U 0.105 0.117 2.667 2.972
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCH.3. DIMENSION D DOES NOT INCLUDE
INTERCONNECT BAR (DAMBAR) PROTRUSION.DIMENSION D INCLUDING PROTRUSION SHALLNOT EXCEED 10.92 (0.043) MAXIMUM.
B1 0.375 0.415 9.525 10.541
BDETAIL A-A
B1
B
DETAIL A−A
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42220BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1TO−220 5−LEAD
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOT−223CASE 318H
ISSUE BDATE 13 MAY 2020
SCALE 2:1
1
A = Assembly LocationY = YearW = Work WeekXXXXX = Specific Device Code� = Pb−Free Package
GENERICMARKING DIAGRAM*
AYWXXXXX�
�
(Note: Microdot may be in either location)
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASH70634ADOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1SOT−223
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
DPAK (SINGLE GAUGE)CASE 369C
ISSUE FDATE 21 JUL 2015
SCALE 1:1
STYLE 1:PIN 1. BASE
2. COLLECTOR3. EMITTER4. COLLECTOR
STYLE 2:PIN 1. GATE
2. DRAIN3. SOURCE4. DRAIN
STYLE 3:PIN 1. ANODE
2. CATHODE3. ANODE4. CATHODE
STYLE 4:PIN 1. CATHODE
2. ANODE3. GATE4. ANODE
STYLE 5:PIN 1. GATE
2. ANODE3. CATHODE4. ANODE
STYLE 6:PIN 1. MT1
2. MT23. GATE4. MT2
STYLE 7:PIN 1. GATE
2. COLLECTOR3. EMITTER4. COLLECTOR
1 23
4
STYLE 8:PIN 1. N/C
2. CATHODE3. ANODE4. CATHODE
STYLE 9:PIN 1. ANODE
2. CATHODE3. RESISTOR ADJUST4. CATHODE
STYLE 10:PIN 1. CATHODE
2. ANODE3. CATHODE4. ANODE
b
D
E
b3
L3
L4b2
M0.005 (0.13) C
c2
A
c
C
Z
DIM MIN MAX MIN MAXMILLIMETERSINCHES
D 0.235 0.245 5.97 6.22E 0.250 0.265 6.35 6.73
A 0.086 0.094 2.18 2.38
b 0.025 0.035 0.63 0.89
c2 0.018 0.024 0.46 0.61
b2 0.028 0.045 0.72 1.14
c 0.018 0.024 0.46 0.61
e 0.090 BSC 2.29 BSC
b3 0.180 0.215 4.57 5.46
L4 −−− 0.040 −−− 1.01
L 0.055 0.070 1.40 1.78
L3 0.035 0.050 0.89 1.27
Z 0.155 −−− 3.93 −−−
NOTES:1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.2. CONTROLLING DIMENSION: INCHES.3. THERMAL PAD CONTOUR OPTIONAL WITHIN DI-
MENSIONS b3, L3 and Z.4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR BURRS. MOLDFLASH, PROTRUSIONS, OR GATE BURRS SHALLNOT EXCEED 0.006 INCHES PER SIDE.
5. DIMENSIONS D AND E ARE DETERMINED AT THEOUTERMOST EXTREMES OF THE PLASTIC BODY.
6. DATUMS A AND B ARE DETERMINED AT DATUMPLANE H.
7. OPTIONAL MOLD FEATURE.
1 2 3
4
XXXXXX = Device CodeA = Assembly LocationL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package
AYWWXXXXXXXXG
XXXXXXGALYWW
DiscreteIC
5.800.228
2.580.102
1.600.063
6.200.244
3.000.118
6.170.243
� mminches
�SCALE 3:1
GENERICMARKING DIAGRAM*
*This information is generic. Please referto device data sheet for actual partmarking.
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
H 0.370 0.410 9.40 10.41
A1 0.000 0.005 0.00 0.13
L1 0.114 REF 2.90 REFL2 0.020 BSC 0.51 BSC
A1
HDETAIL A
SEATINGPLANE
A
B
C
L1L
H
L2 GAUGEPLANE
DETAIL AROTATED 90 CW�
eBOTTOM VIEW
Z
BOTTOM VIEW
SIDE VIEW
TOP VIEW
ALTERNATECONSTRUCTIONS
NOTE 7
Z
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98AON10527DDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1DPAK (SINGLE GAUGE)
© Semiconductor Components Industries, LLC, 2018 www.onsemi.com
SOIC−8 NBCASE 751−07
ISSUE AKDATE 16 FEB 2011
SEATINGPLANE
14
58
N
J
X 45�
K
NOTES:1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.
A
B S
DH
C
0.10 (0.004)
SCALE 1:1
STYLES ON PAGE 2
DIMA
MIN MAX MIN MAXINCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244
−X−
−Y−
G
MYM0.25 (0.010)
−Z−
YM0.25 (0.010) Z S X S
M� � � �
XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package
GENERICMARKING DIAGRAM*
1
8
XXXXXALYWX
1
8
IC Discrete
XXXXXXAYWW
�1
8
1.520.060
7.00.275
0.60.024
1.2700.050
4.00.155
� mminches
�SCALE 6:1
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
Discrete
XXXXXXAYWW
1
8
(Pb−Free)
XXXXXALYWX
�1
8
IC(Pb−Free)
XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42564BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SOIC−8 NBCASE 751−07
ISSUE AKDATE 16 FEB 2011
STYLE 4:PIN 1. ANODE
2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE
STYLE 1:PIN 1. EMITTER
2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER
STYLE 2:PIN 1. COLLECTOR, DIE, #1
2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1
STYLE 3:PIN 1. DRAIN, DIE #1
2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1
STYLE 6:PIN 1. SOURCE
2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE
STYLE 5:PIN 1. DRAIN
2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE
STYLE 7:PIN 1. INPUT
2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd
STYLE 8:PIN 1. COLLECTOR, DIE #1
2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1
STYLE 9:PIN 1. EMITTER, COMMON
2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON
STYLE 10:PIN 1. GROUND
2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND
STYLE 11:PIN 1. SOURCE 1
2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1
STYLE 12:PIN 1. SOURCE
2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN
STYLE 14:PIN 1. N−SOURCE
2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN
STYLE 13:PIN 1. N.C.
2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN
STYLE 15:PIN 1. ANODE 1
2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON
STYLE 16:PIN 1. EMITTER, DIE #1
2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1
STYLE 17:PIN 1. VCC
2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC
STYLE 18:PIN 1. ANODE
2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE
STYLE 19:PIN 1. SOURCE 1
2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1
STYLE 20:PIN 1. SOURCE (N)
2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN
STYLE 21:PIN 1. CATHODE 1
2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6
STYLE 22:PIN 1. I/O LINE 1
2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND
STYLE 23:PIN 1. LINE 1 IN
2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT
STYLE 24:PIN 1. BASE
2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE
STYLE 25:PIN 1. VIN
2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT
STYLE 26:PIN 1. GND
2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC
STYLE 27:PIN 1. ILIMIT
2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN
STYLE 28:PIN 1. SW_TO_GND
2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN
STYLE 29:PIN 1. BASE, DIE #1
2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1
STYLE 30:PIN 1. DRAIN 1
2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASB42564BDOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2SOIC−8 NB
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
SCALE 1:1
D2PAKCASE 936−03
ISSUE EDATE 29 SEP 2015
0
V
U
TERMINAL 4
NOTES:1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.2. CONTROLLING DIMENSION: INCHES.3. TAB CONTOUR OPTIONAL WITHIN DIMENSIONS
A AND K.4. DIMENSIONS U AND V ESTABLISH A MINIMUM
MOUNTING SURFACE FOR TERMINAL 4.5. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH OR GATE PROTRUSIONS. MOLD FLASHAND GATE PROTRUSIONS NOT TO EXCEED0.025 (0.635) MAXIMUM.
6. SINGLE GAUGE DESIGN WILL BE SHIPPED AFTER FPCN EXPIRATION IN OCTOBER 2011.
DIMA
MIN MAX MIN MAXMILLIMETERS
0.386 0.403 9.804 10.236
INCHES
B 0.356 0.368 9.042 9.347C 0.170 0.180 4.318 4.572D 0.026 0.036 0.660 0.914E 0.045 0.055 1.143 1.397
F 0.051 REF 1.295 REFG 0.100 BSC 2.540 BSCH 0.539 0.579 13.691 14.707J 0.125 MAX 3.175 MAXK 0.050 REF 1.270 REFL 0.000 0.010 0.000 0.254M 0.088 0.102 2.235 2.591N 0.018 0.026 0.457 0.660P 0.058 0.078 1.473 1.981RS 0.116 REF 2.946 REFU 0.200 MIN 5.080 MINV 0.250 MIN 6.350 MIN
�
A
1 2 3
K
F
B
J
S
H
DM0.010 (0.254) T
EOPTIONALCHAMFER
*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
8.380
5.080DIMENSIONS: MILLIMETERSPITCH
2X
16.155
1.0162X
10.490
3.504
XXXXXXGALYWW
GENERICMARKING DIAGRAM*
XXXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “ �”,may or may not be present.
BOTTOM VIEWOPTIONAL CONSTRUCTIONS
TOP VIEW
SIDE VIEWDUAL GAUGE
BOTTOM VIEW
L
T
P
R DETAIL C
SEATINGPLANE
2XG
N M
CONSTRUCTION
D
C
DETAIL C
EOPTIONALCHAMFER
SIDE VIEWSINGLE GAUGECONSTRUCTION
S
C
DETAIL C
TT
D
E 0.018 0.026 0.457 0.660S
8� 0� 8�
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASH01005ADOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1 D2PAK
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
D2PAK 5−LEADCASE 936A−02
ISSUE EDATE 28 JUL 2021
SCALE 1:1
GENERICMARKING DIAGRAM*
xxxxxx = Device CodeA = Assembly LocationWL = Wafer LotY = YearWW = Work WeekG = Pb−Free Package
xxxxxxxxxxx
AWLYWWG
*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.
98ASH01006ADOCUMENT NUMBER:
DESCRIPTION:
Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1D2PAK 5−LEAD
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
www.onsemi.com1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patentcoverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liabilityarising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/orspecifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customerapplication by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are notdesigned, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classificationin a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorizedapplication, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, andexpenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if suchclaim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. Thisliterature is subject to all applicable copyright laws and is not for resale in any manner.
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