lecture 06 org comm

8/12/2019 Lecture 06 Org Comm

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Terms

Essential Computer

CPU + Memory Peripheral devices

Any device attached to a computer in order to increase

its functionality.

External: printers, scanners, microphones, speakers, etcInternal: disk drives, CD-ROM drives, modem, etc

Input-only: keyboard and mouse

Output-only: printers

Input and output: writable CD-ROM.

I/O (Input/Output) The transfer of data to/from a computer from/to a

peripheral device (done by a program, operation, or a

device).

Input: from a device to the computer Output: from the computer to a device.


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Input/Output Problems

Wide variety of peripherals Different methods of operation (H/W).

Delivering different amounts of data

At different speeds (and different fromCPU and memory)

In different formats (e.g., word length)

Solution? I/O modules


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I/O Module

Interface to CPU and Memory

Interface to one or more peripheral devices


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Types of I/O Devices

Human readableScreen, printer, keyboard

Machine readable

Magnetic disk, tape Communication

Modem

Network Interface Card (NIC)


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External Device

External Device (Peripheral)

Control Signals

Send data to module,receive data from module,send status, position diskhead.

Status signalsREADY, NOT READY

Buffer: temporarily holddata being transferred,

8-16 bits is common. Transducer: energy-

electrical signals.

Control logicControls o eration.

I/O Module

To/from computer

Computer

Outside world


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Keyboard/Monitor, and Disk Drive

ASCII Printable and control (e. g., carriage return).

KeyboardA key is pressed.

Transducer translates signal into ASCII.

ASCII is transmitted to I/O module in the computer. Text can be stored as ASCII in the computer.

Monitor On output, computer sends ASCII to I/O module. I/O

module sends ASCII to external device (monitor). Transducer at the monitor sends electronic signals to

display the character.

Disk Drive Transducer converts magnetic patterns to/from bits.

Head can be moved in and out across disks surface.


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Lecture 6

Chapter 7. Input/Output (Cont.)


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Functions of I/O Module

1. Control & Timing.

2. CPU Communication.

3. Device Communication.

4. Data Buffering.

5. Error Detection.


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1. Control & Timing - Input Operation

Common CPU, memory, and bustiming is

needed

1. CPU checks I/O module device status.

2. I/O module returns status.

3. If ready, CPU requests data transfer (command

to I/O module).

4. I/O module gets data from external device.

5. I/O module transfers data to CPU.

Variations for output, DMA, etc.

Bus arbitration.


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2. CPU Communication

Decode command

I/O module accepts commands from CPU on control lines.

e.g., SEEK track number (command + parameter on data

lines) for a disk drive.

Recognize address

One unique address for each peripheral it controls.

Exchange data

Between CPU and device over the data bus.

Report status

BUSY, READY, or some error conditions.


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4. Data Buffering (Speed Mismatch)


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5. Error Detection

Mechanical and electrical malfunctionsReport to CPU.

e.g., paper jam, bad disk track.

Bit pattern changes

Parity bit (ASCII).


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I/O Module

Status register: holds device status or accepts control info from CPU Some control lines may be used by the module for bus arbitration.

If module controls more than one device, it has a set of uniqueaddresses.


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I/O Module Decisions

Hide or reveal device properties to CPU.

Support multiple or single device.

Control device functions or leave for CPU.

Also O/S decisions

e.g. Unix treats everything it can as a file

I/O channel(I/O processor)

I/O module takes most of work.

Mainframe.

I/O controller(device controller)

Primitive I/O module.

PC.


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Input Output Techniques

Programmed.

Interrupt driven.

Direct Memory Access (DMA).


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Programmed I/O

CPU (program) has direct control over I/O

Sensing status

Read/write commands

Transferring data

CPU waits for I/O module to complete

operation Wastes CPU time

CPU issues a command to the I/O module.

I/O module performs operation.

I/O module sets status bits. CPU checks status bits periodically.

I/O module does not inform CPU directly.

I/O module does not interrupt CPU.

CPU may wait or come back later.


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I/O Commands

CPU executes an I/O-related instruction.

CPU issues addressIdentifies module (& device if >1 per module)

CPU issues command

Control - telling module what to doe.g. spin up disk

Test - check status

e.g. power? Error?

Read/Write

Module transfers data via buffer from/to device

With programmed I/O, there is a one-to-onemapping between I/O instructions and I/Ocommands.


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Addressing I/O Devices

Under programmedI/O, data transfer is very likememory access (CPU viewpoint).

Each device given unique identifier.

CPU commands contain identifier (address).


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I/O Mapping

Memory mapped I/ODevices and memory share the same addressspace.

I/O looks just like memory read/write.

No special instructions for I/OLarge selection of memory access instructions

available.

Isolated I/O

Separate address spaces

Need I/O or memory select lines

Special instructions for I/O

Limited set


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I/O Mapping - Example


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Interrupt-Driven I/O

Overcomes CPU waiting No repeated CPU checking of device

I/O module interrupts when ready


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Interrupt Driven I/O

Basic Operation

CPU issues read command

I/O module gets data from

peripheral whilst CPU does

other work

I/O module interrupts CPU

CPU requests data

I/O module transfers data


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Identifying Interrupting Module

How do you identify the module issuing the interrupt?

Different line for each module PC

Limits number of devices

Software poll

CPU asks each module in turn Slow

Daisy Chain or Hardware poll Interrupt Acknowledge sent down a chain

Module responsible places vector on bus CPU uses vector to identify handler routine

Bus Master Module must claim the bus before it can raise interrupt

e.g. PCI & SCSI


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Multiple Interrupts

How do you deal with multiple interrupts?

i.e. an interrupt handler being interrupted

Each interrupt line has a priority.

Higher priority lines can interrupt lower priority lines.

If bus mastering only current master can interrupt.


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Example - PC Bus

80x86: one interrupt line.

8086 based systems: 182C59A intrpt controller.

82C59A: 8 intrpt lines.

Sequence of events

82C59A acceptsinterrupts

82C59A determinespriority

82C59A signals 8086

(raises INTR line) CPU Acknowledges

82C59A puts correctvector on data bus

CPU processesinterru t.


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Reading Material

Stallings, chapter 7, pages 222-233

lecture 06 org comm

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