[lecture-07] the thumb instruction sets

7/29/2019 [Lecture-07] the Thumb Instruction Sets

1/22

[email protected]@CS.NCHU, 2012, 2012 1

Lecture 07

The Thumb Instruction Set


2/22


The Thumb Instruction Set

The Thumb instruction set addressed the issue of code density.

It may be viewed as a compressed form of a subset of the ARM instructionset.

Thumb is not a complete architecture. It only supports common applicationfunctions, allowing recourse to the full ARM instruction set wherenecessary.

ARM processors which support the Thumb IS can also execute thestandard 32-bit ARM IS. Not all ARM processors are capable of executingThumb instructions.


3/22


The Thumb bit in the CPSR

The interpretation of the instruction stream at any particular time isdetermined by bit 5 of the CPSR, the T bit (see pp. 40). If T is set theprocessor interprets the instruction stream as 16-bit Thumb instructions,otherwise it interprets it as standard ARM instructions.

Not all ARM processors are capable of executing Thumb instructions; thosethat are have a T in their name, such as the ARM7TDMI described inSection 9.1 on page 248.

Thumb 16-bit compressed instruction set;

On-chip Debug support, enabling the processor to halt in response to a debugrequest.

An enhanced Multiplier, with higher performance than its predecessors andyielding a full 64-bit result.

Embedded ICE hardware to give on-chip breakpoint and watchpoint support.

N Z C V unused mode

31 28 27 8 7 6 5 4 0

I F T


4/22


Thumb entryThe normal way they switch to execute Thumb instructions is by executinga Branch and Exchange instruction (see BX, pp. 115 and example, pp. 116). This instruction sets the T bit if the bottom bit of the specified register was set, and switches

the PC to the address given in the remainder of the register.

Example_1:

MOV R0, #0x40

BX R0

Example_2:

MOV R0, #0x43

BX R0

Thumb exit

An explicit switch back to an ARM instruction stream can be caused byexecuting a Thumb BX instruction (see example, pp. 117).

An implicit return takes place whenever an exception is taken, since exceptionentry is always handled in ARM code.


5/22


Thumb Systems

A typical embedded system will include a small amount of fast 32-bitmemory on the same chip as the ARM core and will execute speed-criticalroutines (such as digital signal processing algorithms) in ARM code fromthis memory. The bulk of the code will not be speed-critical and mayexecute from a 16-bit off-chip ROM.


6/22


The Thumb Programmers Model

r0r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

SP (r13)

LR (r14)

PC (r15)

CPSR

Hi registers

Lo registers

shaded registers haverestricted access

The Thumb IS gives full access to the eight Lo general purpose registers r0 to r7,and makes extensive use of r13 to r15 for special purposes:

r13 is used as a stack pointer. r14 is used as the link register. r15 is the program counter (PC).

The remaining registers (r8 to r12 and CPSR) have only restricted access: A few instructions allow the Hi register (r8 to r15) to be specified. The CPSR condition code flags are set by arithmetic and logical operations and control

conditional branching.


7/22


Thumb-ARM similaritiesAll Thumb instructions are 16 bits long. They map onto ARM instructions sothey inherit many properties of the ARM instruction set: The load-store architecture. Support for 8-bit byte, 16-bit half-word and 32-bit word data types. A 32-bit unsegmented memory.

Thumb-ARM differencesIn order to achieve a 16-bit instruction length a number of characteristic

features of the ARM IS have been abandoned: Most Thumb instructions are executed unconditionally. (All ARM instructions are executed

conditionally.)

Many Thumb data processing instructions use a 2-address format. (the destination register isthe same as one of the source registers). (ARM data processing instructions, with theexception of the 64-bit multiplies, use a 3-address format.)

Thumb instruction formats are less regular than ARM instruction formats, as a result of thedense encoding.


8/22


Thumb Branch Instructions

8-bit offset

15 12 11 8 7 0

1 1 0 1 cond

11-bit offset

15 1110 0

1 1 1 0 0

11-bit offset

15 12 1110 0

1 1 1 1 H

Rm

15 8 7 6 5 3 2 0

0 1 0 0 0 1 1 1 H 0 0 0

(1) B

(2) B

(3) BL

(4) B{L}X RmL

10-bit offset

15 11 10 1 0

1 1 1 0 1 (3a) BLX 0

8-bit offset

15 12 11 8 7 0

1 1 0 1 cond

11-bit offset

15 1110 0

1 1 1 0 0

11-bit offset

15 12 1110 0

1 1 1 1 H

Rm

15 8 7 6 5 3 2 0

0 1 0 0 0 1 1 1 H 0 0 0

(1) B

(2) B

(3) BL

(4) B{L}X RmL

10-bit offset

15 11 10 1 0

1 1 1 0 1 (3a) BLX 0

The ARM instructions have a large (24-bit) offset field which clearly will not fit in a 16-bit instruction format. Therefore the Thumb instruction set includes various ways ofsubsetting the functionality.

Typical uses of branch instructions include:

Short conditional branches to control (for example) loop exit;

Medium-range unconditional branches to goto sections of code; Long-range subroutine calls.

ARM handles all these with the same instruction, typically wasting many bits of the24-bit offset in the first two cases. Thumb has to be more efficient, using differentformats for each of these cases.

Thumb target

Thumb target

Thumb target

ARM target

ARM or Thumb target


9/22


Thumb Software Interrupt Instruction

The instruction causes the following actions:

The address of the next Thumb instruction is saved in r14_svc. The CPSR is saved in SPSR_svc. The processor disables IRQ, clears the Thumb bit and enters supervisor mode by modifying

the relevant bits in the CPSR.

The PC is forced to address 0x08.

The ARM instruction SWI handler is then entered. The normal return instructionrestores the Thumb execution state.

Assembler format: SWI

The equivalent ARM instruction has an identical assembler syntax; the 8-bitimmediate is zero-extended to fill the 24-bit field in the ARM instruction.

8-bit immediate

15 8 7 0

1 1 0 1 1 1 1 1


10/22


Thumb Data Processing Instruction (1)

Thumb data processing instructions comprise a highly optimized set of fairly complexformats covering the operations most commonly required by a compiler.

Rd

15 10 9 8 6 5 3 2 0

0 0 0 1 1 0 A

Rd

15 10 9 8 6 5 3 2 0

0 0 0 1 1 1

#imm8

15 13 12 11 10 8 7 0

0 0 1 Op

Rn

15 13 12 11 10 6 5 3 2 0

0 0 0 Rd

(1) ADD| SUB Rd, Rn, Rm

(2) ADD| SUB Rd, Rn, #i mm3

(3) R d/ Rn , #i mm8

(4) LSL| LSR| ASR Rd, Rn, #shi f t

Op

15 10 9 6 5 3 2 0

0 1 0 0 0 0

Rd/Rn

15 10 9 8 7 6 5 3 2 0

0 1 0 0 0 1 M

(5) Rd/ Rn, Rm/ Rs

(6) ADD| CMP| MOV Rd/ Rn, Rm

RnRm

Rn#imm3A

Rd/Rn

Op #sh

Rm/Rs Rd/Rn

Rm

#imm8

15 12 11 10 8 7 0

1 0 1 0 R

15 8 7 6 0

1 0 1 1 0 0 0 0 A #imm7

(7) ADD Rd, SP| PC, #i mm8

(8) ADD| SUB SP, SP, #i mm7

Rd

DOp


11/22



Instructions that use the Lo, general-purpose register (r0-r7)

MOVS Rd, # ;MOV Rd, #MVNS Rd, Rm ;MVN Rd, Rm

CMP Rn, # ;CMP Rn, #CMP Rn, Rm ;CMP Rn, RmCMN Rn, Rm ;CMN Rn, Rm

TST Rn, Rm ;TST Rn, Rm

ADDS Rd, Rn, # ;ADD Rd, Rn, #ADDS Rd, Rd, # ;ADD Rd, Rd, #ADDS Rd, Rn, Rm ;ADD Rd, Rn, RmADCS Rd, Rn, Rm ;ADC Rd, Rm

SUBS Rd, Rn, # ;SUB Rd, Rn, #SUBS Rd, Rd, # ;SUB Rd, Rd, #SUBS Rd, Rn, Rm ;SUB Rd, Rn, Rm

SBCS Rd, Rn, Rm ;SBC Rd, RmRSBS Rd, Rn, #0 ;NEG Rd, Rn

ARM instruction Thumb instruction


12/22



Instructions that use the Lo, general-purpose register (r0-r7)

MOVS Rd, Rm, LSL # ;LSL Rd, Rm, #MOVS Rd, Rd, LSL Rs ;LSL Rd, RsMOVS Rd, Rm, LSR # ;LSR Rd, Rm, #MOVS Rd, Rd, LSR Rs ;LSR Rd, RsMOVS Rd, Rm, ASR # ;ASR Rd, Rm, #MOVS Rd, Rd, ASR Rs ;ASR Rd, RsMOVS Rd, Rd, ROR Rs ;ROR Rd, Rs

ANDS Rd, Rd, Rm ;AND Rd, Rm

EORS Rd, Rd, Rm ;EOR Rd, RmORRS Rd, Rd, Rm ;ORR Rd, RmBICS Rd, Rd, Rm ;BIC Rd, RmMULS Rd, Rd, Rm ;MUL Rd, Rm



13/22



Instructions that operate with or on the Hi registers (r8-r15), in some cases incombination with a Lo register;

ADD Rd, Rd, Rm ;ADD Rd, Rm(1/2 Hi regs)

CMP Rn, Rm ;CMP Rn, Rm(1/2 Hi regs)MOV Rd, Rm ;MOV Rd, Rm(1/2 Hi regs)ADD Rd, PC, # ;ADD Rd, PC, #ADD Rd, SP, # ;ADD Rd, SP, #ADD SP, SP, # ;ADD SP, SP, #SUB SP, SP, # ;SUB SP, SP, #

All the data processing instructions that operate with and on the Lo registers updatethe condition code bits (the S bit is set in the equivalent ARM instruction).

The instructions that operate with and on the Hi registers do not change thecondition code bits, with the exception of CMP which only changes the condition

codes. The instructions that are indicated above as requiring 1 or 2 Hi regs must have one

or both register operands specified in the Hi register area.

#imm3, #imm7 and #imm8 denote 3-, 7- and 8-bit immediate fields respectively. #shdenotes a 5-bit shift amount field.



14/22


Thumb Single Register Data Transfer Instructions (1)

These instructions are a carefully derived subset of the ARM single register transferinstructions, and have exactly the same semantics as the ARM equivalent.

In all cases the offset is scaled to size of the data type, so the range of the 5-bit offsetis 32 bytes in a load or store byte instruction, 64 bytes in a load or store half-wordinstruction and 128 bytes in a load or store word instruction.

Rd

15 13 12 11 10 6 5 3 2 0

0 1 1 B

Rd

15 12 11 10 6 5 3 2 0

1 0 0 0

Rd

15 12 11 9 8 6 5 3 2 0

0 1 0 1 Op

Rd

15 11 10 8 7 0

0 1 0 0 1 #off8

(1) LDR| STR{B} Rd, [ Rn, #of f 5]

(2) LDRH| STRH Rd, [ Rn, #of f 5]

(3) LDR| STR{S}{H| B} Rd, [ Rn, Rm]

(4) LDR Rd, [ PC, #of f 8]

L

15 12 11 10 8 7 0

1 0 0 1 (5) LDR| STR Rd, [ SP, #of f 8]

Rn#off5

Rn#off5L

Rn

Rd #off8

L

Rm


15/22




16/22




17/22


Thumb Multiple Register Data Transfer Instructions (1)

The block copy forms of the instruction use the LDMIA and STMIA addressingmodes. The base register may be any of the Lo register, and the register list mayinclude any subset of these registers but should not include the base register.

The stack forms use SP (r13) as the base register. In addition to the eight registers

which may be specified in the register list, the link register (LR, or r14) may beincluded in the PUSH instruction and PC (r15) may be included in the POP form.

reg list

15 12 11 10 8 7 0

1 1 0 0

reg list

15 10 9 8 7 0

1 0 1 1 1 1

(1) LDMI A| STMI A Rn! ,

(2) POP| PUSH {{, R}}

Rn

RL

L{}


18/22


Thumb Multiple Register Data Transfer Instructions (2)


19/22


Thumb Implementation

data in

instructionpipeline

immediate elds

B operand bus

data in from memory

mux

Thumbdecompressor

ARM instructiondecoder

mux

select high orlow half-word

select ARM orThumb stream

The Thumb instruction set can be incorporated into a 3-stage pipeline ARMprocessor macrocell with relatively minor changes. The 5-stage pipelineimplementations are trickier.

The biggest addition is the Thumb instruction decompressor in the instructionpipeline; this logic translates a Thumb instruction into its equivalent ARM instruction.


20/22


Thumb Instruction Mapping

The Thumb decompressor performs a static translation from the 16-bitThumb instruction into the equivalent 32-bit ARM instruction. This involves:

Performing look-up to translate the major and minor opcodes. Zero-extending the 3-bit register specifiers to 4-bit specifiers. Mapping other fields across as required.

ExampleThumb: ADD Rd, #imm8ARM: ADDS Rd, Rd, #imm8

The simplicity of the decompression logic is crucial to the efficiency of theThumb instruction set. There would be little merit in the Thumb architectureif it resulted in complex, slow and power-hungry decompression logic.


21/22


ExampleThumb: ADD Rd, #imm8ARM: ADDS Rd, Rd, #imm8

Since the only conditional Thumb instructions are branches, the condition always is used intranslating all other Thumb instructions.

Whether or not a Thumb data processing instruction should modify the condition codes in theCPSR is implicit in the Thumb opcode; this must be made explicit in the ARM instruction.

The Thumb 2-address format can always be mapped into the ARM 3-address format byreplicating a register specifier

#imm8

15 13 12 1110 8 7 0

0 0 1 10 Rd

1 1 1 0 0 0 0 0 0 0 #imm81 0 1 0 0 1 0 Rd 0 Rd

31 28 2726 25 24 21 20 19 1615 12 11 0

alwayscondition

zeroshift immediatevalue

destinationmajor opcode,

format 3: MOV/CMP/ ADD/ SUBwith immediate

and sourceregister

minor opcodedenoting ADD

& set CC


22/22


Thumb applications

Thumb Properties The Thumb code requires 70% of the space of the ARM code. The Thumb code uses 40% more instructions than the ARM code. With 32-bit memory, the ARM code is 40% faster than the Thumb code.

With 16-bit memory, the Thumb code is 45% faster than the ARM code. Thumb code uses 30% less external memory power than ARM code.

So where performance is all-important, a system should use 32-bit memory

and run ARM code. Where cost and power consumption are more important, a

16-bit memory system and Thumb code may be a better choice.

Thumb Systems

A high-end 32-bit ARM system may use Thumb code for certain non-criticalroutines to save power or memory requirements.

A low-end 16-bit system may have a small amount of on-chip 32-bit RAM forcritical routines running ARM code, but use off-chip Thumb code for all non-critical routines.

[lecture-07] the thumb instruction sets

Documents