lecture 11 exam review

7/29/2019 Lecture 11 Exam Review

1/24

EL 511 VLSI Design

1

EL 511

VLSI Design

Instructor:

Mazad S. Zaveri

Faculty Block 4, Room 4206

Email: [email protected]://intranet.daiict.ac.in/~mazad_zaveri/


2/24

EL 511 Intro. VLSI Design

2

Amdahls law Important in todays world of multi-core chips

According to Amdahls law, the performance increase (speed-up) is

limited by the sequential part of the code

Speed-up is S = 1/[ops +(opp /p)],where = ops the fraction of serial operations,

opp = the fraction of parallel operations,

p = number of parallel processors

Hence, as the number of parallel processors p increase, S becomesmore dependent on the serial portion of the data

i.e. S (1/ops), when p is very large

The improvement in terms of performance, by adding moreprocessors (operating in parallel) will gradually diminish

Economics - Law of diminishing returns


3/24

EL 511 VLSI Design

3

PN junction formation General functional form of the

electrostatic variables in a PN

junction (under equilibrium)

Electrostatic potential (V)

Built-in potential (Vbi)

Electric-Field

Charge density Where does the charge come

from? Static charge?

How to draw these plots

manually?

Look at their equations

dV

dx

= E1 1 1c v idE dE dE

q dx q dx q dx= = =E

0S

d

dx K

=E


4/24

EL 511 VLSI Design

4

Built-in Potential Built-in potential

Definition: Voltage drop that occurs across the depletion region under equilibrium

conditions

Its a function of the doping concentrations of P and N side both

Acts as an opposition to flow of carriers

2ln A D

bi

i

N NkTV

q n

=

( ) ( )1

bi i F F ip side n sideV E E E E

q = +

How much energy does an electron

need to travel from n-side to p-sideHow much energy does a hole need

to travel from p-side to n-side

( ) ln DF i n sidei

NE E kT n

= ( )ln Ai F p side

i

NE E kTn

=


5/24

EL 511 VLSI Design

5

Depletion width How to calculate depletion region

width?

We can separately calculate thedepletion regions on the n-side and p-

side Function of the doping concentrations,

the built-in potentials, and appliedvoltage

( )

1/ 2

02 S A Dbi A

A D

K N NW V V

q N N

+=

W

( )

1/ 2

02

( )

S An bi A

D A D

K Nx V V

q N N N

=

+

( )

1/ 2

0

2

( )D n S Dp bi A

A A A D

N x K Nx V VN q N N N

= = +

0SJ

K AC

W

=

Depletion capacitance


6/24

EL 511 VLSI Design

6

Depletion Width Depletion width is a function of

applied (external) voltage If applied voltage (VA>0)

Depletion width decreases Space charge decreases

Electric field (max value) decreases

Electro-static potential effectivelyreduces

If applied voltage (VA


7/24

EL 511 VLSI Design

7

Possible (Ideal) MS Contacts

Workfunction

relation

N-type

semiconductor

P-type

semiconductor

Rectifying Ohmic

Ohmic Rectifying

M S >

S M >


8/24

EL 511 VLSI Design

8

Metal-Semiconductor contacts Equations:

Depletion region

Electric field

Built-in potential

Workfunction of

semiconductor

( )

[ ]

1/ 2

0

/

/

0

2 1

1

2( )

2

S

bi A

D A

D A

S

bi M S

GS i Fp

GS Fn i

K

W V Vq N

qNW

K

Vq

EE E

EE E

=

=

=

= + +

= +

E


9/24

N-type substrate (or body) In P-channel MOSFET

Depending on the appliedgate-voltage MOS Cap could exhibit the

following conditions:

Flat band (VG = 0)

Accumulation (VG > 0) Depletion (VG < 0)

Onset of inversion (VG = VT)

Inversion (VG < VT)

VLSI systems work at 0 to +ve Volts. How do we give ve voltages to P-MOSFET?

MOS Capacitor with N-type substrate

- Under Various Bias Conditions

0VT

Applied Volt . VG

Inversion Depletion Accumulation

Onset of Inversion Flat band

(VG < 0)

(VG < 0)


10/24

N-type substrate: Flat band

When VG = 0 (No applied bias) Metal Fermi-level and substrate Fermi-level are aligned

No band bending

Assuming that the workfunction of metal and semiconductor are equal

(ideal condition) The characteristics of the substrate (concentration of electrons) is thesame everywhere (in the bulk and near the surface)

Block charge diagram

No generated charges

The substrate has many electrons (Even then, why is there no charge?)

Gate

Substrate

Oxide

VG

GND

Gate

Substrate

OxideSurface (Oxide-Semiconductor interface)

Bulk

Surface

Bulk


11/24

N-type substrate: Accumulation When VG>0

Relatively Metal Fermi-level goes down (relatively to substrate Fermi-level)

For simplicity, assume that substrate Fermi-level remains in a fixed position,because substrate is grounded.

Band bending will be such that (near the surface)

Ei moves away from the semiconductor Fermi-level The concentration of electrons increases at/near the surface as compared to

the bulk

Notice, oxide bands also bend, but with constant slope


Positive charge on the gate Leads to a negative charge (accumulation of electrons) near the surface

region in the semiconductor substrate

Gate

Substrate

Oxide

VG

GND

Gate

Substrate

OxideSurface (Oxide-Semiconductor interface)

Bulk


12/24

N-type substrate: Depletion When VT< VG


13/24

N-type substrate:

Onset of Inversion

Surface (Oxide-Semiconductor interface)

Bulk

Gate

Substrate

Oxide

Gate SubstrateOxide

Gate

Substrate

Oxide

VG

GND

Onset of channel

formation

When VG = VT (VG n(surface), and p(surface) < n(bulk)

When Ei(surface) - EF = EF - Ei(bulk), we have inversion of the surface

We have p(surface) = n(bulk), majority carriers at surface are now holes

Also, in other words, Ei(surface) - Ei(bulk) = 2[EF - Ei(bulk)], at inversion

Block charge diagram More -ve charge on the gate

Leads to a +ve charge (ionized donors in depletion region) near the surface

Depletion region width grows (max. at inversion)

Leads to increase in +ve charged holes at surface


14/24

N-type substrate: Strong Inversion

When VG

< VT

(VG

n(bulk)

Block charge diagram More -ve charge on the gate

Depletion region width assumed to be stuck at max. (i.e. same as that

during onset of inversion) Leads to increase in +ve charged holes at surface

Surface (Oxide-Semiconductor interface)

Bulk

Gate

Substrate

Oxide

Gate SubstrateOxide

Gate

Substrate

Oxide

VG

GND


15/24

Ei (surface)

Ei (bulk)

Equations (according to Pierrets book)

Numerical Examples Consider NA = 1018 cm-3

What is surface potential at inversion?

Consider ND = 1018 cm-3

What is surface potential at inversion?

Draw the approx. band diagram ?

[ ]

[ ]

1( ) ( )

1 ( ) ( )

ln

ln

2

S i i

F i F

AF

i

DF

i

S F

E bulk E surfaceq

E bulk E bulkq

NkT

q n

NkT

q n

=

=

=

=

= At the depletion to inversion transition point

P-type semiconductor

N-type semiconductor


16/24

Equations (from Pierret)

1/ 20

1/ 2

0max

0

2

2 2

SS

A

SF

A

A

S

KW

qN

KWqN

qNW

K

=

=

=E


17/24

MOS Cap: P-type substrate Similar in functioning to the n-type substrate MOS Cap

But the relation of applied gate voltage to the various exhibited MOSCap conditions are reversed

0 VT

Applied Vol t. VG

InversionDepletionAccumulation

Onset of InversionFlat band


18/24

P-type substrate: Flat Band Condition

When VG = 0 (No appliedbias)

Metal Fermi-level and substrate

Fermi-level are aligned No band bending

Assuming that the workfunction of

metal and semiconductor are equal

(ideal condition)

The characteristics of the substrate

(concentration of holes) is the same

everywhere (in the bulk and near the

surface) Block charge diagram

No generated charges

Surface

Bulk


19/24

P-type substrate: Accumulation

When VG


20/24

P-type substrate: Depletion

When VT> VG >0 Relatively

Metal Fermi-level goes down (relative to substrate EF)

Band bending will be such that Ei (surface) moves closer to EF The concentration of holes decreases at/near the

surface

How?

Holes near the surface are repelled (due to applied +vebias on gate); i.e. electron from bulk will be attracted, andwill fill up missing bonds (holes) at acceptor atoms

Hence, these acceptor atoms become -ve chargedionized acceptor atoms (fixed charges), and create adepletion region.


+ve charge on the gate

Leads to a -ve charge (ionized acceptors in depletionregion) near the surface


21/24

P-type substrate: Onset of Inversion and Inversion

When VG >= VT (VG = VT at Onset of Inversion) Relatively Metal Fermi-level continues to go down (relatively to substrate

EF)

Band continue to bend (same direction as VT> VG >0)

Ei (surface) crosses the EF level, and continues to move down Hole concentration continues to decrease near the surface

Electron concentration continues to increase near the surface When Ei(surface) = EF, we have p(surface) = n(surface) = ni When Ei(surface) < EF, we have n(surface) > p(surface), and

n(surface) < p(bulk)

When EF - Ei(surface) = Ei(bulk) - EF, we have inversion of thesurface

We have n(surface) = p(bulk), majority carriers at surface arenow electrons

Also, in other words, Ei(bulk) - Ei(surface) = 2[Ei(bulk)- EF], atinversion

Block charge diagram More +ve charge on the gate

Leads to a -ve charge (ionized acceptors in depletion region) nearthe surface

Depletion region width grows (assume max. at inversion)

Leads to increase in -ve charged electrons at surface


22/24

EL 511 VLSI Design

22

Ideal IV Characteristics NMOS

What is the meaning of this

plot? Vds DC sweep from 0 to 1.8V

Vgs DC (step) sweep

0.6, 0.9, 1.2, 1.5, 1.8

Where are linear andsaturation regions in the plot? Boundary condition

Vds >= Vgs-Vt

Can we approx verify thisgraph, with the givenequations?

Can we find the resistance ofthe transistor inlinear/resistive region from

this plot?

lecture 11 exam review

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