CSE 123: Computer NetworksAaron Schulman

Lecture 19:Router Design

Eample courtesy Mike Freedman

Lecture 19 Overview

! Finish up BGP relationships

! Router internalsu Bufferingu Scheduling

2CSE 123 – Lecture 19: Router Design

! Make up the “core” of the Internetu Has no upstream provider of its ownu Typically has a national or international backbone

! Top of the Internet hierarchy of ~10-20 ASesu E.g., AT&T, Level 3 (CenturyLink), NTT/Verio, Century Link

(formerly Qwest), Sprint, Verizonu Full peer-peer connections between tier-1 providers

Tier-1 Providers

3CSE 123 – Lecture 19: Router Design

The Internet Hierarchy

4

Page 15 - Labovitz SIGCOMM 2010

A New Internet Model

  Flatter and much more densely interconnected Internet   Disintermediation between content and “eyeball” networks   New commercial models between content, consumer and transit

Settlement Free

Pay for BW

Pay for access BW

Settlement free

Pay for BW

Pay for access BW

CSE 123 – Lecture 19: Router Design

! Interdomain-routingu Exchange reachability information (plus hints)u BGP is based on path vector routingu Local policy to decide which path to follow

! Traffic exchange policies are a big issue $$$u Complicated by lack of compelling economic model (who

creates value?) u Can have significant impact on performance

BGP Summary

5CSE 123 – Lecture 19: Router Design

What’s in a Router?! Physical components

u One or more input interfaces that receive packetsu One or more output interfaces that transmit packetsu A chassis (box + power) to hold it all

! Functionsu Forward packetsu Drop packets (congestion, security, QoS)u Delay packets (QoS)u Transform packets? (Encapsulation, Tunneling)

6CSE 123 – Lecture 19: Router Design

Router Functions1. Receive incoming packet from link input interface2. Lookup packet destination in forwarding table

(destination, output port(s))3. Validate checksum, decrement ttl, update checksum 4. Buffer packet in input queue

5. Send packet to output interface (interfaces?)6. Buffer packet in output queue7. Send packet to output interface link

7CSE 123 – Lecture 17: Router Design

Functional architecture Reservation/Admission

ControlRouting

Protocols

Routing Table

ClassificationRules

Firewall

PacketClassification Switching

ForwardingTable

OutputScheduling

Control Plane• Complex• Per-control action• May be slow

Data plane• Simple• Per-packet• Must be fast

8

Interconnect architecture! Input & output connected via switch fabric

! Kinds of switch fabricu Shared Memoryu Busu Crossbar

! How to deal with transientcontention?u Input queuingu Output queuing

Input OutputSwitch

9CSE 123 – Lecture 19: Router Design

First Generation Routers(mostly software)

CPU RouteTable Buffer

Memory

MAC

Line Card

Shared Bus(es)

MAC

Line Card

MAC

Line Card

Single CPU and shared memory;

All classification by main CPU

10CSE 123 – Lecture 19: Router Design

Second Generation Routers(hw caching fw table)

CPU RouteTable

MAC

Line Card

Shared Bus(es)

ForwardingCache

Buffers

MAC

Line Card

ForwardingCache

Buffers

MAC

Line Card

ForwardingCache

Buffers

Direct DMA oncache hit

Cache ofrecent routes

11CSE 123 – Lecture 19: Router Design

Third Generation Routers(improved hw shared bus)

MAC

Line Card

ForwardingTable

Buffers

CPU Card

RoutingTable

CPU

MAC

Line Card

ForwardingTable

Buffers

Switch FabricShared interconnect (frequently crossbar)

Centralized scheduler

Full forwarding table in line card

Fixed cells

12CSE 123 – Lecture 19: Router Design

Output queuing! Output interfaces buffer packets

! Prou Simple algorithmsu Single congestion point

! Conu N inputs may send to the same outputu Requires speedup of N

» Output ports must be N times faster than input ports

Input OutputSwitch

13CSE 123 – Lecture 19: Router Design

Input queuing! Input interfaces buffer packets

! Prou Single congestion pointu Simple to design algorithms

! Conu Must implement flow controlu Low utilization due to Head-of-Line (HoL) Blocking

Input OutputSwitch

14CSE 123 – Lecture 19: Router Design

Head-of-Line Blocking

15CSE 123 – Lecture 19: Router Design

IQ + Virtual Output Queuing! Input interfaces buffer packets

in per-output virtual queues

! Prou Solves blocking problem

! Conu More resources per portu Complex arbiter at switchu Still limited by input/output

contention (scheduler)

Input OutputSwitch

16CSE 123 – Lecture 19: Router Design

17

Virtual Output Queues

CSE 123 – Lecture 17: Router Design

Switch scheduling! Problem

u Match inputs and outputsu Resolve contentions, no packet dropsu Maximize throughputu Do it in constant time…

! If traffic is uniformly distributed its easyu Lots of algorithms (approximate matching)

! Seminal result (Dai et al, 2000)u Maximal size matching + speedup of two guarantees

100% utilization for most traffic assumptions

18CSE 123 – Lecture 19: Router Design

For Next Time

! Read P&D 6.2

! Get started on Project 3!

19CSE 123 – Lecture 19: Router Design