lecture 2-5 logic families
TRANSCRIPT
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Integrated Electronics
Lecture-2-5Digital IC design Technologies
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Digital Logic Circuit Families
CMOS Bipolar BICMOS e!s
Complementar"
MOS
#seedo
$MOS
#ass Transistor
Logic#MOS
$MOS
TTL %CL &TL DTL I2L
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Operational Characteristic o'
Digital ICs Logic Le(el $oise Immunit"
$oise Margin #ropagation Dela"
Fan In)Fan out
#o*er Dissipation
Dela" #o*er #roduct
Silicon !rea +
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Logic Le(els 'or CMOS
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$oise Immunit"
The ailit" o' an apparatus or s"stem to
per'orm its 'unctions *hen inter'erence
.noise/ is present0
The higher the le(el o' noise at *hich the
euipment maintains its operating ailit"3 the
higher its noise immunit"0
In order to not e''ected " noise3 a logic circuit
must ha(e the certain amount o' noise
immunit"04
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$oise Immunit"
%''ect o' input noise o' gate operation
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$oise Margin
! measure o' a circuit noise immunit" is called
the noise margin3 *hich is e7pressed in (olts0
There are t*o (alues o' noise margin speci'ied'or the gi(en logic circuit8 the 9I9-le(el noise
margin .:$9/ and the LO;-le(el noise margin
.:$L/0
q :$9 < :O9.min/ = :I9.min/
q :$L < :IL.ma7/ = :OL.ma7/
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$oise Margin
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#ropagation Dela"
#ropagation dela"3 is the time reuired 'or a digital
signal to tra(el 'rom the input.s/ o' a logic gate to the
output0
I' the output o' a logic gate is connected to a long
trace or used to dri(e man" other gates.high fanout/
the propagation dela" increases sustantiall"0
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#ropagation Dela"
There are t*o propagation dela" time
speci'ied 'or logic gates0
1/ t#9L8 #ropagation Dela" Time 'rom 9I9 to LO;0
2/ t#L98 #ropagation Dela" Time 'rom LO; to 9I9
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Fan In ) Fan Out
Fan-inis the numer o' inputs a gate can handle0
The 'an-in de'ined as the ma7imum numer o' inputs
that a logic gate can accept0
I' numer o' input e7ceeds3 the output *ill e
unde'ined or incorrect0 It is speci'ied "
manu'acturer and is pro(ided in the data sheet0
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Fan-In ) Fan-Out
The 'an-out is de'ined as the ma7imum numer o'
inputs .load/ that can e connected to the output o'
a gate *ithout degrading the normal operation0
Fan Out is calculated 'rom the amount o' currenta(ailale in the output o' a gate and the amount o'
current needed in each input o' the connecting gate0
It is speci'ied " manu'acturer and is pro(ided in the
data sheet0
%7ceeding the speci'ied ma7imum load ma" cause a
mal'unction ecause the circuit *ill not e ale
suppl" the demanded po*er0 15
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Fan-In ) Fan-Out
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#o*er Dissipation
!s po*er is de'ined as the rate o' energ"trans'er3 @po*er dissipation@ is a measure o'
the rate at *hich energ" is dissipated3 or lost3
'rom an electrical s"stem0
! logic gate dra*s current 'rom the dc suppl"
(oltage source indicated in ne7t slide 'igure0
;hen the gate is in the 9I9 output state3 anamount o' current designated " ICC9 is
dra*n3 and in the LO; output state3 a
di''erent amount o' current ICCL is dra*n1
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#o*er Dissipation
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#o*er Dissipation
%7ample8 I' ICC9 is speci'ied as 105m! *hen
:CC is 5: and i' the gate is in a static
.nonchanging/ 9I9 output state3 the po*er
dissipation .#D/ o' the gate is
#D < :CCAICC9 < .5:/ A .105 m!/ < 05 m;
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#o*er Dissipation
;hen a gate is pulsed3 its output s*itches
ac and 'orth et*een 9I9 and LO;3 and
the amount o' suppl" current (aries et*een
ICC9 and ICCL0
The a(erage po*er dissipation depends on the
dut" c"cle and is usuall" speci'ied 'or a dut"
c"cle o' 5?0
;hen the dut" c"cle is 5? the output is 9I9
hal' the time and LO; the other hal'0 The
a(era e su l current is there'ore2?
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#o*er Dissipation
The a(erage suppl" current is there'ore
The a(erage po*er dissipation is
#D < :CCAICC9
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Dela" #o*er #roduct
In digital electronics3 the po*er=dela"
product is a 'igure o' merit correlated *ith the
energ" e''icienc" o' a logic gate or logic 'amil"0
!lso no*n as s*itching energ"3 it is the
product o' po*er consumption .a(eraged o(er
a s*itching e(ent/ times the input=output
dela"3 or duration o' the s*itching e(ent0
It has the dimension o' energ"3 and measures
the energ" consumed per s*itching e(ent02+
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Dela" #o*er #roduct
So3 an ideal digital technolog" *ould ha(e
(er" small propagation dela" tp3 and (er"
smallpo*er dissipation #D0
But3 there is a prolem0 Designing a'asterE
.e0g03 lo*er tp/ digital gate usuall" reuiresgreater power0 !nd designing a gate to
minimie po*er consumption usuall" slows
down the digital de(ice0 2,
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Dela" #o*er #roduct
The merit o' comparing logic-circuit
technologies .or 'amilies/ is the dela" po*er
product de'ined as
D# < #D tp
;here #D is the po*er dissipation o' the gate0
$ote that D# has the units o' Goules0
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Silicon !rea
The design o' digital :LSI circuits is the
minimiation o' silicon area per logic gate0
Smaller area reuirement enales the'arication o' a larger numer o' gates per chip0
Area reduction occurs in three different ways:
10 Through ad(ances in processing technolog"that enales the reduction o' the minimum
de(ice sie
20 Through ad(ances in circuit design techniues024
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%nd o' Lecture-2-5
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