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Lecture 27
ANNOUNCEMENTSR l ffi h ill d M d 12/10• Regular office hours will end on Monday 12/10• Special office hours will be posted on the EE105 website
• Final Exam Review Session: Friday 12/14 3PM HP AuditoriumFinal Exam Review Session: Friday 12/14, 3PM, HP Auditorium– Video will be posted online by Monday 12/17
• Final Exam:– Thursday 12/20, 12:30PM‐3:30PM, 277 Cory– Closed book; 6 pages of notes only
h– Comprehensive in coverage:• Material of MT#1 and MT#2, plus MOSFET amplifiers, MOSFET current sources, BJT and MOSFET differential amplifiers, feedback.
EE105 Fall 2007 Lecture 27, Slide 1 Prof. Liu, UC Berkeley
• Qualitative questions on state‐of‐the‐art device technology
Outline
• IC technology advancementIC technology advancementQ: How did we get here?
• Modern BJT technologyQ: What is an HBT?
• Modern MOSFET technologyQ: What are the challenges (and potential solutions) for continued MOSFET scaling?
EE105 Fall 2007 Lecture 27, Slide 2 Prof. Liu, UC Berkeley
The IC Market• The semiconductor industry is approaching $300B/yr in sales
Military
Communications24%
Military2%
Computers42%
Transportation Cons mer Electronics
Industrial8%
EE105 Fall 2007 Lecture 27, Slide 3 Prof. Liu, UC Berkeley
Transportation 8%
Consumer Electronics16%
Courtesy of Dr. Bill Flounders, UC Berkeley Microlab
IC Technology Advancement
Improvements in IC performance and cost have been enabled by the steady miniaturization of the transistorenabled by the steady miniaturization of the transistor
International Technology Transistor Scaling
Better Performance/Cost100
m)
Roadmap for Semiconductors
Investment
SMIC’s Fab 4 (Beijing, China)Photo by L.R. Huang, DigiTimes
Market Growth 10
LEN
GTH
(n
PITCH
2000 2005 2010 2015 20201
GAT
E LOW POWER HIGH PERFORMANCE
YEAR: 2004 2007 2010 2013 2016
EE105 Fall 2007 Lecture 27, Slide 4 Prof. Liu, UC Berkeley
YEARHALF-PITCH: 90nm 65nm 45nm 32nm 22nm
The Nanometer Size ScaleMOSFET
Carbon nanotube
EE105 Fall 2007 Lecture 27, Slide 5 Prof. Liu, UC Berkeley
Nanogap DNA Detector
Prof. Luke Lee, BioEngineering Dept., g g phttp://www-biopoems.berkeley.edu/
Double-stranded DNASingle-stranded DNA
Polysilicon
Poly-SiPoly-SiPoly-SiPoly-Si
EE105 Fall 2007 Lecture 27, Slide 6 Prof. Liu, UC Berkeley
Insulator (Insulator (Si3N4) Insulator (Insulator (Si3N4)
IC Fabrication• Goal: Mass fabrication (i.e. simultaneous fabrication) of many
IC “chips” on each wafer each containing millions or billions ofIC chips on each wafer, each containing millions or billions of transistors
• Approach: Form thin films of semiconductors, metals, and insulators over an entire wafer, and pattern each layer with a process much like printing (lithography).
Planar processing consists of a sequence of additive and subtractive steps with lateral patterning
oxidationdeposition
ion implantation
etching lithography
EE105 Fall 2007 Lecture 27, Slide 7 Prof. Liu, UC Berkeley
p
Planar Processing(patented by Fairchild Semiconductor in 1959: J A Hoerni US Patent 3 064 167)
• DEPOSITION of a thin film
(patented by Fairchild Semiconductor in 1959: J. A. Hoerni, US Patent 3,064,167)
• LITHOGRAPHY– Coat with a protective layer– Selectively expose the protective layer– Develop the protective layer– Develop the protective layer
• ETCH to selectively remove the thin film
EE105 Fall 2007 Lecture 27, Slide 8 Prof. Liu, UC Berkeley• Strip (etch) the protective layer
Courtesy of Dr. Bill Flounders, UC Berkeley Microlab
Overview of IC Process Steps
E it
Test
EpitaxyBare SiliconWafer
ProcessedWafer
Deposition/growthAnneal
Mask PatternCMP
Ion Implantation
Mask Pattern Generation
CD SEMMetrology
DefectDetection
EE105 Fall 2007 Lecture 27, Slide 9 Prof. Liu, UC Berkeley
Etch Lithography
Courtesy of Dr. Bill Flounders, UC Berkeley Microlab
Modern BJT StructureB E C
p+ p+ P baseN collector
N+ polySi
N+ Shallowtrench
P+polySiP+polySi
F
N+ subcollector
P− substrate
Deeptrench
Deep trench
Features:• Narrow base • n+ poly‐Si emitterS lf li d l Si b t t• Self‐aligned p+ poly‐Si base contacts
• Lightly‐doped collector• Heavily‐doped epitaxial subcollector• Shallow trenches and deep trenches filled with SiO for electrical isolation
EE105 Fall 2007 Lecture 27, Slide 10 Prof. Liu, UC Berkeley
• Shallow trenches and deep trenches filled with SiO2 for electrical isolation
BJT Performance Parameters• Common emitter current gain, β :
DA 2 ⎞⎛
BBiEE
EEiBB
iEEE
BB
iBBE
B
C
WNnDWNnD
nDqAWN
nDqA
II
2
2
2
2
=⎞
⎜⎜⎛
⎟⎟⎠
⎞⎜⎜⎝
⎛
=≡β
• The cutoff frequency, fT, is the frequency at which β falls to 1.
EE
i
WN ⎠⎜⎜⎝
It is correlated with the maximum frequency of oscillation, fmax.
• Intrinsic gainT
A
C
A
T
Com V
VIV
VIrg =⋅≈
EE105 Fall 2007 Lecture 27, Slide 11 Prof. Liu, UC Berkeley
Heterojunction Bipolar Transistor (HBT)
• To improve β , we can increase niB by using a base material (Si1 Ge ) that has a smaller band gap energy(Si1‐xGex) that has a smaller band gap energy
• for x = 0.2, Eg of Si1‐xGex is 0.1eV smaller than for Si
⎞⎜⎜⎛ − Eg2
⎠⎜⎜⎝
∝kT
n gi exp2
EEiBB WNnD 2
=β
• Note that this allows a large β to be achieved with large NB(even >N ) which is advantageous for
BBiEE WNnD 2β
(even >NE), which is advantageous for
• increasing Early voltage (VA)
• reducing base resistance
EE105 Fall 2007 Lecture 27, Slide 12 Prof. Liu, UC Berkeley
g
Modern MOSFET Structures(Intel Penryn© from www semiconductor com)(Intel Penryn©, from www.semiconductor.com)
N-channel MOSFETs P-channel MOSFETs
• 45nm CMOS technology features:– High‐permittivity gate dielectric and metal gate electrodes
strained channel regions
EE105 Fall 2007 Lecture 27, Slide 13 Prof. Liu, UC Berkeley
– strained channel regions– shallow trench isolation
MOSFET Performance Parameters
• Transconductance (short‐channel MOSFET):I
– The average carrier velocity v is dependent on the velocity
THGS
Doxm VV
IvWCg−
==
The average carrier velocity v is dependent on the velocity at which carriers are “injected” from the source into the channel, which is dependent on the carrier mobility
• The cutoff frequency of a MOSFET is given byGS
mT C
gf =π2
• Intrinsic gain: )(11D
om VVIVVIrg =⋅=
λλ
GS
EE105 Fall 2007 Lecture 27, Slide 14 Prof. Liu, UC Berkeley
)( THGSDTHGS VVIVV −− λλ
MOSFET Scaling Challenges• Suppression of short‐channel effects
Gain in I is incommensurate with L scaling GateGate
MOSFET:Lg
Tox
– Gain in ION is incommensurate with Lg scaling
• Variability in performanceSubstrate
Source Drain
Substrate
Source DrainLeff Nsub
Xj
Variability in performance
– Sub‐wavelength lithography:(Costly resolution‐enhancement
Design
Mask
250nm250nm 180nm180nm
OPCOPC
90nm and Below90nm and Below
PSM
0°
180°
PSMPSM
0°
180°
0°
180°
techniques are needed)
– Random variations:• Photoresist line‐edge roughness
Wafer
180°180°180°
OPC0°
180°OPCOPCOPC
0°
180°
Photoresist line edge roughness
photoresist SiO2 Gate
S D i
EE105 Fall 2007 Lecture 27, Slide 15 Prof. Liu, UC Berkeley
• Statistical dopant fluctuationsA. Brown et al., IEEE Trans. Nanotechnology, p. 195, 2002
Source Drain
“VTH Roll‐Off”• |VTH| decreases with Lg
– Effect is exacerbated by
M. Okuno et al., 2005 IEDM p. 52
Effect is exacerbated by
high values of |VDS|
• Qualitative explanation:Q p
– The source & drain p‐n junctions assist in depleting the Si underneath the gate. The smaller the Lg, the greater the percentage of charge balanced by the S/D p n junctions:balanced by the S/D p‐n junctions:
Large Lg: S Dn+n+
VG
xj
EE105 Fall 2007 Lecture 27, Slide 16 Prof. Liu, UC Berkeley
Small Lg: DSp depletion region
j
Why New Transistor Structures?
• DIBL must be suppressed to scale down Lg• Leakage occurs in region far from channel surface
Let’s get rid of it! Lg
G tGate
DrainSource
GateThin-BodyMOSFET Source Drain
Gate
“Silicon-on-I l t ” Buried Oxide
Substrate
Insulator” (SOI)Wafer
EE105 Fall 2007 Lecture 27, Slide 17 Prof. Liu, UC Berkeley
Thin‐Body MOSFETs
• Leakage is suppressed by using a thin body (TSi < Lg)Ch l d i i t d d hi h i bilit– Channel doping is not needed higher carrier mobility
• Double‐gate structure is more scalable (to Lg<10nm)
Ultra-Thin Body (UTB)L
Double-Gate (DG)
Gate
Lg
S D i
Gate
Buried Oxide
Source Drain TSiGate
Source Drain TSi
EE105 Fall 2007 Lecture 27, Slide 18 Prof. Liu, UC Berkeley
Substrate
Double‐Gate “FinFET”
Planar DG-FET FinFET
Gate
Lg
D. Hisamoto et al. (UC Berkeley),IEDM T h i l Di t 1032
DrainGate
Lg
Source Drain
Gate
TSi
IEDM Technical Digest, pp. 1032-1034, 1998
N. Lindert et al. (UC Berkeley), IEEE Electron Device Letters, pp. 487 489 2001
Source
Gate
Fin Width = TSi
Fin Height HFIN = W/2
487-489, 2001
GATEDRAIN
20 nm
10 nmY.-K. Choi et al. (UC Berkeley), IEDMTechnical Digest, pp. 421-424, 200115nm Lg FinFET:
EE105 Fall 2007 Lecture 27, Slide 19 Prof. Liu, UC Berkeley
SOURCE
15 nm Lg FinFETsY K Choi et al (UC Berkeley) IEDM Technical Digest pp 421 424 2001
TSi = 10 nm; Tox = 2.1 nm
Y.-K. Choi et al. (UC Berkeley), IEDM Technical Digest, pp. 421-424, 2001
10-2 10-2
P+Si0.4Ge0.6Vd=-1.0 V Vd=1.0 V
um] 600 600
|V V|=1 2V NMOSPMOS
/um
]Transfer Characteristics Output Characteristics
10-6
10-4
10-6
10-4Gate
Vd=-0.05 V
d
Vd=0.05 V
nt, I
d [A
/u
300
400
500
300
400
500
Voltage step: 0.2V
|Vg-Vt|=1.2VPMOS
t, I d[u
A/
10-10
10-8
10-10
10-8N-body=2x1018cm-3
n C
urre
n
100
200
300
100
200
300: 0.2V
Cur
ren
-1.0 -0.5 0.0 0.5 1.0 1.5 2.010-12 10-12
NMOSPMOS
Dra
in
Gate Voltage V [V]-1.5 -1.0 -0.5 0.0 0.5 1.0 1.50
100
0
100D
rain
Drain Voltage V [V]
EE105 Fall 2007 Lecture 27, Slide 20 Prof. Liu, UC Berkeley
Gate Voltage, Vg [V] Drain Voltage, Vd [V]
10 nm Lg FinFETsB Yu et al (AMD & UC Berkeley) IEDM Technical Digest pp 251 254 2002B. Yu et al. (AMD & UC Berkeley), IEDM Technical Digest, pp. 251-254, 2002
DrainGate
220Å
NiSi
Poly-SiSource
SiO2 cap
Lg=10nmSi Fi
BOX
Si Fin
EE105 Fall 2007 Lecture 27, Slide 21 Prof. Liu, UC Berkeley
MOSFET Scaling Scenario
t lli t
• Advanced structures will enable Si MOSFET scaling to Lg <10 nm
high-κ gate dielectric
metallic gate
Lg (nm): 50 40 30 20 10G
S D
Si classical
strained Si
forward body biasingal
multi-gateG
S DSi
G
forward body biasing
EE105 Fall 2007 Lecture 27, Slide 22 Prof. Liu, UC Berkeley
G
The End is Not the Limit !Innovations in process technology, materials, and device design will
t i th Si l ti
Technology, Device & CircuitInnovations,
Heterogeneous Integrationsustain the Si revolution
Lower Power,Lower CostInvestment
UbiC ( 1 t )R PCs (1 person/computer)Mainframes (>1 persons per computer)
Information technologyMarket GrowthAcknowledgement:
Mark Weiser
UbiComp (>1 computers per person)
ALE
S($
)/Y
Information technology will befor better quality-of-lifepervasiveembeddedhuman-centered
today
SA
TIMEEnvironmentpervasive
embeddedhuman-centeredhuman centeredsolving societal-scale problems
Healthcare Disaster response
EnergySensatex
human centered
EE105 Fall 2007 Lecture 27, Slide 23 Prof. Liu, UC BerkeleyPhilips Transportation
EECS 105 in the Grand Scheme • Example electronic system: cell phone
EE105 Fall 2007 Lecture 27, Slide 24 Prof. Liu, UC Berkeley