lecture 3: iii-v cmos 1 - lunds tekniska högskola · border traps (kim apl 2010, yu yuan edl 2011,...
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1Nanoelectronics: Materials Integration 1
Lecture 3: III-V CMOS 1
Contents:
High-k Dielectrics on III-Vs: W Wang et al Microelectronic Engineering 88, 2011, p 1061 ”Is interfacial chemistry....”
2
ALD critical for III-V MOS structures
Alternative cycles of metal and oxide
Has self cleaning effect
Reaction at interface detected by XPS
Nanoelectronics: Materials Integration 1
3
Correlation between XPS and CV
Nanoelectronics: Materials Integration 1
4
The Bad Guys
5
Defects in high-k/In0.53Ga0.47As systems
+ +
+ +
+ +
+ +
M O S
Ec
EV
Interface traps in bandgap
Border traps (Kim APL 2010, Yu Yuan EDL 2011, Lin IEDM 2012, Brammertz TED 2011, Ramon APL 2013, …)
Bulk fixed charges (Shin APL 2010, Long JES 2011, Djara TED 2012, …)
Interface traps in CB (Taoka IEDM 2011)
Electrically Active Defects in the InGaAs MOS system
In0.53Ga0.47As
+ ++
-
Nanoelectronics: Materials Integration 1
6
Interface States DIT Fixed Charges Nox e/h Border Traps
+ ++ + + + +
Semico
nd
ucto
rO
xide
Dra
in C
urr
en
t
Gate voltage
SS Degradation
Dra
in C
urr
en
t
Gate voltage
VT Shift Hysteresis
Gate VoltageD
rain
Cu
rren
t
Effect of charged defects states in MOS structure
Nanoelectronics: Materials Integration 1
-4 -3 -2 -1 0 1 2
0.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009 [c]
Gate Bias (V)
Al2O
3/InGaAs
Transfer time
3 minutes
Cmin
DitInversion
Gate Stack Progress (Dit) : 2008 to 2017
7
Ni / 8nm Al2O3 on n- In0.53Ga0.47As/n+InP
Full DIT responseoutside CV window
Dit (Ei) > 4x1013 cm-2eV-1
Low DIT : CV < -2V Dominated by inversion response
Dit (Ei) 8x1011 cm-2eV-1
2008 [1] 2017 [3]2011 [2]
DIT responsein the CV window
Dit (Ei) 2x1013 cm-2eV-1
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009
Cap
acitance (
F/m
2)
Gate Bias (V)
transfer time
30 minutes
Al2O
3/InGaAs
Cmin
[a]
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.50.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009 [b]
Gate Bias (V)
transfer time
7 minutes
Al2O
3/InGaAs
Cmin
Dit
Dit
[1] Typical CV response from 2008-2010 see for example: R. D. Long, et al., J. Electrochem. Soc., 158 (5) G103-G107 (2011), [2] É. O’Connor, et al., Journal ofApplied Physics, 109, 024101 (2011), [3] É. O’Connor, et al., Appl. Phys. Lett. 110, 032902 (2017)
Nanoelectronics: Materials Integration 1
CV for InAs Nanowires
J. Wu et al., IEEE T-ED 2016
Vertical Nanowire Capacitors, Tgrowth 420 C
Doped bottom segment, Sputtered W
ALD @ 250/100C EOT 1.5 nm
Low Parasitic Capacitance
Good CV Modulation
Interpretation of the CV Data
Data interpreted with a combined model
with interface traps and border traps
Similar Nbt to planar InAs references
Lower Dit than planar InAs references
Nanoelectronics: Materials Integration 1
Low Dit on InAs Nanowires
J. Wu et al., IEEE T-ED 2015
Vertical Nanowire Capacitors
ALD @ 250C EOT 1.7 nm
Low Parasitic Capacitance
Good CV Modulation
Low Dit on InAs Nanowires
J. Wu et al., Nano Lett. 2016
Has an InAs nanowire less traps?
WZ crystal structure, larger Eg
WZ crystal structure, more stable facets
Nanowire geometry, less volume for
minority generation
Low-Frequency CV Fitting
Low Dit (<1012 ev-1cm-2) around Ec
InAs-GaSb Nanowire Growth
- Au seeds of different diameter patterned on Si/InAs
wafers using EBL.
- InAs-GaSb nanowires grown using MOVPE.
- Gibbs-Thomson effect
Vapor pressure of Sb in Au increases with dAu
and when equal to that of gas phase, material
transport to NW is inhibited.
- GaSb growth is suppressed for sufficiently small dAu.
γa : surface energy of Au seed
Ωa: molar volume of Au seed
α: utilization factor of TMSb
pTMSb: precursor pressure
x: Sb fraction in seed
p*v: saturation vapor press
J. Svensson et al., Nano Letters 2015
Nanoelectronics: Materials Integration 1
InAs-GaSb Nanowire Growth
• Length of InAs and GaSb have opposite
dependence on dAu.
• Diameter of GaSb larger than InAs since
Sb enhances group III solubility in Au.
• Distance between two types of wires down
to 200 nm.
Nanoelectronics: Materials Integration 1
p and n-MOSFET layout
- Tuning dAu and pitch enables
equal length of InAs and
InAs/GaSb NWs.
- Doping profiles enable n.i.d.
channel and good contacts.
Nanoelectronics: Materials Integration 1
Device and Circuit Fabrication
1. High-k dep
2. InAs mesa (a)
3. Organic bottom spacer
4. W gate deposition
5. Gate length definition
5. Gate patterning (b)
6. Organic top spacer
7. Via holes (c)
8. Ni/Au drain deposition and patterning (d)
Vin
InAs
nMOS
Vin
Vin
Vdd
Vout
GND
GND GND GND
GND
InAs/
GaSb
pMOS
InAs/
GaSb
pMOS
InAs
nMOS
MOSFET Characteristics
Sample A (1 nm doped GaSb shell):
InAs Ion = 44 µA/µm (Vdd=0.5V), SS = 525 mV/dec
GaSb Ion = 7 µA/µm (Vdd=0.5V), SS = 300 mV/dec
Sample B (shell removed by digital etch):
InAs Ion = 0.1 µA/µm (Vdd=0.5V), SS = 180 mV/dec, Ion/Ioff = 103
GaSb Ion = 0.1 µA/µm (Vdd=0.5V), SS = 180 mV/dec, Ion/Ioff = 104
Nanoelectronics: Materials Integration 1
Vertial III-V Inverter on Si
- Gain = 2 V/V (at Vdd = 0.5 V).
- Frequency response limited
to 1 kHz due to parasitics.
- Can be improved by EBL
patterned gate/drain
electrodes and a self-aligned
gate process.
Vout
Vin
Vdd
GND
GND
GND
GND
InAs
nMOS
InAs/GaSb
pMOS
Nanoelectronics: Materials Integration 1
Vertical NAND Gate on Si
- Two p-MOSFETs in parallell and
two n-MOSFETs in series.
VoutVinA
VddGND
InAs
nMOS
InAs/GaSb
pMOS
VinB
Nanoelectronics: Materials Integration 1