lecture 3: transistor as an thermonic switch · lecture 3: transistor as an thermonic switch...

Lecture 3: Transistor as an thermonic switch

2016-01-21 1Lecture 3, High Speed Devices 2016

Lecture 3: Transistors as an thermionic switch


Reading Guide: 54-57 in Jena

Transistor metrics

• Reservoir – equilibrium

• Thermionic switch – basics of transistor operation

• FET/Bipolar Transistor

• FET – Short channel effects

N-type Field Effect Transistor – Large Signal DC


+Vgs

Ids=f(Vgs,Vds)

IDS

IDS

Gate

Source

Drain+VDS

N-type Field Effect Transistor – Metrics


VGS VGS

I D (m

A/µ

m)

VDS= VDS=

g m(m

S/µ

m)

Output Characteristics Transfer Characteristics Transconductance

VT – Threshold voltage

𝑅𝑜𝑛 = 𝑑𝐼

𝑑𝑉𝐷𝑆

−1

𝑉𝐷𝑆→0𝑉

𝑔𝑑 = 𝑑𝐼𝐷𝑑𝑉𝐷𝑆 𝑉𝐷𝑆,𝑉𝐺𝑆

VT – when the current becomes ‘small’

𝑔𝑚 = 𝑑𝐼𝐷𝑑𝑉𝐺𝑆 𝑉𝐷𝑆,𝑉𝐺𝑆

(mS/µm)

(mS/µm)

(Wµm)

Output conductance

On-resistancece

A good FET has:Low RON, low gd, large gm, VT>0V and a large BVDS

Voltage gain requires gm>gd

gd

Ron

BVDS

N-type Field Effect Transistor – Metrics (off-state)


VGS VGS

I D (m

A/µ

m)

VDS=0.8VVDS=0.8V

Log

(ID)

Output Characteristics Transfer Characteristics Transconductance

VT – Threshold voltageBVDS

VDS=50 mV

VDS=50 mV

ID below VT :Sub threshold current

Ideal inverse subthreshold slope: 𝑘𝑇

𝑞log10(𝑒) ≈ 60 𝑚𝑉/𝑑𝑒𝑐𝑎𝑑𝑒

Drain Induced barrier lowering DIBL (mV/V)

SS

A FET for digital applications has:SS ~60mV/decadeSmall DIBL (10-40mV/V)

Npn Bipolar transistor – Large Signal DC


VBE

Ids=f(VBE,VCE)

IC

IE=IC+IB

Base

Emitter

Collector

IB

Npn Bipolar transistor – Metrics


𝑔𝑚 =𝐼𝐶𝑉𝑡

Collector current density: JC (mA/µm2) Current gain: 𝛽𝐹 =𝛿𝐼𝐶

𝛿𝐼𝐵

Output conductance:gd (mS/µm2) A good HBT has:Very low gd, large JC, large bF

large BVDS

Voltage gain requires gm>gd

gm follows from IC:

HBTs are rarely operated at low VDS

-> Ron usually not important.

Ohmic contact - Reservoir


Metal n++ semiconductor

+VS

Ideal ohmiccontact

• The applied bias sets the metal fermi level with respect to ground. (Electric potential <-> )

• An ideal ohmic contact keeps the semiconductor in (Gibbs) equilibrium with the metal <-> Equal EF

• The n++ doping keeps the semiconductor bands

flat for moderate current densities (𝑑𝐸𝑓

𝑑𝑥=

𝐽

𝜇𝑛𝑛)

Lightly doped semiconductor

Reservoir for electrons

EC

Ev

EF

n+ - i – n+ Resistor: ballistic current


n++

+0 V


n++

kx

E

EF,L EF,R

If no scattering – electrons flowing from left to right have positive kx

electrons flowing from right to left have negative kx

No current flows: +kx and -kx are equally occupied!

𝑣𝑋 =ℏ𝑘𝑥

𝑚∗

Positive current: kx>0Negative current: kx<0

n+ - i – n+ Resistor: ballistic current


n++

+VD


n++

qVD

kx

E

An applied bias lowers the drain reservoir by qVD

+kx is populated by EF,L. –kx is populated by EF,R.

EF,L

EF,R

𝐸𝐹,𝑅 = 𝐸𝐹,𝐿 − 𝑞𝑉𝐷

This leads to a net electron current from left to right

𝑣𝑋 =ℏ𝑘𝑥

𝑚∗

Positive current: kx>0Negative current: kx<0

General Transistor Model


VDS

n++ Channel/Base n++

SourceEmitter

DrainCollector

VCE

Ideal transistor the potential energy of the channel is only controlled by the gate/base terminal.HBT – direct control of EC,channel

FET – indirect control of EC,channel

VGS

VBE

EF,LEF,R

EC

General Transistor Model


EC

EC

EC EC EC

VGS=0.4VVDS=0V

VGS=0.4VVDS=0.1V

VGS=0.4VVDS=0.4V

VGS=0.6VVDS=0.4V

VGS=0.1VVDS=0.4V

Bipolar Transistor Realization


n++ p+ n++

VBE

The base is a p+ regionThe base terminal is connected directly to the base

This constitutes a reservoir for holes – not for electrons

VCE

EC

VBE

+VCE

VBE

JEJC𝑛 − 𝑛0

𝜏

• No e-field• Diffusion with recombination• Recombination: base current

VCE

QW

Field Effect Transistors - realization


p

+VGS

+VDS

n++ n++

Insulator

Small Bandgap (i)

+VGS

+VDS

Wide Bandgap

Wide Bandgap/insulator

+VGS

n++ n++

Insulator/WB

n++ n++

QW / Nanowire

+VGS

n++ n++

Insulator/WB

Insulator/WB

+VGS

+VDS

+VDS

Traditional Si-MOSFET

Traditional HEMT

Quantum Well HEMT /SOI MOSFET/ Graphene FET…

FinFET / Nanowire FET / Carbon Nanotube FET

Field Effect Transistors – indirect channel potential control


Positive VGS NegativeVGS

Positive VGS

NegativeVGS

y

x

y x



𝐽𝑑𝑟𝑖𝑓𝑡 = 𝑞𝜇𝑛𝑛 𝑥 𝜀 𝑥 = −𝜇𝑛𝑛 𝑥𝑑𝐸𝑐

𝑑𝑥

Long channel FET diffusive: potential drop along the channel required.

Channel potential not 100% controlled by the gate – complicates things. n(x) decreases -> pinch off.

Field Effect Transistors – subthreshold current


𝐹𝑗

𝐸𝐹 − 𝐸1

𝑘𝑇≈ 𝑒(𝐸𝐹−𝐸1)/𝑘𝑇

When E1 >> EF,L

• Exponential tail of Fermi-Dirac function:

• Current decreases exponentially with increasing E1

• This gives ideally a 60 mV / decade slope

• Theoretical limit for a thermionic switch

• 105 on-off ratio: at least 0.3 VGS

E1

EFL



Ballistic FET diffusive: No potential drop along the channel is requiredIdeal gate control sets the potential in the channelSource/Drain electrodes injects electrons

Short channel effects – large a drain potential can pull down E1 – output conductance

Field Effect Transistors – Short Channel Effects


1) We want the channel potential to be set by the gate voltage.

2) When the current through the transistor is small – very little charge inside the channel. 𝜌 ≈ 0 𝐶/𝑚2. (For simplicity here)

𝛻 ⋅ 𝜖𝑟𝜖0𝛻V = 03D Possionequation

3) Both drain, source and gate terminal can influence the potential inside the channel!

4) This is studied by solution to the 2D Possion Equation.

VS VD

VG

𝛻 ⋅ 𝜖𝑟𝜖0𝛻V = 0

Analogue: Thermal Conduction


t1

02

2

2

2

y

T

x

Tl2

l1

y

x

• The linear differential equation for the steady statetemperature field is equivalent to Possions equation!

• We want the temperature (potential) in the channel to be controlled by the temperature (potential) on the gate electrode and NOT by the drain electrode!

• This makes it very easy to intuivitely understand how to design an transistor!

t2

T=0 ◦C

T=-25 ◦C

T=+25 ◦C

T=0 ◦C

𝛻 ⋅ 𝜆𝛻𝑇 = 0

Thermal Conduction:

𝛻 ⋅ 𝜖𝑟𝜖0𝛻V = 0

Possion Equation:

Temperature <-> Voltage

Thermal Conductivity <-> Dielectric Constants

1 minute intuition- geometry


t1

t2

T=0 ◦C

T=+25 ◦C

T=-25 ◦C

t1

t2

T=0 ◦C

T=+25 ◦C

T=-25 ◦C

t1

t2

T=+25 ◦C

T=-25 ◦C

(a)(c)

(b)

Rank the structures in terms ofhighest temperature at

1 minute intuition- thermal conductivity


T=0 ◦C

T=+25 ◦C

T=-25 ◦C(b)

l: thermal conductivity

Rank the structures in terms ofhighest temperature at

T=0 ◦C

T=+25 ◦C

T=-25 ◦C(a)

T=0 ◦C

T=+25 ◦C

(c)

l = small

l = small

l = small

l = large

l = large

l = small

Laplace’s Equation is linear


0V

-0.5V

0.5V 0V 0V

-0.5V

0V 0.5V

0V

Φ 𝑥, 𝑦 = 𝛼𝐺(𝑥, 𝑦)𝑉𝐺+𝛼𝐷(𝑥, 𝑦)𝑉𝐷 + 𝛼𝑆(𝑥, 𝑦)𝑉𝑆The potential at a certain point:

𝜕2

𝜕𝑥2+

𝜕2

𝜕𝑦2𝛼Φ = 𝛼

𝜕2

𝜕𝑥2+

𝜕2

𝜕𝑦2Φ = 0

0< 𝛼𝐺, 𝐷, 𝑆< 1 x,y dependence from solution of Laplace’s equation

Potential Distribution


l l

V=-0.5

Potential Distribution – Ground plane FET


Ground Plane

V=0 V=0.0

V=-0.5

V=0.0

Potential Distribution – Double gate FET


V=-0.5

V=-0.5

V=0 V=0

Potential Distribution – Double gate FET


VS VD ts

ti

ti

𝜆 ≈ 𝑡𝑠 + 2𝑡𝑖 If eri=ers

𝑉 𝑥 ≈ −𝑉𝐺𝑆 + 𝑉𝐺𝑆 sinh𝜋 𝐿 − 𝑥

𝜆/ sinh

𝜋𝐿

𝜆+ (𝑉𝐷𝑆 + 𝑉𝐺𝑆) sinh

𝜋 𝐿 − 𝑥

𝜆/ sinh

𝜋𝐿

𝜆

𝜆 ≈ 𝑡𝑠

𝛻 ⋅ 𝜖𝑟𝜖0𝛻V = 0

This can be solved easily with e.g. COMSOL.

Analytical solution through separation of variables + Fourier series expansion.

Analytic solution:

If eri>>ers

Geometric Length Scale for the FET

Short Channel Effects


L=50 nml=10 nm

L=30 nml=10 nm

L=20 nml=10 nm

𝜆 ≈ 𝑡𝑠 + 2𝑡𝑖 L > 2l

Short gate lengths requires thin oxide and thin semiconductors

𝜆𝐺𝐴𝐴 < 𝜆𝐷𝐺 < 𝜆𝑆𝐺

Double Gate

Single Gate Gate All Around

FinFETs/Nanowire: thicker ti/ts for the same gate length

lecture 3: transistor as an thermonic switch · lecture 3: transistor as an thermonic switch...

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