lecture 8: sequential networks and finite state machines cse 140: components and design techniques...
TRANSCRIPT
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Lecture 8:
Sequential Networks and Finite State Machines
CSE 140: Components and Design Techniques for Digital Systems
Fall 2014
CK Cheng
Dept. of Computer Science and Engineering
University of California, San Diego
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Combinational
CLK CLK
A B C D
Sequential Networks
1. Components F-Fs2. Specification3. Implementation: Excitation Table
S(t)X
Y
CLK
RTL: Register-Transfer Level Description
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Specification
• Combinational Logic– Truth Table– Boolean Expression– Logic Diagram (No feedback loops)
• Sequential Networks: State Diagram (Memory)– State Table and Excitation Table– Characteristic Expression – Logic Diagram (FFs and feedback loops)
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Specification: Finite State Machine
• Input Output Relation• State Diagram (Transition of States)• State Table• Excitation Table (Truth table of FF inputs)• Boolean Expression• Logic Diagram
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Specification: Examples
• Transition from circuit to finite state machine representation– Netlist => State Table => State Diagram =>
Input Output Relation
• Example 1: a circuit with D Flip Flops• Example 2: a circuit with other Flip Flops
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Building Sequential Circuits and describing their behavior
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What we will learn:
1. Given a sequential circuit, describe its behavior over time2. Given the behavior of a sequential circuit, implement the circuit
Sequential Circuit: Wall-E How does Wall-E behave?
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What does it mean to describe the behavior of a sequential circuit
Specify how the output of the circuit changes as a function of inputs and the state of the circuit
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State: What is it? Why do we need it?
Free running 2 bit Counter
Symbol/ CircuitBehavior over time
time
CLK
Q0
Q1
What is the expected output of the counter over time?
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State: What is it ? Why do we need it?
Symbol/ Circuit Behavior over time
time
CLK
2 bit Counter
PI Q: At time t1, what information is needed to produce the output of the counter at the next rising edge of the clock (i.e t2)?
A. All the outputs of the counter until t1
B. The initial output of the counter at time t=0C. The output of the counter at current time t1
D. We cannot determine the output of the counter at t2 prior to t2
t1 t2
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Finite State Machines: Describing circuit behavior over time
2 bit Counter
Symbol/ CircuitDiagram that depicts behavior over time
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State Diagrams: Describing circuit behavior over time
State diagram of the 2 bit counter
S0
S1
S2
S3
PI Q: What information is not explicitly indicated in the state diagram?
A. The input to the circuitB. The output of the circuitC. The time when state transitions
occurD. The current state of the circuit.E. The next state of the circuit.
Finite State Machine
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Implementing the 2 bit counter
S0
S1
S2
S3
State Diagram
State Table
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
Current state Next State
S0 S1
S1 S2
S2 S3
S3 S0
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Implementing the 2 bit counter
S0
S1
S2
S3
State Diagram
State Table
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
Current state Next State
S0 S1
S1 S2
S2 S3
S3 S0
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Implementing the 2 bit counter
State Table
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
PI Q: To obtain the outputs Q0(t+1) and Q1(t+1) from the inputs Q1(t) and Q0(t) we need to use:
A. Combinational logicB. Some other logic
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Implementing the 2 bit counter
State Table
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
Q0(t)
Q1(t)
Q0(t+1)
Q1(t+1)
PI Q: What is wrong with the 2-bit counter implementation shown above
A. The combinational circuit is incorrectB. The circuit state changes correctly but continuously rather than at the rising
edge of the clock signalC. The output of the circuit is unreliable because inputs can get corrupted
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Implementing the 2 bit counter
State Table
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
0 0 0 1
0 1 1 0
1 0 1 1
1 1 0 0
We store the current state using D-flip flops so that:• The inputs to the combinational circuit don’t change while the next output is
being computed• The transition to the next state only occurs at the rising edge of the clock
Q0(t)
Q1(t)
DQ
Q’
DQ
Q’
CLK
Implementation of 2-bit counter
Q0(t+1) = Q0(t)’Q1(t+1) = Q0(t) Q1(t)’ + Q0(t)’ Q1(t)
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Generalized Model of Sequential Circuits
S(t)X
Y
CLK
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Modified 2 bit counter
Q0(t)
Q1(t)
DQ
Q’
DQ
Q’
CLK
x(t)
Q0(t)
Q1(t) y(t)
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Modified 2 bit counter
Q0(t)
Q1(t)
DQ
Q’
DQ
Q’
CLK
x(t)
Q0(t)
Q1(t) y(t)
Characteristic Expression:y(t) = Q0(t+1) = Q1(t+1) =
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Modified 2 bit counter
Q0(t)
Q1(t)
DQ
Q’
DQ
Q’
CLK
x(t)
Q0(t)
Q1(t)
y(t)
y(t) = Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)’ Q0(t)’Q1(t+1) = D1(t) = x(t)’(Q0(t)⊕Q1(t))
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State table
0 0 0 11 01 1
PSinput
x=0 x=1
Q1(t) Q0(t) | (Q1(t+1) Q0(t+1), y(t))Present State | Next State, Output
S0
S1
S2
S3
PSinput
x=0 x=1
Netlist State Table State Diagram Input Output Relation
State Assignment
Characteristic Expression:
y(t) = Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)’ Q0(t)’Q1(t+1) = D1(t) = x(t)’(Q0(t)⊕Q1(t))
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State table
0 0 0 11 01 1
PSinput
x=0 x=1
01, 0 00, 010, 0 00, 011, 0 00, 000, 1 00, 1
Q1(t) Q0(t) | Q1(t+1) Q0(t+1), y(t)Present State | Next State, Output
S0
S1
S2
S3
PSinput
x=0 x=1
S1, 0 S0, 0S2, 0 S0, 0S3, 0 S0, 0S0, 1 S0, 1
Let:S0 = 00S1 = 01S2 = 10S3 = 11
Remake the state table using symbols instead of binary code , e.g. ’00’
Netlist State Table State Diagram Input Output Relation
State Assignment
y(t) = Q1(t)Q0(t)Q0(t+1) = D0(t) = x(t)’ Q0(t)’Q1(t+1) = D1(t) = x(t)’(Q0(t) + Q1(t))
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Netlist State Table State Diagram Input Output Relation
Given inputs and initial state, derive output sequence
S1 S2 S3S0
Time 0 1 2 3 4 5
Input 0 1 0 0 0 -
State S0
Output
S0
S1
S2
S3
PSinput
x=0 x=1
S1, 0 S0, 0S2, 0 S0, 0S3, 0 S0, 0S0, 1 S0, 1
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Netlist State Table State Diagram Input Output Relation
Example: Given inputs and initial state, derive output sequence
x/y
S1 S2 S3S00/0 0/00/0
1/0
1/0
Time 0 1 2 3 4 5
Input 0 1 0 0 0 -
State S0 S1 S0 S1 S2 S3
Output 0 0 0 0 0 1
(0 or 1)/1
S0
S1
S2
S3
PSinput
x=0 x=1
S1, 0 S0, 0S2, 0 S0, 0S3, 0 S0, 0S0, 1 S0, 1
1/0
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Let’s implement our free running 2-bit counter using T-flip flops
S0
S1
S2
S3
PS Next state
S1 S2 S3 S0
State Table
S0
S1
S2
S3
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Let’s implement our free running 2-bit counter using T-flip flops
S0
S1
S2
S3
S1 S2 S3 S0
State Table
S0
S1
S2
S3
State Table with AssignedEncoding
0 0 0 11 01 1
Current
01101100
Next
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Let’s implement our free running 2-bit counter using T-flip flops
id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1)
0 0 0 0 1
1 0 1 1 0
2 1 0 1 1
3 1 1 0 0
Excitation table
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Let’s implement our free running 2-bit counter using T-flip flops
id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1)
0 0 0 0 1 0 1
1 0 1 1 1 1 0
2 1 0 0 1 1 1
3 1 1 1 1 0 0
Excitation table
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Let’s implement our free running 2-bit counter using T-flip flops
id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1)
0 0 0 0 1 0 1
1 0 1 1 1 1 0
2 1 0 0 1 1 1
3 1 1 1 1 0 0
Excitation table
T0(t) = T1(t) =
Q0(t+1) = T0(t) Q’0(t)+T’0(t)Q0(t)Q1(t+1) = T1(t) Q’1(t)+T’1(t)Q1(t)
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Let’s implement our free running 2-bit counter using T-flip flops
id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1)
0 0 0 0 1 0 1
1 0 1 1 1 1 0
2 1 0 0 1 1 1
3 1 1 1 1 0 0
Excitation table
T0(t) = 1 T1(t) = Q0(t)
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TQ
Q’
TQ
Q’
Q0
Q1
1
T1
Free running counter with T flip flops
T0(t) = 1 T1(t) = Q0(t)
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y(t) = Q1(t)Q0(t)T0(t) = x(t) Q1(t)T1(t) = x(t) + Q0(t)
X
TQ
Q’
TQ
Q’
y
Q0
Q1
T0
T1
Example 3 Circuit with T Flip-Flops
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Logic Diagram => Excitation Table => State Table
y(t) = Q1(t)Q0(t)T0(t) = x(t) Q1(t)T1(t) = x(t) + Q0(t)Q0(t+1) = T0(t) Q’0(t)+T’0(t)Q0(t)Q1(t+1) = T1(t) Q’1(t)+T’1(t)Q1(t)
id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y
0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0 0
2 0 1 0 1 0 1 1 0
3 0 1 1 1 0 1 1 0
4 1 0 0 0 0 1 0 0
5 1 0 1 1 1 0 1 0
6 1 1 0 1 0 0 1 1
7 1 1 1 1 1 0 0 1
Excitation Table:Truth table of the F-F inputs
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Excitation Table: iClicker
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In excitation table, the inputs of the flip flops are used to produceA.The present stateB.The next state
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id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y
0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0 0
2 0 1 0 1 0 1 1 0
3 0 1 1 1 0 1 1 0
4 1 0 0 0 0 1 0 0
5 1 0 1 1 1 0 1 0
6 1 1 0 1 0 0 1 1
7 1 1 1 1 1 0 0 1
Excitation Table =>State Table => State Diagram
PS\Input X=0 X=1
S0
S1
S2
S3
State AssignmentS0 00S1 01S2 10S3 11
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id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y
0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0 0
2 0 1 0 1 0 1 1 0
3 0 1 1 1 0 1 1 0
4 1 0 0 0 0 1 0 0
5 1 0 1 1 1 0 1 0
6 1 1 0 1 0 0 1 1
7 1 1 1 1 1 0 0 1
Excitation Table =>State Table => State Diagram
S0 S1 S3
S2
PS\Input X=0 X=1
S0 S0,0 S2,0
S1 S3,0 S3,0
S2 S2,0 S1,0
S3 S1,1 S0,1
State AssignmentS0 00S1 01S2 10S3 11
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id Q1(t) Q0(t) x T1(t) T0(t) Q1(t+1) Q0(t+1) y
0 0 0 0 0 0 0 0 0
1 0 0 1 1 0 1 0 0
2 0 1 0 1 0 1 1 0
3 0 1 1 1 0 1 1 0
4 1 0 0 0 0 1 0 0
5 1 0 1 1 1 0 1 0
6 1 1 0 1 0 0 1 1
7 1 1 1 1 1 0 0 1
Excitation Table =>State Table => State Diagram
0/0
S0 S1 S3
S2
0/0
1/1
0/1
0, 1/01/0
1/0
PS\Input X=0 X=1
S0 S0,0 S2,0
S1 S3,0 S3,0
S2 S2,0 S1,0
S3 S1,1 S0,1
State AssignmentS0 00S1 01S2 10S3 11
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Netlist State Table State Diagram Input Output Relation
0/0
S0 S1 S3
S2
0/0
1/1
0/1
0, 1/01/0
1/0
PS\Input X=0 X=1
S0 S0,0 S2,0
S1 S3,0 S3,0
S2 S2,0 S1,0
S3 S1,0 S0,1
Time 0 1 2 3 4 5
Input 0 1 1 0 1 -
State S0
Output
Example: Output sequence
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Netlist State Table State Diagram Input Output Relation
0/0
S0 S1 S3
S2
0/0
1/1
0/1
0, 1/01/0
1/0
PS\Input X=0 X=1
S0 S0,0 S2,0
S1 S3,0 S3,0
S2 S2,0 S1,0
S3 S1,0 S0,1
Time 0 1 2 3 4 5
Input 0 1 1 0 1 -
State S0 S0 S2 S1 S3 S0
Output 0 0 0 0 1 0
Example: Output sequence
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Implementation
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State Diagram => State Table => Logic Diagram
• Canonical Form: Mealy and Moore Machines• Excitation Table
• Truth Table of the F-F Inputs• Boolean algebra, K-maps for combinational
logic• Examples• Timing
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Canonical Form: Mealy and Moore Machines
Combinational Logic
x(t) y(t)
CLK
C2
C1
y(t)
CLK
x(t)
C1 C2
CLK
x(t)
y(t)
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Mealy Machine: yi(t) = fi(X(t), S(t))Moore Machine: yi(t) = fi(S(t))
si(t+1) = gi(X(t), S(t))
C1 C2
CLK
x(t)
y(t)
Mealy Machine
C1 C2
CLK
x(t) y(t)
Moore Machine
S(t) S(t)
Canonical Form: Mealy and Moore Machines
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Implementation: State Diagram => State Table => Netlist
Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.
Assign mapping a:0, b:1
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Implementation: State Diagram => State Table => Netlist
Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.
Assign mapping a:0, b:1
PI Q How many states should the pattern recognizer haveA. One because it has one outputB. One because it has one inputC. Two because the input can be one of two states (a or b)D. Three because . .. . . . .E. Four because . . . . .
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PI Q: How many states should the pattern recognizer haveA. One because it has one outputB. One because it has one inputC. Two because the input can be one of two states (a or b)D. Three because . .. . . . .E. Four because . . . . .
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Implementation: State Diagram => State Table => Netlist
Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = aab, the output y(t) = 1, otherwise y(t) = 0.
S1S0a/0
b/0
a/0
b/1
S2a/0
b/0
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State Diagram => State Table with State Assignment
State AssignmentS0: 00S1: 01S2: 10
PS\x a b
S0 S1,0 S0,0
S1 S2,0 S0,0
S2 S2,0 S0,1
PS\x 0 1
00 01,0 00,0
01 10,0 00,0
10 10,0 00,1
Q1(t+1)Q0(t+1), ya: 0b: 1
S1S0a/0
b/0
a/0
b/1
S2a/0
b/0
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Example 2: State Diagram => State Table => Excitation Table => Netlist
PS\x 0 1
00 01,0 00,0
01 10,0 00,0
10 10,0 00,1
id Q1Q0x D1D0 y
0 000 01 0
1 001 00 0
2 010 10 0
3 011 00 0
4 100 10 0
5 101 00 1
6 110 -- -
7 111 -- -
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0 2 6 4
1 3 7 5
x(t)
Q1
0 1 - 1
0 0 - 0
Q0D1(t):
D1(t) = x’Q0 + x’Q1
D0 (t)= Q’1Q’0 x’y= Q1x
id Q1Q0x D1D0 y
0 000 01 0
1 001 00 0
2 010 10 0
3 011 00 0
4 100 10 0
5 101 00 1
6 110 -- -
7 111 -- -
Example 2: State Diagram => State Table => Excitation Table => Netlist
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DQ
Q’
DQ
Q’
Q1
Q0
D1
D0
Q0
Q1
x’
D1(t) = x’Q0 + x’Q1
D0 (t)= Q’1Q’0 x’y= Q1x
x
y
Q’1
Q’0x’
Example 2: State Diagram => State Table => Excitation Table => Netlist
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DQ
Q’
DQ
Q’
Q1
Q0
D1
D0
Q0
Q1
x’
x
y
Q’1
Q’0x’
Example 3: State Diagram => State Table => Excitation Table => Netlist
S1S0 a/0b/0
a/0
b/1
S2a/0
b/0
iClicker: The relation between the above state diagram and sequential circuit.A. One to one.B. One to manyC. Many to oneD. Many to manyE. None of the above
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Finite State Machine Example
• Traffic light controller– Traffic sensors: TA, TB (TRUE when there’s traffic)
– Lights: LA, LB
TA
LA
TA
LB
TB
TB
LA
LB
Academic Ave.B
rava
do
Blv
d.
Dorms
Fields
DiningHall
Labs
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FSM Black Box
• Inputs: CLK, Reset, TA, TB
• Outputs: LA, LB
TA
TB
LA
LB
CLK
Reset
TrafficLight
Controller
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FSM State Transition Diagram• Moore FSM: outputs labeled in each state• States: Circles• Transitions: Arcs
S0LA: greenLB: red
Reset
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FSM State Transition Diagram• Moore FSM: outputs labeled in each state• States: Circles• Transitions: Arcs
S0LA: greenLB: red
S1LA: yellowLB: red
S3LA: redLB: yellow
S2LA: redLB: green
TATA
TB
TB
Reset
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FSM State Transition Table
PS Inputs NSTA TB
S0 0 X S1
S0 1 X S0
S1 X X S2
S2 X 0 S3
S2 X 1 S2
S3 X X S0
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State Transition TablePS Inputs NS
Q1(t) Q0(t) TA TB Q1(t +1) Q0(t +1)
0 0 0 X 0 1
0 0 1 X 0 0
0 1 X X 1 0
1 0 X 0 1 1
1 0 X 1 1 0
1 1 X X 0 0
State Encoding
S0 00
S1 01
S2 10
S3 11
Q1(t+1)= Q1(t)xor Q0(t)
Q0(t+1)= Q’1(t)Q’0(t)T’A + Q1(t)Q’0(t)T’B
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FSM Output TablePS Outputs
Q1 Q0 LA1 LA0 LB1 LB0
0 0 0 0 1 0
0 1 0 1 1 0
1 0 1 0 0 0
1 1 1 0 0 1
Output Encoding
green 00
yellow 01
red 10
LA1 = Q1
LA0 = Q’1Q0
LB1 = Q’1
LB0 = Q1Q0
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FSM Schematic: State Register
S1
S0
S'1
S'0
CLK
state register
Reset
r
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Logic Diagram
S1
S0
S'1
S'0
CLK
next state logic state register
Reset
TA
TB
inputs
S1 S0
r
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FSM Schematic: Output Logic
S1
S0
S'1
S'0
CLK
next state logic output logicstate register
Reset
LA1
LB1
LB0
LA0
TA
TB
inputs outputs
S1 S0
r