lecture sct2 – process integration
TRANSCRIPT
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Lecture SCT2 – Process Integration
12. Web-based virtual Lecture: July 08 2021Prof. Dr. Johann W. Bartha
Inst. f. Halbleiter und MikrosystemtechnikTechnische Universität Dresden
Summer Semester 2021
Start lecture here
“SCT_SS21_12.1“ 37:08
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The hyperlinks to the video streams in this virtual lecture are marked by the Video Campus Sachsen Logo. To watch them you need to be logged on at the host: VCS. Please click on: https://videocampus.sachsen.de/loginselect TU-Dresden in the selection mask and than logon with the same ID and password as you use for OPAL or ZIH. Stay logged on as long as you work with the lecture slides.
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This document including the contained video streams is only
available to students of the lecture „Semiconductor Technology 2“
at TU-Dresden. It must not be copied and published
outside of TUD! It is intended for
TUD internal use only!L12
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Lecture evaluation open until July 08!
Please participate in the lecture evaluation!
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Outline
http://www.computerhistory.org/siliconengine/timeline/
0. Introduction/ Lab organization/DMA /SCT1/Motivation1. Process integration
1.MOS Structure, MOS Capacitor2.Structure of a MOSFET3.I/V behavior
2. Circuits in Metal-Gate FET Technology1.Process sequence of N-MOSFET in Metal Gate2.From inverter to memory cell3.SRAM in NMOS Metal Gate4.The threshold voltage of the MOSFET
1.Parasitic FET2.Enhancement/Depletion Transistor3.N-MOS Logic by E/D Transitors4.Process sequence of the N-MOS E/D Process
3. Self aligned Process1.Metal Gate -> Si Gate2. Channel-Stop & LOCOS Technology
1.Example: Process flow of E/D SiGate LOCOS Inverter 2.LOCOS Variation3.Shallow Trench Isolation
3.Lightly doped drain4.SALICIDE5. Self Aligned Contacts (SAC)6. Resist trimming
4.Transition to CMOS Technology1.MOS Transistor Types2.CMOS Inverter
1.Consideration NMOS E/D Inverter2.Comparison CMOS Inverter
3.CMOS Process flow (Example CMOS 180 nm process)5. Further Considerations
1.Scaling1. Challenges2.Material Equivalent Scaling3.Further Concepts
SC-Basics
Review: - SCT Basics- MOS-Cap-CV- MOS-FET (N-FET enh.)- Al-Gate FET- SRAM product (E/E) - VT adjust => Depl.- E/D Logic- Self aligned process
Si-Gate, LOCOS, STI, LDD, SALICIDE, SAC, Resist Trimming
Today: CMOS
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Outline
http://www.computerhistory.org/siliconengine/timeline/
0. Introduction/ Lab organization/DMA /SCT1/Motivation1. Process integration
1.MOS Structure, MOS Capacitor2.Structure of a MOSFET3.I/V behavior
2. Circuits in Metal-Gate FET Technology1.Process sequence of N-MOSFET in Metal Gate2.From inverter to memory cell3.SRAM in NMOS Metal Gate4.The threshold voltage of the MOSFET
1.Parasitic FET2.Enhancement/Depletion Transistor3.N-MOS Logic by E/D Transitors4.Process sequence of the N-MOS E/D Process
3. Self aligned Process1.Metal Gate -> Si Gate2. Channel-Stop & LOCOS Technology
1.Example: Process flow of E/D SiGate LOCOS Inverter 2.LOCOS Variation3.Shallow Trench Isolation
3.Lightly doped drain4.SALICIDE5. Self Aligned Contacts (SAC)6. Resist trimming
4.Transition to CMOS Technology1.MOS Transistor Types2.CMOS Inverter
1.Consideration NMOS E/D Inverter2.Comparison CMOS Inverter
3.CMOS Process flow (Example CMOS 180 nm process)5. Further Considerations
1.Scaling1. Challenges2.Material Equivalent Scaling3.Further Concepts
SC-Basics
Review: - SCT Basics- MOS-Cap-CV- MOS-FET (N-FET enh.)- Al-Gate FET- SRAM product (E/E) - VT adjust => Depl.- E/D Logic- Self aligned process
Si-Gate, LOCOS, STI, LDD, SALICIDE, SAC, Resist Trimming
Today: CMOS
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Continue “SCT_SS20_12.2“ 21:00
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Blackboard 12.1
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4. Transition to CMOS Technology
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4.1 Different Types of MOSFET
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4.2 Transition to the CMOS inverter 4.2.1 Remember: E/E inverter
Remember the N-MOS Inverter!
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4.2 Transition to the CMOS inverter 4.2.1 Remember: E/E inverter
Remember the N-MOS Inverter!
When Vi is increased from zero to VD, acurrent flows through the load transistor for Vi > VT and reaches a saturation value controlled by the load transistor.
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4.2 Transition to the CMOS inverter 4.2.1 Remember: E/E inverter
Remember the N-MOS Inverter!
When the input is high, the inverter consumes continuously power!
When Vi is increased from zero to VD, acurrent flows through the load transistor for Vi > VT and reaches a saturation value controlled by the load transistor.
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4.2.2. Hydrodynamic analogy: CMOS Inverter
Instead of the load device it would be much nicer to have a switching devicethat operates complementary!
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4.2.2. Hydrodynamic analogy: CMOS Inverter
Instead of the load device it would be much nicer to have a switching devicethat operates complementary! Like the two valves controlled by the piston.
Operation state 1
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4.2.2. Hydrodynamic analogy: CMOS Inverter
Instead of the load device it would be much nicer to have a switching devicethat operates complementary! Like the two valves controlled by the piston.
Operation state 1 Operation state 2
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4.2.2. Hydrodynamic analogy: CMOS Inverter
Instead of the load device it would be much nicer to have a switching devicethat operates complementary!
Something like this can be done by combining a N-MOS and a P-MOS FET:
Like the two valves controlled by the piston.Operation state 1 Operation state 2
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Process - integration
Application example:Ring Oscillator
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Process - integration
Application example:Ring Oscillator
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Process - integration
Application example:Ring Oscillator
Multiple stage ring oscillator can be nicely used to determine the switching speed of a circuit technology. The more stages the more easy to measure.
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Application example: Ring Oscillator
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Application example: Ring Oscillator
Feeding back last output to first input:
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Does this circuit oscillate ?
Application example: Ring Oscillator
Feeding back last output to first input:
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Does this circuit oscillate ?
No! Last output and first input are both on high. No reason to change the state!
Application example: Ring Oscillator
Feeding back last output to first input:
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And now?
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Odd number of inverters required!
And now?
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Back to realization of an inverter with an active load by using N-MOS and P-MOS FET
Odd number of inverters required!
And now?
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Back to realization of an inverter with an active load by using N-MOS and P-MOS FET
Odd number of inverters required!
And now?
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Continue“SCT_SS20_12.03” 31:01
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Functioning of the CMOS Inverter
Remember the N-MOS characteristic.
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Functioning of the CMOS Inverter
Remember the N-MOS characteristic.
Remember the P-MOS characteristic.
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Functioning of the CMOS Inverter
Remember the N-MOS characteristic.
Remember the P-MOS characteristic.
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Functioning of the CMOS Inverter
Remember the N-MOS characteristic.
Remember the P-MOS characteristic. Let’s turn the transistor aroundand plot IS instead of ID.
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Functioning of the CMOS Inverter
Remember the N-MOS characteristic.
Remember the P-MOS characteristic.
Now we shift each terminal by VD!
Let’s turn the transistor aroundand plot IS instead of ID.
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Functioning of the CMOS Inverter
Remember the N-MOS characteristic.
Remember the P-MOS characteristic.
Now we shift each terminal by VD!
Let’s turn the transistor aroundand plot IS instead of ID.
We assemble this to the CMOS inverter:
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Process - integrationPerfect transfer curve
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Process - integration
Transfer curve: ☺ Very steep☺ Vo max = VD, Vo min = 0☺ Static power consumption = 0
Perfect transfer curve
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Process - integration
Higher process complexity necessary!
Transfer curve: ☺ Very steep☺ Vo max = VD, Vo min = 0☺ Static power consumption = 0
Perfect transfer curve
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VDS = -VDD … 0
VGS =
-VDD … 0
VDS = 0 …+VDD
VGS =
0 …+VDD
CMOS Concept discovered by IDS=f(VDS)
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VDS = -VDD … 0
VGS =
-VDD … 0
VDS = 0 …+VDD
VGS =
0 …+VDD
VGS =
-VDD … 0
VDS = -VDD … 0 VDS
CMOS Concept discovered by IDS=f(VDS)
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VDS = -VDD … 0
VGS =
-VDD … 0
VDS = 0 …+VDD
VGS =
0 …+VDD
VGS =
-VDD … 0
VDS = -VDD … 0 VDS
VGS =
0 … VDD
VDS = 0 … VDD
VDS
VGS=0
VDD
VGS
CMOS Concept discovered by IDS=f(VDS)
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VDS = -VDD … 0
VGS =
-VDD … 0
VDS = 0 …+VDD
VGS =
0 …+VDD
VGS =
-VDD … 0
VDS = -VDD … 0 VDS
VGS =
0 … VDD
VDS = 0 … VDD
VDS
VGS=0
VDD
VGS
CMOS Concept discovered by IDS=f(VDS)
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Vout=VDD
No Current!
Concept of the CMOS InverterInput = low
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Vout=0.95V
Concept of the CMOS Inverter
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Vout=0.8V
Concept of the CMOS Inverter
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Vout=0.2V
Concept of the CMOS Inverter
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Vout=0.05V
Concept of the CMOS Inverter
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Vout=0V
No Current!
Concept of the CMOS InverterInput = high
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Ideal: long channel & IDsat(N)=IDsat(P)
Real: short channel & IDsat(N)>IDsat(P)
To get closer to ideal, design of FET width W(P) > W(N) !L12
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CMOS ComplementaryMOS(UtilizingNMOS & PMOS)
Inverter
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CMOS ComplementaryMOS(UtilizingNMOS & PMOS)
Inverter
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CMOS Inverter
Aus: Schumiki, Seegebrecht „Prozeßtechnologie“ Springer 1991
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CMOS Inverter
Aus: Schumiki, Seegebrecht „Prozeßtechnologie“ Springer 1991
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4.3. CMOS Prozessablauf
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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4.3. CMOS Prozessablauf
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
CMOS Inverter:
Epi Wafer-Dual well-STI-SiGate-LDD (S/D extensions)-SALICIDE-SAC-Dielecric CMP
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CMOS Inverter-STI
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-STI
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-wells
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-wells
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-Si Gate & S/D extensions
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-Si Gate & S/D extensions
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-S/D formation
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-S/D formation
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-SALICIDE & SAC contact etch
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-SALICIDE & SAC contact etch
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter- Metal 1
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter- Metal 1
Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
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CMOS Inverter-Metal 2 +
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CMOS Inverter-Metal 2 +
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CMOS Inverter-Metal 2 +
In this scheme: Metal is etched and Oxide is polished!
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Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
Alternative Metallization
Scheme
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Taken from IC Knowledge 2008http://www.icknowledge.com/misc_technology/Overview%20Post.pdf
Alternative Metallization
Scheme
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CMOS SRAM
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Integrated Circuit of a Logic Adder
Example for a logic circuit: CMOS Adder
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Outline
http://www.computerhistory.org/siliconengine/timeline/
0. Introduction/ Lab organization/DMA /SCT1/Motivation1. Process integration
1.MOS Structure, MOS Capacitor2.Structure of a MOSFET3.I/V behavior
2. Circuits in Metal-Gate FET Technology1.Process sequence of N-MOSFET in Metal Gate2.From inverter to memory cell3.SRAM in NMOS Metal Gate4.The threshold voltage of the MOSFET
1.Parasitic FET2.Enhancement/Depletion Transistor3.N-MOS Logic by E/D Transitors4.Process sequence of the N-MOS E/D Process
3. Self aligned Process1.Metal Gate -> Si Gate2. Channel-Stop & LOCOS Technology
1.Example: Process flow of E/D SiGate LOCOS Inverter 2.LOCOS Variation3.Shallow Trench Isolation
3.Lightly doped drain4.SALICIDE5. Self Aligned Contacts (SAC)6. Resist trimming
4.Transition to CMOS Technology1.MOS Transistor Types2.CMOS Inverter
1.Consideration NMOS E/D Inverter2.Comparison CMOS Inverter
3.CMOS Process flow (Example CMOS 180 nm process)5. Further Considerations
1.Scaling1. Challenges2.Material Equivalent Scaling3.Further Concepts
SC-Basics
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