lecture08 delay

8/11/2019 Lecture08 Delay

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Lecture 8 ECE 425

Lecture 8 -- Gate-level Delay Estimation


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Lecture 8 ECE 425

Outline

Estimating delay of single gates and multi-gate circuits


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Pictorial View


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Why do we care?

Its pretty obvious why we care about gate delay, in thatwe like circuits to go fast

Rise/fall times matter for a number of reasons

Theyre a component of total gate delay

While the inputs to a gate are rising or falling, aconductive path exists between power and ground

Power dissipation

Can potentially harm the chip if too much current

flows

For signals that have high inductance, overly short

rise/fall times can lead to di/dt-induced swings

Mostly relevant on chip I/O pins


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Estimating Delay

Gate delays are determined by how quickly the drivinggate can charge/discharge its load capacitance


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Estimating Delay

Gate delay may vary depending on which inputs arechanging -- generally use the worst case


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General Approach

Divide circuit into DC-connected components, solve foreach component


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Fall Time Analysis

During the fall time one or more nMOS transistorsdischarge the energy stored in the output capacitance


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Fall Time Analysis

During the fall time, the nMOS transistor starts in thesaturated region and passes into the linear region


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Fall Time Analysis

Divide fall time into two components: tf,satand tf,linear

In saturation, current through the transistor is constant


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Fall Time

This becomes

Define t1, t2such that Vo(t1) = 0.9Vddand Vo(t2) = Vdd- Vt.

Then,

And tf, satis:


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Fall Time

In the linear region, current through the transistordepends on Vo

And tf, linearbecomes


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Fall Time

Integrating, we get tf, linear =

And

For many processes, Vt~= 0.2Vdd, allowing us toapproximate


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Rise Time

Redoing the same analysis for the pMOS transistor in pull-up gives

Note that beta for pMOS tends to be about 1/2 beta for

nMOS given equivalent size devices, so typically want

pMOS about twice as wide as nMOS to get equivalent

rise and fall times


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Gate Delay Estimation

Somewhat more complicated -- depends on rise and falltimes of the input signals.

Assuming (unrealistically) that the input rises or falls inzero time, then the gate delay can be approximated ashalf of the rise or fall time for the gate, and averaged to

Since gates are generally driven by other gates, we needa better approximation for real circuits

Could just simulate the design, but that wouldnt givemuch insight

Simulation is good for verifying that something worksthe way you want but not for designing it to do so


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Circuit Delay Estimation

1. Divide circuit into DC-connected blocks as we talkedabout at the start of lecture.

2. Compute a simple delay model for each block

3. Add the delays for each block to get overall delay.

In CMOS, a DC-connected block (stage) will be either:

1. A single logic gate

2. A transmission-gate network and the gates driving it

In the simple case, a block switches in response to a single

signal changing at one of its inputs, called the trigger

signal


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Making the System Tractable

As weve seen, solving even simple transistor networksanalytically requires solving differential equations that

change at region boundaries

For example, the rise and fall time derivations we

presented really only apply for inverters, and

computing them for larger gates is more complex

Now think about doing that for a 100-transistor

network, much less anything bigger

Solution: linearizethe transistor equations by replacingeach transistor with an equivalent resistor, Reff


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Computing Reff

Refffor a transistor depends on what region its operatingin

Example: Reff= dVds/dIds = infinity in saturation

In linear region,

During switching, a transistor travels through different

regions of operation

We want a single Reffthat approximates the behavior of atransistor during the entire rise/fall time

Reffwill be different depending on whether the

transistor is transmitting a zero or a one.


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Case One -- nMOS Transistor, Logic 0

nMOS transistor, discharging capacitor to ground


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nMOS Transistor, Logic 0

Want to model as a single network with Reff, C

Choose Reffso that both circuits have the same fall time


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Back to the I-V curve


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Problem: VOnever makes it to 0.9 Vddin this case,assuming Vt= 0.2Vdd, so cant try to match the full rise

time

If we try to match the time it takes to hit 0.5Vdd, we get

Note that this is about 3x larger than the dischargingcase. Why does this make sense?


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pMOS Transistors


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Estimating Stage Delay

Need to decide whether each transistor is off, transmittinga logic 0, or transmitting a logic 1.

Then, can replace the stage with an RC network


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This is stilltoo complex -- solving these networks exactlyrequires solving several simultaneous differential

equations.

Simplify further by reducing to an equivalent single-RC

network with time constant


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Example of the Process


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At most one node should be the input node to the stage,corresponding to either Vddor Vss

Generally, were interested in the delay at a specific

output node

Question: how to compute Reqand Ceq? When the RC-network is a tree (no loops), there is a good

estimate that is also easy to compute.

This estimate of is called the Elmore Time

Constant


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Estimating the Stage delay

1. Identify an input node and an output node, and theunique path between them. Call the path P

2. For every node n in the tree other than the input node

1. Identify the unique path between the input node and n

2. Identify the sub-path that is the intersection of thispath and P

3. Sum the resistances along the sub-path, call it Rn4. If Cn is the capacitance at n, create a !n= RnCn

3. Sum the !n to get

!

eqfor the network

4. Given !eq, can select Reqand Ceqvalues to match, but

generally dont need to, !eqis enough


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Example


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Example


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One Note

If a node n is already at the voltage it will have after thetransition, set !n= 0, since the node will not be charging

or discharging

Example:


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Cascade of Stages

Suppose stage 1 feeds stage 2

If the time constant of stage 1 is !1, when is stage 2

triggered? (I.e., when does it start switching)

Time for yet another approximation


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Cascade of Stages

By convention, assume that stage 2 is triggered when theoutput of stage 1 has completed 90% of its logic swing

and is thus well within Vtof one of the rails

Thus, the delay through stage 1 is

Thus, if stage 1 triggers at time 0, stage 2 triggers at time2.3 !1, stage 3 triggers at time 2.3 !1 + 2.3 !2, etc.


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Interconnect Delay

Interconnect delay can be a big issue, particularly forsystems larger than a few gates

Interconnect delay is a function of interconnect length

To be fully accurate, youd treat interconnects as

transmission lines and analyze them that way Were not going to do that, surprise surprise


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Interconnect Delay

Instead, break long lines into lumpedRC-segments


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Interconnect Delay


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Interconnect Delay


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Rules of Thumb

Formally, lowest delay of an interconnect occurs when thedelay of each wire segment equals the delay of the buffer

With this model, interconnect delays become linear, not

quadratic


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Next Time

Logical effort: a way of making circuits fast, not justknowing how slow they are.

lecture08 delay

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