leti activities towards a better power efficiency: from today’s ......2015/07/16 · leti...

LETI activities towards a better Power efficiency: from today’s

solution to disruptive approachesOlivier Faynot• Microelectronic division manager• CEA-Leti

e3s_asstText BoxFor Internal E3S Use Only. These Slides May Contain Prepublication Data and/or Confidential Information.

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• Context• Use of existing technologies• New materials and integration schemes• Disruptive approaches

AGENDA

Olivier Faynot | E3S tutorial | July 2015

Short term

Long term


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AGENDA



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POWER CHALLENGE

� Chips� CPU = 130 W; SoC Consumer 10W; SoC Mobile = 1 W

Traditional CPU

Consumer chip

Mobile chip

Computing power

250 GFLOPS 40 GFLOPS 4 GFLOPS

Energy efficiency

0.5W/ GFLOPS

0.4 W/ GFLOPS(X1.2)

0.25 W/ GFLOPS

(X2)

REQUIRED HW Efficiency

25 TFLOPS(X100)

.5mW/ GB/GFLOP (X1000)

� Classical computers : Performances (Top 500)� 500mw/GFLOP wall� 1PFLOP = 1MW� 1ExaFLOP = 1 GW (projection 2016)

� Web 2.0 : Data Transfer 1GFLOPs requires 1GB/s� New kind of processor required



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POWER CHALLENGE: 2020 OBJECTIVES

X50 by HW and X20 By SW in 2020Increasing proportion of e-Memories in circuit

CMOS Logic

Memory

3D

Photonic



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• Context• Use of existing technologies

� FDSOI� 3D integration

• New materials and integration schemes• Disruptive approaches

AGENDA



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EXAMPLE 1: PLANAR FDSOI TECHNOLOGY

Total dielectric isolation

• Lower S/D capacitances

• Lower S/D leakages

• Latch-up immunity

= Faster, Cooler transistorsUltra-thin Body (TSi~1/3LG)

• Excellent short-channel immunity • low SCE, DIBL

No channel doping, no pocket implant

• Improved VT variationUltra-thin BOX option

• Back-bias controlGround-plane implantation

• VT adjustment

Thin Silicon Channel



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USE OF FDSOI

Ene

rgy

Effi

cien

cy(D

MIP

S/m

W)

Vdd

100%

200%

300%

400%

500%

0%0.3 0.5 0.70.4 0.6 0.8 0.9 1.0 1.1 1.2

+50%

• 2 key words: Low VDD and Back Bias



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• Best in class for Power efficiency

• Ability for Low Voltage operation

USE OF FDSOI

Thin Silicon Channel



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Source: Bill Dally, « To ExaScale and Beyond »www.nvidia.com/content/PDF/sc_2010/theater/Dally_SC 10.pdf

EXAMPLE 2: 3D INTEGRATION

Source: Bill Dally, « To ExaScale and Beyond »

www.nvidia.com/content/PDF/sc_2010/theater/Dally_SC10.pdf Olivier Faynot | E3S tutorial | July 2015


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EXAMPLE 2: SILICON BOARD CONCEPT TO REDUCE ENERGY CONSUMPTION

Traditional technology Silicon Board concept

6 cm²

Large IC with maximum integration on chip Small dies stacked on a large interposer

25x0.9 cm²1 die 25 chiplets+ 1 interposer

95% final test yield

� 296 $ IC cost

90% final test yield

� 284 $ 3D-IC costIC cost*

5000 $ wafer cost

89 dies of 6 cm²

20% yield

� 281 $ die cost

300 mm

Wafer

6 cm² dies 0.9 cm²dies

300 mm

Wafer

25 cm² dies

300 mm

Wafer

� 255 $ total die cost� 281 $ die cost

Interposer:500 $ wafer cost

14 dies of 25 cm²

98% yield

� 36.44 $ die cost

Chiplets:5000 $ wafer cost

714 dies of 0.9 cm²

80% yield

� 8.75 $ die cost

Die cost

*: test and package costs are not included but considered equal for both technologies in this exercise

Sam

e co

st 6

cm

² ve

rsus

25

cm²

2 GFLOPS/W 100 GFLOPS/WMore than 50x energy efficiency

3Ghz 200Mhz

[Denis Dutoit, Gilles Simon]



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• Context• Use of existing technologies• New materials and integration schemes

� SiGe for TFET� RRAM� Coocube TM

• Disruptive approaches

AGENDA



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• P mode operation

• No impact of gate length(1µm => 50nm) on measured I D(VG) curves

A) TUNNEL FET OPERATION


TFET DEVICES: INTEREST OF SIGE

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

-2 -1.5 -1 -0.5 0

Dra

in c

urr

en

t (µ

A/µ

m)

Gate voltage (V)

L=1µm

150nm

70nm

50nm

p mode TFET

W = 2µm

SGOI 25%

VDS = -0.9V

EC

EV

OFF state

ON statee- P+N+

Gate

BOX

VD

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• on the ID(VG) curves :

B) IMPACT OF THE GE CONTENT IN THE CHANNEL



1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

-2 -1.5 -1 -0.5

Dra

in c

urr

en

t (µ

A/µ

m)

Gate voltage (V)

SGOI 25%

SGOI 20%

SOI

p mode TFET

L/W = 1/2µm

VDS = -0.9VVth shift

ION increase

• on the SS(ID) figure of merit :

100

150

200

250

300

350

400

450

500

1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01

SS

(m

V/d

ec)

Drain current (µA/µm)

SGOI 25%

SGOI 20%

SOI

� Threshold voltage shift� ION increase

� No clear impact on min. SS� ION increase at fixed SS


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C) ORIGIN OF THE ON CURRENT GAIN ?



1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

-1.5 -1 -0.5 0 0.5

Dra

in c

urr

en

t (µ

A/µ

m)

VG - Vth (V)

SGOI 25%

SGOI 20%

SOI

• ID(VG-Vth) plots• ID(VG) plots

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

-2 -1.5 -1 -0.5

Dra

in c

urr

en

t (µ

A/µ

m)

Gate voltage (V)

SGOI 25%

SGOI 20%

SOI

p mode TFET

L/W = 1/2µm

VDS = -0.9V

ION increase ION,r increase

� The Vth shift is not the (only) origin of the ON state gain� Relative ON state current (ION,r) is enhanced for large xGe

ION,r @

VG-Vth = -0.9V


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C) ORIGIN OF THE ON CURRENT GAIN ?



• Impact of the Ge content on the SiGe band diagram *

0.8

0.9

1

1.1

0 0.1 0.2 0.3

cSiG

e ba

ndga

p (e

V)

Ge content (cSGOI channel)

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 0.1 0.2 0.3

ener

gy (

eV)

Ge content

0

0.2

0.4

0.6

0.8

1

1.2

1.4

0 0.1 0.2 0.3

ener

gy (

eV)

Ge content

Ec

Ev

EG(xGe)

EG(xGe)

EG(xGe)

EC

EV

OFF state

ON statee- P+N+

� SiGe: Increasing the Ge fraction leads to smaller band gap

*M. Rieger and P. Vogl, Phys. Rev. B 48, 14276 (1993)


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• Electrostatics & transport

TFET - MOSFET COMPARISON : MAIN INTERESTING PROPERTIES


3) INTEREST OF SIGE FOR TFET

pTFET pMOSFET

DIBL vs. L 0 ∝ L-2

SS vs. L constant* SS-kT/q ∝ L-1

ION vs. L constant ∝ L-1

ION vs. xGe(SGOI channel)

∝ exp(xGe)cf. BTBT

∝ xGecf. µhole*

No clear path today for SS

| 18Olivier Faynot | E3S tutorial | July 2015

COOLCUBE TECHNOLOGY

L2

2

1

L1

1 2

Classical 2D CoolcubeTM


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COOLCUBE TECHNOLOGY DESCRIPTION


Bulk TSVSOI TSV

D = 10.000/mm 2

D = 100.000/mm 2

D ~ 100.000.000/mm 2

D> 1.000.000/mm 2

CoolCubeTM


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• By construction:� 50% foot print reduction� Reduced wire length� Additional gain if cell

placement optimized


COOLCUBE

O. Turkylmaz et al., DATE 2014


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COOLCUBE TECHNOLOGY DESCRIPTION


L. Brunet, ECS 2014

Front side macroscopic

aspect of a 300mm wafer

Infrared characterization Acoustic characterization


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CLASSIFICATION OF MEMORY TECHNOLOGY

RRAMMRAMPCMFRAMSONOSFLASH

DRAMSRAM

Volatile Memory Non Volatile Memory

MEMORY DEVICES

Resistance change

Polarization change

Charge trap

Phase change

Tunnel magneto

resistance

• Oxygen-vacancy

• Electro-chemical

Voltage/ current based,

Resistor

Charge based,

Capacitor

3D bulk 1D filamentary



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• Forming voltage compatible with CMOS technology

RESISTIVE MEMORIES

• material set compatible with CMOS• fabrication temperature compatible with

BEOL

Initial pristine state

FORMING

Low Resistive State(LRS)

VG

V

VG(limiter)

V




CBRAM VS OXRAM



NONVOLATILE-LOGIC WITH RRAM



� Dopage Al de l’électrolyte MOx : augmentation de la fenêtre mémoire

� Ab initio: réduction coût énergétique de l’insertion du Cu dans les lacunes d’O, diélectrique moins dégradé

1030.5 1 1.5 2 2.5 3

104

105

106

107

108

HR

S R

esi

sta

nce

[Oh

m]

RESET BL voltage [V]

0%

13%

21%

Typical RON

109

108

107

106

105

104

103

1 1.5 2 2.5 3

RESET WL voltage [V]

13%

21%

0%

Typical RON

MOx(Al)Optimum

doping

Al doping ratio

Cu-based

Doped oxide

MOx(Al)

BEC0.6 0.7 0.8 0.9

1.5

2

2.5

0.5 1

Metal/Oxygen atomic

3

1

FormingSET Forming free

MOx(Hf)

0 5 15 16 20V

olt

ag

e [

V]

Metal /Oxygen atomic ratio

Doping content %

Cu-based

Doped oxide

MOx(Hf)

BEC

� MOx electrolyte Hf doping : Formingvoltage reduction

� Ab initio: reduction of Cu filament formation energy

G. Molas et al., IEDM 2014


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100ns

Tsw

RESISTIVE MEMORIES

TypicalImplementation

Embedded

Distributed

� Low VDD operation demonstrated� Up to 108 cycles demonstrated� Low VDD: open the path for new circuit architecture



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AGENDA




VON NEUMANN MACHINE


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• Von Neumann chips are moving away from the brain’s efficiency

VON NEUMANN BOTTLENECK




NEUROMORPHIC BASED RRAM CIRCUITS



RRAM-SYNAPSE NEURAL NETWORK @ LETI



POTENTIATION (LTP)/DEPRESSION (LTD)



2 PCM SYNAPSE



VISUAL PATTERN EXTRACTION: PCRAM NEURON NETWORK

XNET spiking neural network simulator



VISUAL PATTERN EXTRACTION


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• Energy efficiency improvement requires to work on:� New materials and devices:

• CoolcubeTM and RRAM are the most promising� New circuit design tricks� New architectures and paradigms


KEY MESSAGES


THANKS YOU FOR

YOUR ATTENTION!

CEA17 rue des Martyrs 38000 –Grenoble

Cedex 09 FRANCE


leti activities towards a better power efficiency: from today’s ......2015/07/16 · leti...

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