linear technologlinear technology · linear technology magazine • february 1998 3 design features...

LINEAR TECHNOLOGYLINEAR TECHNOLOGYLINEAR TECHNOLOGYFEBRUARY 1998 VOLUME VIII NUMBER 1

, LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load,FilterCAD, Linear View, Micropower SwitcherCAD, Operational Filter and SwitcherCAD are trademarks of LinearTechnology Corporation. Other product names may be trademarks of the companies that manufacture the products.

Universal Continuous-TimeFilter ChallengesDiscrete Designs by Max Hauser

The LTC1562 is the first in a newfamily of tunable, DC-accurate, con-tinuous-time filter products featuringvery low noise and distortion. It con-tains four independent 2nd order,3-terminal filter blocks that are resis-tor programmable for lowpass orbandpass filtering functions up to150kHz, and has a complete PC boardfootprint smaller than a dime. More-over, the part can deliver arbitrarycontinuous-time pole-zero responses,including highpass, notch and ellip-tic, if one or more programmingresistors are replaced with capaci-tors. The center frequency (f0) of theLTC1562 is internally trimmed, withan absolute accuracy of 0.5%, andcan be adjusted independently in each2nd order section from 10kHz to150kHz by an external resistor. Otherfeatures include:

Rail-to-rail inputs and outputs Wideband signal-to-noise ratio

(SNR) of 103dB Total harmonic distortion (THD)

of –96dB at 20kHz, –80dB at100kHz

Built-in multiple-input summingand gain features; capable of118dB dynamic range

Single- or dual-supply operation,4.75V to 10.5V total

“Zero-power” shutdown modeunder logic control

No clocks, PLLs, DSP or tuningcycles required

The LTC1562, in the SSOP package,provides eight poles of programmablecontinuous-time filtering in a totalsurface mount board area (includingthe programming resistors) of 0.24square inches (155 mm2 )—smallerthan a U.S. 10-cent coin. This filtercan also replace op amp–R-C activefilter circuits and LC filters in appli-cations requiring compactness,flexibility, high dynamic range or fewerprecision components.

What’s Inside?As shown in Figure 1, the LTC1562includes four identical 3-terminalblocks. Each contains active circuitry,precision capacitors and precisionresistors, forming a flexible 2nd orderfilter core. These blocks are designedto make filters as easy to configure asop amps. The 3-terminal arrange-ment minimizes the number ofexternal parts necessary for a com-plete 2nd order filter with arbitrarilyprogrammable f0, Q and gain. Figure2 shows the contents of one block,along with three external resistors,forming a complete lowpass/band-pass filter (the most basic applicationof the LTC1562). In Figure 2, a low-pass response appears between theVIN source and the LP output pin, andsimultaneously a bandpass responseis available at the BP output pin. Bothoutputs have rail-to-rail capabilityfor the maximum possible signalswing, and hence, maximum signal-to-noise ratio (SNR).

continued on page 3

IN THIS ISSUE…COVER ARTICLEUniversal Continuous-Time FilterChallenges Discrete Designs .......... 1Max Hauser

Issue Highlights ............................ 2LTC® in the News ........................... 2DESIGN FEATURESAn SMBus-Controlled 10-Bit, CurrentOutput, 50µA, Full-Scale DAC........ 6Ricky Chow

Micropower 600kHz Fixed-FrequencyDC/DC Converters Step Up from a1-Cell or 2-Cell Battery .................. 8Steve Pietkiewicz

New 333ksps, 16-Bit ADC Offers 90dBSINAD and –100dB THD .............. 11Marco Pan

Ultralow Power 14-Bit ADC Samplesat 200ksps .................................. 14Dave Thomas

A 10MB/s Multiple-Protocol Chip SetSupports Net1 and Net2 Standards................................................... 17

David Soo

DESIGN IDEASHigh Clock-to-Center Frequency RatioLTC1068-200 Extends Capabilities ofSwitched Capacitor Highpass Filter................................................... 23

Frank Cox

LT1533 Ultralow Noise SwitchingRegulator for High Voltage orHigh Current Applications .......... 24Jim Williams

A Complete Battery Backup SolutionUsing a Rechargeable NiCd Cell .. 26L.Y. Lin and S.H. Lim

Zero-Bias Detector Yields HighSensitivity with NanopowerConsumption ............................... 28Mitchell Lee

DESIGN INFORMATIONMicropower Octal 10-Bit DACConserves Board Space with SO-8Footprint ..................................... 29Kevin R. Hoskins

Tiny MSOP Dual Switch Driver isSMBus Controlled ........................ 31Peter Guan

New Device Cameos ..................... 34Design Tools ................................ 35Sales Offices ............................... 36

Linear Technology Magazine • February 19982

EDITOR’S PAGE

LTC in the News…

LTC ReportsAnother Strong Quarter“Demand for our products remainedstrong and well diversified acrossend markets,” said Robert Swanson,president and CEO of Linear Tech-nology Corporation. “We had anotherstrong quarter, achieving record lev-els for sales and profits. The turmoilin the Asian financial markets didnot have a material impact on ourbusiness in this quarter, althoughwe continue to closely monitor thisgeographical area for its impact inthe future.”

Douglas Lee, an analyst atNationsBanc Montgomery Securitiesin San Francisco, predicts that Lin-ear Technology will “see a sequentialsales growth of about 7% for theMarch quarter.” This was reportedin the January 19, 1998 issue ofElectronic Buyers’ News.

Net sales for the second quarterended December 28, 1997 were$117,004,000, an increase of 30%over net sales of $90,080,000 for thesecond quarter of the previous year.The Company also reportednet income for the quarter of$43,582,000, an increase of 38%over the $31,631,000 reported forthe second quarter of last year.

Diluted earnings per share (EPS)were $0.55 compared to $0.40 forthe similar quarter last year. This isthe first quarter that earnings pershare (EPS) are reported in com-pliance with the new FinancialAccounting Standards Board pro-nouncement No. 128. Diluted EPS isanalogous to the methodology theCompany used in the past in report-ing EPS.

During the quarter, Linear Tech-nology purchased 1,002,500 sharesof its stock for $56.4 million, $5.9million of which was paid after quar-ter end. A cash dividend of $0.40 willbe paid on February 11, 1998 toshareholders of record on January23, 1998

Issue HighlightsOur cover article for this issue intro-duces a new filter product, theLTC1562. The LTC1562 is the first ina new family of tunable, DC-accurate,continuous-time filter products fea-turing very low noise and distortion. Itcontains four independent 2nd order,3-terminal filter blocks that are resis-tor programmable for lowpass orbandpass filtering functions up to150kHz, and has a complete PC boardfootprint smaller than a dime.

Data converters are strongly repre-sented in this issue, with a new DACand several new ADCs:

The LTC1427-50 is a 10-bit, cur-rent-source-output DAC with anSMBus interface. This device providesprecision, full-scale current of 50µA±1.5% at room temperature (±3% overtemperature), wide output voltage DCcompliance (from –15V to [VCC – 1.3V])and guaranteed monotonicity over awide supply-voltage range. It is anideal part for applications in con-trast/brightness control or voltageadjustment in feedback loops.

We also introduce the LTC1604, afast, high performance 16-bit sam-pling ADC in a tiny 36-pin SSOPpackage. This device runs at 333kspsand delivers excellent DC and ACperformance. It operates on ±5V sup-plies and typically draws only 220mW.It is a complete differential, high speed,low power, 16-bit sampling ADC thatrequires no external components. TheLTC1604 also provides two power-shutdown modes, NAP and SLEEP, toreduce power consumption duringinactive periods. It not only offers theperformance of the best hybrids butalso provides low power, small size,an easy-to-use interface and the lowcost of a monolithic part.

A new, versatile 14-bit ADC, theLTC1418, can digitize at 200kspswhile consuming only 15mW from asingle 5V supply. The LTC1418 isdesigned to be easy to use and adapt-able, requiring little or no supportcircuitry in a wide variety of applica-

tions. It features 0.25LSB INL maxand 1LSB DNL max, parallel and se-rial data output modes and NAP andSLEEP power-shutdown modes.

In the power conversion arena, wedebut two new micropower DC/DCconverters designed to provide powerfrom a single-cell or higher input volt-age, the LT1308 and the LT1317. TheLT1308 is intended for generatingpower on the order of 2W–5W, for RFpower amplifiers in GSM or DECTterminals or for digital-camera powersupplies. The LT1317, intended forlower power requirements, operatesfrom an input voltage as low as 1.5V.It can generate 100mW to 2W of power.Both devices feature Burst Mode™operation for high efficiency at lightloads. Both devices switch at 600kHz;this high frequency keeps associatedpower components small and flat.

On the interface front, we presenta new multiprotocol chip set that isguaranteed to be Net1 and Net2 com-pliant. The LTC1543/LTC1544/LTC1344A chip set creates a com-plete software-selectable serialinterface using an inexpensive DB-25 connector. The LTC1543 is adedicated data/clock chip and theLTC1544 is a control-signal chip. Thechip set supports the V.28 (RS232),V.35, V.36, RS449, EIA-530, EIA-530Aand X.21 protocols in either DTE orDCE mode.

In the Design Ideas section, wefeature a 1kHz, 8th order Butter-worth highpass filter, power gainstages to extend the output-powercapability of the LT1533 ultralow noiseswitching regulator, a nanopowerzero-bias detector and a complete bat-tery backup solution based on a singleNiCd cell and the LT1558 battery-backup controller.

We conclude with Design Informa-tion on the LTC1660 10-bit octal DACand the LTC1632 SMBus switch con-troller and a pair of New DeviceCameos.

Linear Technology Magazine • February 1998 3

DESIGN FEATURES

The LTC1562 is versatile; it is notlimited to the lowpass/bandpass fil-ter of Figure 2. Cascading multiplesections, of course, yields higher-order filters (Figure 3a). A highpassresponse results if the external inputresistor (RIN of Figure 2) is replaced bya capacitor, CIN, which sets only gain,not critical frequencies (Figure 3b).Responses with arbitrary zeroes (forexample, elliptic or notch responses)are implemented with feedforwardconnections with multiple 2nd orderblocks, as shown in the applicationcircuit in Figure 8. Moreover, the vir-tual-ground INV input gives each2nd-order section the built-in capa-bility for analog operations such asgain (preamplification), summing andweighting of multiple inputs, oraccepting current or charge signalsdirectly. These flexible 3-terminalelements are Operational Filter™blocks.

Although the LTC1562 is offered ina 20-pin SSOP package, the LTC1562is a 16-pin circuit; the extra pins areconnected to the die substrate andshould be returned to the negativepower supply. In single-supply appli-

cations, these extra V– pins should beconnected directly to a PC board’sground plane for the best groundingand shielding of the filter. 16-pin plas-tic DIP packaging is also available(consult the factory).

DC Performanceand Power ShutdownThe LTC1562 operates from single ordual supply voltages, nominally 5V to10V total. It generates an internalhalf-supply reference point (the AGNDpin), establishing a reference voltagefor the inputs and outputs insingle-supply applications. In theseapplications, the AGND pin should bebypassed with a capacitor to theground plane (at V–); the pin can beconnected directly to ground when asplit supply is used. The DC offsetvoltage from the filter input to the LPoutput for a typical 2nd order section(unity DC gain) is typically 5mV. Bothoutputs swing to within approximately100mV of each supply rail with loadsof 5kΩ and 30pF.

To save power in a “sleep” situa-tion, a logic high input on the SHDNpin will put the LTC1562 into itsshutdown mode, in which the chip’spower supply current is reduced toonly junction leakage (typically 2µAfrom a single 5V supply). The shut-down pin is designed to accept CMOSlevels with 5V swing, for example, 0Vand 5V logic levels when the LTC1562is powered from either a single 5V ora split ±5V supply. Note that in theLTC1562, unlike some other prod-ucts, a small bias current source(approximately 2µA) at the SHDN pincauses the chip to default to the shut-down state if this pin is left open.Therefore, the user must rememberto connect the SHDN pin to a logic lowfor normal operation if the shutdownfeature is not used. (This default-to-shutdown convention saves systempower in the shutdown state, since iteliminates even the microampere cur-rent that would otherwise flow fromthe driving logic to the bias-currentsource.)

V+

V–

SHDN

1562 F02

2ND ORDER SECTIONS

A

INV BP LP

B

D C

INV BP LP

INV BP LP INV BP LP

SHUTDOWN SWITCH

SHUTDOWN SWITCH

AGND

V+

V–

–

+

+–

R2 RQ

RIN

VIN

LP INV BP

1562 F01

C

1 sR1C*

*R1 AND C ARE PRECISION INTERNAL COMPONENTS

INV BP LP

2ND ORDER

INV BP LP

2ND ORDER

VIN

VOUT

INV BP LP

2ND ORDER

VOUT

CIN

VIN

Figure 1. LTC1562 block diagram

Figure 2. Single 2nd order section, illustrating connectionwith external resistors R2, RIN and RQ

Figure 3a. Two 2nd order sections cascaded for higher order responseFigure 3b. 2nd order section configured forhighpass output

LTC1562, continued from page 1


DESIGN FEATURES

Frequency ResponsesLowpass filters with standard all-poleresponses (Butterworth, Chebyshev,Bessel, Gaussian and so on) of up to8th order (eight poles) can be realizedwith LTC1562 sections connected asin Figures 2 and 3a; practicalexamples appear later in this article.Resistor ratios program the standardfilter parameters f0, Q and gain;required values of these filter param-eters can be found from tables or fromsoftware such as FilterCAD™ for Win-dows®, available free from LTC.

The “LP” and “BP” outputs of each2nd order section, although namedafter their functions in Figure 2, candisplay other responses than lowpassand bandpass, respectively, if theexternal components are not allresistors. The highpass configurationof Figure 3b has a passband gain setby the ratio CIN/C, where C is aninternal 160pF capacitor in theLTC1562. The two resistors in Figure3b control f0 and Q, as in the othermodes.

The LTC1562 is the firsttruly compact universalactive filter, yet it offersinstrumentation-grade

performance rivaling muchlarger discrete-component

designs.

Bandpass applications can use theLTC1562 in either of two ways. In thebasic configuration, with the onlyexternal components being resistors(Figure 2), the BP output has a band-pass response from VIN. With an inputcapacitor, as in Figure 3b, the BPoutput has a highpass response asnoted above and the LP pin shows abandpass response.

The f0 range is approximately10kHz–150kHz, limited mainly by themagnitudes of the external resistorsrequired. At high f0 these resistors fallbelow 5k, heavily loading the outputsof the LTC1562 and leading to in-creased THD and other effects. A lower

f0 limit of 10kHz reflects an arbitraryresistor magnitude limit of 1 Megohm.The LTC1562’s MOS input circuitrycan accommodate higher resistor val-ues than this, but junction leakagecurrent from the input-protection cir-cuitry may cause DC errors.

Design formulas and further detailson frequency-response programmingappear in the LTC1562 data sheet.

Low Noise and DistortionThe active (that is, amplifier) circuitryin the LTC1562 was designed ex-pressly for filtering. Because of this,filter noise is due primarily to thecircuit resistors rather than to theamplifiers. The amplifiers also exhibitexceptional linearity, even at highfrequencies (patents pending). Thenoise and distortion performance forfilters built with the LTC1562 com-pares favorably with filters usingexpensive, high performance, off-the-shelf op amps that demand manymore external parts and far moreboard area (we know, because we’ve

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

INV B

BP B

LP B

V+

SHDN

LP A

BP A

INV A

INV C

BP C

LP C

V–

AGND

LP D

BP D

INV D

LTC1562

RIN2, 10k

RIN4, 10k

RIN1 10k

VIN2

VIN1

VOUT1

1562 TA01

VOUT2

RIN3 10k

–5V5V

RQ1, 5.62k

R21, 10k

R23, 10k

0.1µF 0.1µF

RQ3, 5.62k

R24, 10k

RQ4, 13k

RQ2, 13k

R22, 10k

FREQUENCY (Hz)10k

GAIN

(dB)

10

0

–10

–20

–30

–40

–50

–60

–70

–80100k 1M

1562 TA02

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

INV B

BP B

LP B

V+

SHDN

LP A

BP A

INV A

INV C

BP C

LP C

V–

AGND

LP D

BP D

INV D

LTC1562

CIN1 150pF

CIN

TO CIN3

1562 TA08

VOUT

–5V5V

FROM HP C

RQ1, 10.2k

R21, 35.7k

R23, 107k

0.1µF 0.1µF

RQ3, 54.9k

R24, 127k

RQ4, 98.9k

RQ2, 22.1k

R22, 66.5k

CIN3 150pF

CIN4 150pF

CIN2 150pF

FREQUENCY (Hz)1k

GAIN

(dB)

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–9010k 100k 1M

1562 TA09

Figure 4. Dual, matched 4th order 100kHz Butterworth lowpass filterFigure 5. Frequency response of Figure 4’scircuit

Figure 6. 8th order Chebyshev highpass filter with 0.05dB ripple (fCUTOFF = 30kHz)Figure 7. Frequency response of Figure 6’scircuit


DESIGN FEATURES

built them). The details of this perfor-mance depend on Q and otherparameters and are reported for spe-cific application examples below. Aswith other low distortion circuits,accurately measuring distortion per-formance requires both an inputsignal and distortion-analyzing equip-ment with adequately low distortionfloors.

Low level signals can exploit a lownoise preamplification feature in theLTC1562. A 2nd order section oper-ated with unity gain, Q = 1 and f0 =100kHz shows a typical output noiseof 24µVRMS, which gives a 103dB SNRwith full-scale output from a 10Vtotal supply. However, reducing thevalue of RIN in Figure 2 increases thegain without a proportional increasein the output noise (unlike many activefilters). A gain of 100 (40dB) with thesame Q and f0 gives a measured output

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

INV B

BP B

LP B

V+

SHDN

LP A

BP A

INV A

INV C

BP C

LP C

V–

AGND

LP D

BP D

INV D

LTC1562

RFF1, 10k

RIN2, 8.06k

RIN4, 7.32k

RFF2, 17.8k

RIN1, 19.6k

CIN1, 87pF

VIN

ALL RESISTORS = 1% METAL FILM

VOUT

1562 TA03

RIN3, 69.8k

–5V5V

RQ1, 13k

R21, 8.87k

R23, 8.87k

0.1µF

RQ3, 28k

R24, 17.8k

RQ4, 6.98k

RQ2, 8.87k

R22, 12.1k

CIN3, 47pF

0.1µF

FREQUENCY (Hz)1k

GAIN

(dB)

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–9010k 100k 1M

1562 TA04

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

INV B

BP B

LP B

V+

SHDN

LP A

BP A

INV A

INV C

BP C

LP C

V–

AGND

LP D

BP D

INV D

LTC1562

RIN1B 3.83k

RIN1A 6.19k

RIN3A 6.19k

VIN1

VIN3

CIN1 680pF

VIN2

1562 TA07

VOUT2

VOUT3 VOUT4

VOUT1

RIN3B 3.83k

–5V5V

RQ1, 10k

R21, 10k

R23, 10k

0.1µF 0.1µF

RQ3, 10k

R24, 10k

RQ4, 10k

RQ2, 10k

R22, 10k

CIN2 680pF

CIN3 680PF

ALL RESISTORS = 1% METAL FILM

RIN2B 3.83k

RIN2A 6.19k

VIN4CIN4 680pF

RIN4B 3.83k

RIN4A 6.19k

Figure 8. 8th order 100kHz elliptic lowpass filter

Figure 9. Frequency response of Figure 8’scircuit.

Figure 10. Quad 3-pole 100kHz Butterworth lowpass filter

noise of 449µVRMS or an input-re-ferred noise of 4.5µVRMS—a 78dBoutput SNR with an input that is40dB down. Thus, the same circuitcan handle a wide range of inputlevels with high SNR by changing (orswitching) the input resistor. In theexample just cited, the ratio of maxi-mum input signal to minimum inputnoise, by changing RIN, is 118dB.

Dual 4th Order 100kHzButterworth Lowpass FilterThe practical circuit in Figure 4 is adual lowpass filter with a Butter-worth (maximally-flat-passband)frequency response. Each half gives aDC-accurate, unity-passband-gainlowpass response with rail-to-railinput and output. With a 10V totalpower supply, the measured outputnoise for one filter is 36µVRMS in a200kHz bandwidth, and the large-

signal output SNR is 100dB. Mea-sured THD at 1VRMS input is –83.5dBat 50kHz and –80dB at 100kHz. Fig-ure 5 shows the frequency responseof one filter.

8th Order 30kHzChebyshev Highpass FilterFigure 6 shows a straightforward useof the highpass configuration in Fig-ure 3b with some practical values.Each of the four cascaded 2nd ordersections has an external capacitor inthe input path, as in Figure 3b. Theresistors in Figure 6 set the f0 and Qvalues of the four sections to realize aChebyshev (equiripple-passband)response with 0.05dB ripple and a30kHz highpass corner. Figure 7shows the frequency response. Totaloutput noise for this circuit is40µVRMS.

8th Order 100kHzElliptic Lowpass FilterFigure 8 illustrates how sharp-cutofffiltering can exploit the OperationalFilter capabilities of the LTC1562. Inthis design, two external capacitorsare added and the virtual-groundinputs of the LTC1562 sum parallelpaths to obtain two notches in thestopband of a lowpass filter, as plot-ted in Figure 9. This response falls80dB in one octave; the total outputnoise is 46µVRMS and the Signal/

continued on page 32


DESIGN FEATURES

The LTC1427-50 is a 10-bit, cur-rent-output DAC with an SMBusinterface. This device provides preci-sion, full-scale current of 50µA ±1.5%at room temperature (±2.5% over tem-perature), wide output voltage DCcompliance (from –15V to (VCC – 1.3V))and guaranteed monotonicity over awide supply-voltage range. It is anideal part for applications in con-trast/brightness control or voltageadjustment in feedback loops.

DescriptionThe LTC1427-50 communicates withexternal circuitry using the standard2-wire I2C or SMBus interface. Theoperating sequence (Figure 1) showsthe signals on the SMBus. The twobus lines, SDA and SCL, must be highwhen the bus is not in use. Externalpull-up resistors are required on theselines. The LTC1427-50 is a receive-only (slave) device; the system mastermust apply the Write Byte protocol(Figure 1) to communicate with theLTC1427-50.

The master places the LTC1427-50 in a START condition and transmitsa 7-bit address. The write bit is thenmade 0. The LTC1427-50 acknowl-edges and the master transmits thecommand byte. The LTC1427 againacknowledges and latches the activebits of the command byte into registerA (see the block diagram in Figure 2)at the falling edge of the acknowledgepulse. The master then sends thedata byte; the LTC1427-50 acknowl-edges receipt of the data byte; and,finally, the 8-bit data byte and thelast two output bits (the two MSBs ofthe 10-bit input data) from register Aare latched into the register C at thefalling edge of the final acknowledgeand the DAC current output assumesthe new 10-bit value. A stop conditionis optional.

The LTC1427-50 can respond toone of four 7-bit addresses. The firstfive bits have been factory pro-

An SMBus-Controlled 10-Bit, CurrentOutput, 50µA Full-Scale DAC by Ricky Chow

grammed and are always 01011. Thelast two LSB address bits are pro-grammed by the user via AD1 andAD0 (Table 1). When AD1 and AD0are both connected to VCC, upon powerup, the 10-bit internal register C isreset to 1000000000B and the DACoutput is set to midrange. If eitherAD1 or AD0 is connected to ground,at power-up, register C resets to0000000000B and the DAC output isset to zero. For the LTC1427-50, thesource current output (IOUT) can bebiased from –15V to (VCC – 1.3V);

precision full-scale current is trimmedto ±1.5% at room temperature and±2.5% over the commercial tempera-ture range.

There are two ways to shut downthe LTC1427 (see Figure 2). A logiclow at the SHDN pin or a logic high atbit 7 of the command byte sentthrough the SMBus interface will putthe LTC1427 into shutdown mode. Inshutdown mode, the digital data isretained internally and the supplycurrent drops to only 12µA typically.

XXXXX11110SDA

SCL

IOUT

1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27FULL-SCALE CURRENT

S = START P = STOP *OPTIONAL

SMBus WRITE BYTE PROTOCOL, WITH SMBus ADDRESS = 0101111B, COMMAND BYTE = 0XXXXX11B AND DATA BYTE = 11111111B, AD1 = 0, AD0 =1

ZERO-SCALE CURRENT

P

0 111111WR

ACK

SHDN

ACK

ACK

11 11

S

SMBus ADDRESS COMMAND BYTE DATA BYTE

1427_01.EPS

RADJ

IOUT

SCL

SDA

AD0 AD1

10

SHDN

SHDN

VOLTAGE REFERENCEREGISTER B

1-BIT LATCH EN2 SD

EN2

REGISTER C

10-BIT LATCH

SMBus INTERFACE

3-BIT LATCH

REGISTER A

EN1

POWER-ON RESET

13

2

810-BIT CURRENT DAC

SD

1427_02.EPS

SD

Figure 1. LTC1427-50 operating sequence

Figure 2. LTC1427-50 block diagram

1DA 0DA noitacoLsserddAsuBMS eulaVpU-rewoPCAD noitacilppAL L 1011010 elacs-oreZ lortnoCthgilkcaBDCL

L H 1111010 elacs-oreZ esopruPlareneG

H L 0111010 elacs-oreZ esopruPlareneG

H H 0011010 elacs-diM lortnoCtsartnoCDCL

Table 1. LTC1427-50 function table


DESIGN FEATURES

Digitally ControlledLCD Bias GeneratorFigure 3 is a schematic of a digitallycontrolled LCD bias generator usinga standard SMBus 2-wire interface.The LT1317 is configured as a boostconverter, with the output voltage(VOUT) determined by the values of thefeedback resistors, R1 and R2. TheLTC1427-50’s DAC current output isconnected to the feedback node of the

SHDN

AD1

AD0

GND

VCC

IOUT

SCL

SDA

1

2

3

4

8

7

6

5

µP

(e.g., 8051)

P1.2

P1.1

P1.0

LTC1427-50SHDNSHDN

VIN SW

FB

GND VC

LT1317

L1 D1

100k

4700pF

R2 12.1k 1%

R1 226k 1%

C1 1µF

1µF

2–4 CELLS

VCC = 3.3VVOUT*

VOUT = 12.7V–24V IN 11mV STEPS 15mA FROM 2 CELLS 35mA FROM 3 CELLS

*

L1 = 10µH (SUMIDA CD43 MURATA-ERIE LQH3C OR COILCRAFT DO1608) D1 = MBR0530

6 5

2

14

3

+ +

+

LAMPC2 27pF 3kV

R2 220k

R3 100k

Q2* Q1*C1*

0.1µF

L2 100µH

C3A 2.2µF 35V

C3B 2.2µF 35V

VBAT 8V–28V

C5 1000pF

10 6

3 2 1 4 5

L1

D1 1N5818

R1 750Ω

D5 BAT85

C7

1µF

C4 2.2µF

VIN 3.3V

1

12

3

4

5

7

8

9

16

15

14

13

11

10

6

2

5

6

4

8

1

7

2

3

CCFL PGND VIN

DIO

CCFL VC

AGND

NC

NC

NC

CCFL VSW

BULB

BAT

ROYER

REF

NC

SHDN

ICCFL

LT1184F

VCC 3.3V

SHDN

IOUT

AD1

AD0

SDA

SCL

GND

VCC

AN ALUMINUM ELECTROLYTIC WITH AN ESR ≥0.5Ω IS RECOMMENDED FOR C3B TO PREVENT DAMAGE TO THE LT1184F HIGH-SIDE SENSE RESISTOR DUE TO SURGE CURRENTS AT TURN-ON. C1 MUST BE A LOW LOSS CAPACITOR (WIMA MKP-20) Q1, Q2 = ZETEX ZTX849 OR ROHM 2SC5001 L1 = COILTRONICS CTX210605 L2 = COILTRONICS CTX100-4 COILCTRONICS (561) 241-7876 *DO NOT SUBSTITUTE COMPONENTS

0µA–50µA ICCFL CURRENT GIVES 0mA–6mA LAMP CURRENT FOR A TYPICAL DISPLAY

SHDN

LTC1427-50

SMBus TO HOST

C6 0.1µF

Digitally ControlledCCFL Current Usingthe SMBus InterfaceFigure 4 is a schematic of a 90%efficient, digitally controlled floatingCCFL lamp supply using the SMBusserial interface. The DAC current out-put is connected to the ICCFL pin ofLT1184F. With the DAC output cur-rent range of 0µA to 50µA, this circuitgives 0mA to 6mA lamp current for atypical display. Varying the lamp cur-rent from its minimum to maximumlevel adjusts the lamp intensity, andhence, the display brightness.

ConclusionThe LTC1427-50 is a precision 10-bit,50µA full-scale DAC that communi-cates directly with an I2C or SMBusinterface. It operates from a wide sup-ply range, consumes low power, hasguaranteed monotonicity and is pack-aged in a popular SO-8. It is ideal forapplications such as contrast/brightness controls, output voltageadjustment in power supplies andother potentiometer applications.

LT1317. The LTC1427-50’s DAC cur-rent output increases or decreasesaccording to the data sent via theSMBus. As the DAC output currentvaries from 0µA to 50µA, the outputvoltage is controlled over the range of12.7V to 24V. A 1LSB change in theDAC output current corresponds toan 11mV change in the output voltage.

Figure 3. Digitally controlled LCD bias generator

Figure 4. 90% efficient digitally controlled floating CCFL supply using the SMBus serial interface


DESIGN FEATURES

Micropower 600kHz Fixed-FrequencyDC/DC Converters Step Up froma 1-Cell or 2-Cell Battery by Steve Pietkiewicz

Linear Technology introduces twonew micropower DC/DC convertersdesigned to provide power from asingle-cell or higher input voltage.The LT1308 features an onboardswitch capable of handling 2A with avoltage drop of 300mV and operatesfrom an input voltage as low as 1V.The LT1317, intended for lower powerrequirements, operates from an inputvoltage as low as 1.5V. Its internalswitch handles 600mA with a drop of360mV. Both devices feature BurstMode operation at light load; efficien-cies are above 70% for load currentsof 1mA. Both devices switch at600kHz; this high frequency keeps

associated power components smalland flat; additionally, troublesomeinterference problems in the sensi-tive 455kHz IF band are avoided. TheLT1308 is intended for generatingpower on the order of 2W–5W. This issufficient for RF power amplifiers inGSM or DECT terminals or for digital-camera power supplies. The LT1317,with its smaller switch, can generate100mW to 2W of power. The LT1317is available in LTC’s smallest 8-leadpackage, the MSOP. This package isapproximately one-half the size of astandard 8-lead SO package. TheLT1308 is available in the 8-lead SOpackage.

Single Li-Ion Cell to 5V/1ADC/DC Converter for GSMGSM terminals have emerged as aworldwide standard. A commonrequirement for these products is anefficient, compact, step-up converterto develop 5V from a single Li-Ion cellto power the RF amplifier. The LT1308performs this function with a mini-mum of external components. Thecircuit is detailed in Figure 1. Manydesigns use a large aluminum elec-trolytic capacitor (1000µF to 3300µF)at the DC/DC converter output tohold up the output voltage during thetransmit time slice, since the ampli-fier can require more than 1A. The

VIN

SW

FB

LT1308

L1 4.7µH

3V TO 4.2V

D1

LBO

LBI

RC 47k

R2 100k

5V 1A

R1 301k

CC 22nF

1308_01,eps

C1 100µF

C2 100µF

Li-Ion CELL

VC GND

SHDN

AVX TPS SERIES INTERNATIONAL RECTIFIER 10BQ015 COILTRONICS CTX5-1 COILCRAFT DO3316-472

+ +2200µF

C1,C2: D1: L1:

LOAD CURRENT (mA)1

EFFI

CIEN

CY (%

)

95

90

85

80

75

70

6510 100 1000

1308 F01a

VIN = 4.2V

VIN = 3.6V

VIN = 3V

VIN

SW

FB

LT1308

L1 4.7µH

D1

LBO

LBI

RC 47k

R2 100k

3.3V 400mA

R1 169k

CC 22nF

1308_04.eps

C1 10µF

C2 100µF

NiCD CELL

VC GND

SHDN

C1: CERAMIC C2: AVX TPS SERIES D1: IR 10BQ015 L1: COILTRONICS CTX5-1 COILCRAFT DO3316-472

+

LOAD CURRENT (mA)

90

85

80

75

70

65

60

55

501 100 1000

1308 G01

10

EFFI

CIEN

CY (%

)

VIN = 1.2V VOUT = 3.3V R1 = 169k

Figure 2. Efficiency of Figure 1’scircuit reaches 90%

Figure 3. Transient response ofDC/DC converter: VIN = 3V, 0A–1Aload step

Figure 5. Efficiency of Figure 4’scircuit reaches 81%

VOUT200mV/DIV

AC COUPLED

INDUCTORCURRENT

1A/DIV1ms/DIV

Figure 1. Single Li-Ion cell to 5V/1A DC/DC converter Figure 4. Single NiCd cell to 3.3V/400mA DC/DC converter


DESIGN FEATURES

output capacitor, along with theLT1308 compensation network,serves to smooth out the input cur-rent demanded from the Li-Ion cell.Efficiency, which reaches 90%, isshown in Figure 2. Transient responseof a 0A to 1A load step with typicalGSM profiling (1:8 duty cycle, 577µspulse duration) is depicted in Figure3. Voltage droop (top trace) is 200mV.Inductor current (bottom trace)increases to 1.7A peak; the inputcapacitor supplies some of this cur-rent, with the remainder drawn fromthe Li-Ion cell.

Single NiCd Cell to 3.3V/400mA Supply for DECTOnly minor changes are required inFigure 1’s circuit to construct a single-cell NiCd to 3.3V converter. The largeoutput capacitor is no longer requiredas the output current can be handleddirectly by the LT1308. Figure 4 showsthe DECT DC/DC converter circuit.

Efficiency, reaching 81% from a 1.2Vinput, is pictured in Figure 5. Tran-sient response of a typical DECT loadof 50mA to 400mA is detailed in Figure6. Output voltage droop (top trace) isunder 200mV. Figure 7 zooms in on asingle pulse to show the output volt-age and inductor current responsesmore clearly.

2-Cell Digital CameraSupply Produces3.3V, 5V, 18V and –10VPower supplies for digital camerasmust be small and efficient whilegenerating several voltages. The DSPand logic need 3.3V, the ADC andLCD display need 5V and biasing forthe CCD element requires 18V and–10V. The power supplies must alsobe free of low frequency noise, so thatpostfiltering can be done easily. Theobvious approach, to use a separateDC/DC converter IC for each outputvoltage, is not cost-effective. A single

VIN SW

FBLT1308

L1A N = 1 10µH

L1C N = 0.3

R4 47k

R1 100k

5V 200mA3.3V 200mA

CCD BIAS –10V 10mA

CCD BIAS 18V 10mA

VIN 1.6V

TO 6V

R3 340k

R2 2.01M

D1

C7 22nF

C8 1nF

1308_08.eps

C6 10µF

VC

GND

SHDN

C1, C2, C3 = AVX TPS C4, C5 = AVX TAJ C6 = CERAMIC

18 2 3

L1B N = 0.7

3

4

C2 100µF

C1 100µF

+D2

D3

D4

+C3 100µF

+ C4 10µF

+

C5 10µF

+

L1D N = 3.5

7

6

L1E N = 2

6

5

D1, D2 = IR 10BQ015 D3, D4 = BAT-85 L1 = COILTRONICS CTX02-13973

INPUT VOLTAGE (V)1

EFFI

CIEN

CY (%

)

70

80

85

75

65

55

5

1308_09.EPS

60

5021.5 2.5 3.5 4.53 4

90

100mA LOADS

150mA LOADS 200mA LOADS

LT1308, along with an inexpensivetransformer, generates 3.3V/200mA,5V/200mA, 18V/10mA and –10V/10mA from a pair of AA or AAA cells.Figure 8 shows the circuit. A coupled-flyback scheme is used, actually anextension of the SEPIC (single endedprimary inductance converter) topol-ogy. The addition of capacitor C6clamps the SW pin, eliminating asnubber network. Both the 3.3V and5V outputs are fed back to the LT1308FB pin, a technique known as splitfeedback. This compromise results inbetter overall line and load regula-tion. The 5V output has more influencethan the 3.3V output, as can be seenfrom the relative values of R2 and R3.Transformer T1 is available fromCoiltronics, Inc. (561-241-7876).Efficiency vs input voltage for severalload currents on both 3.3V and 5Voutputs is pictured in Figure 9. TheCCD bias voltages are loaded with10mA in all cases.

VOUT200mV/DIV

AC COUPLED

400mAILOAD

50mA

IL1 1A/DIV

100µs/DIV

VOUT200mV/DIV

AC COUPLED

400mAILOAD

20ms/DIV

50mA

Figure 6. DECT load transient response: with a singleNiCd cell, the LT1308 provides 3.3V with a 400mApulsed load. The pulse width = 416µs.

Figure 7. DECT load transient response: faster sweep speed(100µs/DIV) details VOUT and inductor current of a singleDECT transmit pulse.

Figure 8. This digital camera power supply delivers 5V/200mA, 3.3V/200mA, 18V/10mA and –10V/10mA from two AA cells.

Figure 9. Camera power supply efficiencyreaches 78%.


DESIGN FEATURES

VIN

SW

FB

LT1317

L1 22µH

D1

LBO

LBI

RC 100k

R2 324k 1%

5V 200mA

R1 1M

CC 680pF

1308_10.eps

C1 10µF 10V

C2 33µF

2 CELLS

VC GND

SHDN

C1: CERAMIC D1:MOTOROLA MBRO520L L1: 22 µH SUMIDA CD43-220

+

SHUTDOWN

R3 47k

C6 680pF

L1 22µH

L2 22µH

C2 33µF

C1 10µF

C5 1µF

C4 1µF

C3 15µF

D2A D2B

D1

–VOUT –4V/10mA

+VOUT 4V/70mA

VIN 2.5V–5V

SHUTDOWN

R1 1M

R2 442k

VIN SW

VC GND

LB0

SHDN

FB

LB1

LT1317

L1, L2 =MURATA LQH3C220 C1 =MURATA GRM235Y5V106Z01 D1 =MBR0520 D2 =BAT54S (DUAL DIODE) C2 =AVX TAJB33M6010 C3 =AVX TAJA156MO1O C4, C5 =CERAMIC

+

+

LT1317 2-Cell to 5VDC/DC ConverterFigure 10 shows a simple 2-cell to 5VDC/DC converter using the LT1317.This device generates a clean, lowripple output from an input voltage aslow as 1.5V. Designed for 2-cell appli-cations, it offers better performancethan its 1-cell predecessor, theLT1307. More gain in the error ampli-fier results in lower Burst Mode ripple,and an internal preregulator elimi-nates oscillator variation with inputvoltage. For comparison, Figure 11details transient responses of boththe LT1307 and the LT1317 generat-ing 5V from a 3V input. The load stepis 5mA to 200mA. Output capacitancein both cases is 33µF. The LT1307 has

VOUTLT1307

100mV/DIV5V OFFSET

VOUTLT1317

100mV/DIV5V OFFSET

500µs/DIV

ILOAD 200mA

5mA

low frequency ripple of 100mV,whereas the LT1317 Burst Mode rippleof 20mV is the same as the 600kHzripple resulting from the outputcapacitor’s ESR with a 200mA load.

Single Li-Ion Cellto ±4V DC/DC ConverterBy again employing the SEPIC topol-ogy, a ±4V supply can be designedwith one IC. Figure 12’s circuit gener-ates 4V at 70mA and –4V at 10mAfrom an input voltage ranging from2.5V to over 5V. Maximum compo-nent height is 2mm. This converteruses two separate inductors (L1 andL2), so it is an uncoupled SEPIC con-verter. This reduces the overall cost,but requires that all output current

pass through C1. Since C1 is ceramic,its ESR is low and there is no appre-ciable efficiency loss. C5 is charged to–VOUT when the switch is off, then itsbottom plate is grounded when theswitch turns on. The negative outputis fairly well regulated, since the di-ode drops tend to cancel. The circuitis switching continuously at ratedload, where efficiency is 75%. Outputripple is under 40mV and can bereduced further with conventionalpostfiltering techniques.

ConclusionThe LT1308 and LT1317 provide lownoise compact solutions for contem-porary portable-product powersupplies.

Figure 10. 2-cell to 5V boost converter using the LT1317

Figure 12. This single Li-Ion cell to ±4V DC/DC converter has a maximum height of 2mm.

Figure 11. The LT1317 has reduced Burst Moderipple compared to the LT1307.


DESIGN FEATURES

New 333ksps, 16-Bit ADC Offers90dB SINAD and –100dB THD

The fastest, highest performance16-bit sampling ADC is now availablein a tiny 36-pin SSOP package fromLinear Technology. It is the LTC1604.This device runs at 333ksps anddelivers excellent DC and AC perfor-mance. The LTC1604 operates on ±5Vsupplies and typically draws only220mW. It is a complete differential,high speed, low power, 16-bit sam-pling ADC that requires no externalcomponents. The LTC1604 also pro-vides two power shutdown modes,NAP and SLEEP, to reduce powerconsumption during inactive periods.This 333ksps, 16-bit device not onlyoffers the performance of the besthybrids but also provides low power,small size, an easy-to-use interfaceand the low cost of a monolithic part.Some of the key features of this newdevice include:

333ksps throughput 16 bits with no missing codes

and ±2LSB INL Low power dissipation and power

shutdown Excellent AC and DC performance Small package—36-pin SSOP

These features of the LTC1604 cansimplify, improve, and lower the cost

of current data acquisition systemsand open up new applications thatwere not previously possible becauseno similar part was available.

Fast ArchitectureTo achieve 333ksps with outstandingAC and DC performance at the 16-bitlevel, careful design is required. Fig-ure 1, the LTC1604 block diagram,illustrates the design of this part. Ahigh performance differential sample-and-hold circuit, combined with anextremely fast successive-approxima-tion ADC and an on-chip reference,delivers an excellent combination ofAC and DC performance. A digitalinterface allows easy connection tomicroprocessors, FIFOs or DSPs.

Outstanding ACand DC PerformanceThe DC specifications include 16 bitswith no missing codes and ±2LSBintegral nonlinearity error guaran-teed over temperature. The gain of theADC is held nearly constant over tem-perature with an on-chip 10ppm/°C(typical) curvature-corrected bandgapreference. Figures 2 and 3 show INL

and DNL error plots, respectively, forthe LTC1604.

The sample-and-hold circuitdetermines the dynamic performanceof the ADC. The LTC1604 has a widebandwidth, very low distortion, dif-ferential sample-and-hold. FastFourier transform (FFT) test tech-niques are used to test the LTC1604’sfrequency response, distortion andnoise at the rated throughput. Byapplying a low distortion sine waveand analyzing the digital output usingan FFT algorithm, the ADC’s spectral

by Marco Pan

SAMPLE/HOLD

CIRCUIT

PRECISION16-BIT DAC

LTC1604

SAR

+AIN

–AIN

VREF (2.50V)

REFCOMP (4.375V)

OUTPUTBUFFER

16 16

LOW DRIFTVOLTAGE

REFERENCE

CLOCK CONTROL LOGIC BUSY

COMPARATOR

RD CS

7.5k

CONVSTSHDN

CODE

INL

(LSB

)

–32768 –16384 0 16384 32767

1604_02. eps

2.0

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

–2.0

CODE

–32768 –16384 16384 32767

DNL

(LSB

)

1604_03. eps

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.0

0Figure 2. The LTC1604 is very accurate, asshown in the INL error plot. This accuracy isachieved without autocalibration and itsassociated overhead. Accuracy relies oncapacitor matching, which is very stable overtemperature and time.


Figure 3. The differential nonlinearity errorplot shows the excellent performance of theLTC1604.


DESIGN FEATURES

content can be examined for frequen-cies other than the fundamental.Figures 4 and 5 show the excellent ACperformance of the LTC1604 at333ksps with fIN = 5kHz and 100kHz,respectively. The AC performance ofthe LTC1604 include total harmonicdistortion of –100dB for a 5kHz inputand –94dB for a 100kHz input and aninput bandwidth of 15MHz for thesample-and-hold.

Very Low NoiseThe noise of an ADC can be evaluatedin two ways: by signal-to-noise ratio(SNR) in the frequency domain and byhistogram in the time domain. TheLTC1604 excels in both. Figure 4demonstrates that the LTC1604 hasa SNR of over 90dB in the frequencydomain. The noise in the time-domainhistogram is the transition noise as-sociated with a high resolution ADC,which can be measured with a fixedDC signal applied to the input of theADC. The resulting output codes arecollected over a large number of con-versions. The shape of the distributionof codes will give an indication of themagnitude of the transition noise. In

Figure 6, the distribution of outputcodes is shown for a DC input thathas been digitized 4096 times. Thedistribution is Gaussian and the RMScode transition noise is about0.66LSB. This corresponds to a noiselevel of 90.9dB relative to full scale.When added to the theoretical 98dBof quantization error for a 16-bit ADC,this yields an SNR of 90.1dB, whichcorrelates very well with the frequencydomain measurements.

Differential Inputs IgnoreCommon Mode NoiseGetting a clean signal to the input(s)of an ADC, especially a 16-bit ADC, isnot an easy task in many systems.Large noise signals from EMI, the ACpower line and digital circuitry areusually present. Filtering and shield-ing are the common techniques forreducing noise, but these are notalways adequate (see “The Care andFeeding of High Performance ADCs:Getting All the Bits You Paid For”;Linear Technology VI:3 [August,1996]). The LTC1604 offers anothertool to fight noise: differential inputs.

Figure 7a depicts a typical single-ended sampling system with groundnoise, which may be 60Hz noise, digi-tal clock noise or some other type ofnoise. When a single-ended input isused, the ground noise adds directlyto the input signal. By using the dif-ferential inputs of the LTC1604 theground noise can be rejected by con-necting the inputs directly across thesignal of interest, as shown in Figure7b. Ground noise becomes “commonmode” and is rejected internally bythe LTC1604 by virtue of its excellentcommon mode rejection ratio (CMRR).Figure 8 shows the CMRR of theLTC1604 versus frequency. Noticethat the CMRR is constant over theentire Nyquist bandwidth and is only6dB lower at 300kHz. This ability toreject high frequency common modesignals is very helpful in samplingsystems, where noise often has highfrequency components due to switch-ing transients.

FREQUENCY (kHz)0

AMPL

ITUD

E (d

B)

–60

–40

–20

60

1604_04.EPS

–80

–100

20 40 80 100 120 140 160

–120

–140

0fSAMPLE = 333kHz

fIN = 4.959kHz

SINAD = 90.2dB

THD = –103.2dB

FREQUENCY (kHz)

AMPL

ITUD

E (d

B)

–60

–40

–20

1604_05.EPS

–80

–100

–120

–140

0

fIN = 97.152kHz

SINAD = 89.0dB

THD = –96dB

fSAMPLE = 333kHz

0 6020 40 80 100 120 140 160

1604_06.eps

CODE

COUN

T

2500

2000

1500

1000

500

0–5 –4 –3 –2 –1 0 1 2 3 4 5

SIGNAL TO BE MEASURED

GROUNDNOISE

SINGLE-INPUTADC

AGND

AINSIGNAL TO BE

MEASURED

GROUNDNOISE

LTC1604

AGND–AIN

+AIN

0

20

40

10

30

60

50

1604_08.eps

10000 10 100INPUT FREQUENCY (kHz)

COM

MON

MOD

E RE

JECT

ION

(dB)

70

Figure 4. This FFT of the LTC1604’sconversion of a full-scale 5kHz sine waveshows outstanding response with a very lownoise floor when sampling at 333ksps.

Figure 5. Even with inputs at 100kHz, theLTC1604’s dynamic linearity remainsrobust.

Figure 6. This histogram shows that theLTC1604 has an RMS code transition noise of0.66dB.

Figure 7a. Single-input ADC measuringa signal riding on common mode noise.

Figure 7b. Differential-input ADC measuring asignal riding on common mode noise. Figure 8. LTC1604 CMRR vs frequency


DESIGN FEATURES

3V Input/Output CompatibleThe LTC1604 operates on ±5V sup-plies, which makes the device easy tointerface to 5V digital systems. Thisdevice can also talk to 3V digital sys-tems: the digital input pins (SHDN,CS, CONVST and RD) of the LTC1604recognize 3V or 5V inputs. TheLTC1604 has a dedicated output sup-ply pin (OVDD) that controls the outputswings of the digital output pins (D0–D15, BUSY) and allows the part totalk to either 3V or 5V digital systems.

Low Power Dissipationand ShutdownThe LTC1604 runs at full speed on±5V supplies and typically draws only220mW. This power consumption canbe reduced further by using the twopower shutdown modes, NAP andSLEEP, during inactive periods. NAPmode cuts down the power to 8mW,leaving the reference and logic pow-ered up. The ADC wakes up “instantly”(400ns) from NAP mode, so NAP modecan be invoked even during briefinactive periods with no penalty ordelay when conversions must startagain.

SLEEP mode is used when thereare extended inactive periods. InSLEEP mode, the ADC powers downall the circuitry, leaving the logic out-puts in a high impedance state. Theonly current that remains is junc-tion-leakage current (less than 1µA).It takes much longer for the ADC towake up from SLEEP mode becausethe reference circuit must power up

and settle to 0.0006% for full accu-racy. The wake-up time also dependson the value of the compensationcapacitor used on the REF COMP pin.With the recommended 47µF capaci-tor, the wake-up time is 160ms.

ApplicationsThe performance of the LTC1604makes it very attractive to use in awide variety of applications, such asdigital signal processing, PC dataacquisition cards, medical instru-mentation and high resolution ormultiplexed data acquisition.

DSP applications often requireexcellent dynamic performance, sincethe ADC must sample high frequencyAC signals. The LTC1604 is the rightchoice in these types of applicationsbecause of the performance of itssample-and-hold. Figure 9 shows howwell the signal-to-noise plus distor-tion ratio and the spurious free

FREQUENCY (kHz)1000

1604_09.eps

0 10 100

EFFE

CTIV

E BI

TS

16

15

14

13

12

11

10

9

8

98

92

86

80

74

68

62

56

50

SINAD (dB)

dynamic range of the converter holdup as the input frequency is increased.

Another common application is PCdata acquisition cards. The highsample rate, the simple, completeconfiguration and excellent linearityof the LTC1604 make it an ideal choicehere. Another advantage that theLTC1604 provides is the synchro-nized internal conversion clock, whichis very useful in this application. Thisfeature eliminates the second exter-nal clock required by other samplingADCs to run conversion, in additionto the normal sample signal. Clearly,this feature makes the LTC1604 anoutstanding choice for PC data acqui-sition cards.

For single-channel or multiplexedhigh speed data acquisition systems,the LTC1604 has the high samplerate and high impedance inputs thathelp smooth the design of these appli-cations. High sample rates allow morechannels in the data acquisition sys-tem on a very low power and costbudget and the high impedance in-puts of the ADC make them very easyto multiplex.

ConclusionThe new LTC1604 is a complete 16-bitADC with a built-in sample-and-holdand reference. It samples at 333kspsand is the fastest device of its kind onthe market. The excellent DC and ACperformance of the LTC1604 not onlymake it extremely valuable in a widevariety of existing high resolution ap-plications while also opening up newapplications.

Figure 9. The LTC1604 has essentially flatSINAD and effective bits out to Nyquist.

for the latest information

on LTC products, visit

www.linear-tech.com


DESIGN FEATURES

Ultralow Power 14-Bit ADCSamples at 200ksps by Dave Thomas

IntroductionA new, versatile 14-bit ADC, theLTC1418, can digitize at 200kspswhile consuming only 15mW from asingle 5V supply. The LTC1418 isdesigned to be easy to use and adapt-able, requiring little or no supportcircuitry in a wide variety of applica-tions. Some of the key features of thisnew device include:

200ksps throughput Low power—15mW Single 5V or ±5V supplies 1.25LSB INL max and 1LSB DNL

max Parallel and serial data output

modes NAP and SLEEP power shutdown

modes Small package—28-pin SSOP

High Performancewithout High PowerFigure 1 shows a block diagram of theLTC1418. This device includes a highperformance differential sample-and-hold circuit, an ultra-efficientsuccessive approximation ADC, anon-chip reference and a digital inter-face that allows easy serial or parallelinterface to a microprocessor, FIFO

or DSP. The LTC1418 is factory cali-brated, so a lengthy calibration cycleis not required to achieve 14-bit per-formance. DC specifications includea 1LSB max differential linearity error(no missing codes) and 1.25LSB maxintegral linearity error guaranteedover temperature. The gain of theADC is controlled by an on-chip10ppm/°C reference that can be eas-ily overdriven with an externalreference if required.

For AC applications, the dynamicperformance of the LTC1418 isexceptional. The extremely low dis-tortion differential sample-and-holdacquires input signals at frequenciesup to 10MHz. At the Nyquist fre-quency, 100kHz, the spurious freedynamic range is typically 95dB. Thenoise is also low with a signal-to-noise ratio (SNR) of 82dB from DC towell beyond Nyquist.

The superior AC and DC perfor-mance of the LTC1418 doesn’t requirea lot of power. In fact, the LTC1418has the lowest power of any 14-bitADC available, just 15mW at 200kHz(10mW at sample rates below 50kHz).Two shutdown modes make it pos-sible to cut power further at lowersample rates.

High Impedance InputsThe LTC1418’s high impedance in-puts allow direct connection of highimpedance sources without introduc-ing errors. Many ADCs have a resistiveinput or input bias current that re-quires low source impedance toachieve low errors. Other ADCs withswitched capacitor inputs exhibit largeoffset shifts when driven with highsource impedance or a large source-impedance imbalance between theirdifferential inputs. The uniquesample-and-hold circuit of theLTC1418 has a low capacitance, highresistance (10MΩ||25pF) switched-capacitor input that has only 2LSB ofoffset shift with a source impedanceimbalance between 0Ω and 1M (seeFigure 2a). (There is no shift if theinput impedance is equal for +AIN and

S/H 14

BUFFER

8k

10µF

10µF

REFCOMP

AIN–

AIN+

VREF

4.096V

5V

LTC1418

14-BIT ADC SELECTABLE SERIAL/

PARALLEL PORT

D13

DGND1418 TA01

VSS (0V OR –5V)

AGND

SER/PAR

D5

D4 (EXTCLKIN)

D3 (SCLK)

D2 (CLKOUT)

D1 (DOUT)

VDD

D0 (EXT/INT)

TIMING AND LOGIC

2.5V REFERENCE

BUSYCSRDCONVSTSHDN1µF

SOURCE IMPEDANCE MISMATCH (OHMS)100

CHAN

GE IN

OFF

SET

VOLT

AGE

(LSB

)

1M

1418_02a.EPS

2

4

5

8

10

01k 10k 100k

SOURCE RESISTANCE (OHMS)1k

MAX

IMU

M S

AMPL

E R

ATE

(SAM

PLES

/SEC

)

1M

1418_02b.EPS

10k

100k

200k

1k10k 100k


Figure 2a. Change in offset voltage withsource impedance mismatch

Figure 2b. Maximum sample rate vsunbuffered source resistance


DESIGN FEATURES

–AIN.) Connecting the ADC directly toa high impedance source avoids addi-tional noise and offset errors thatmay be introduced by buffering cir-cuitry. The only downside to directlyconnecting the ADC to a high sourceimpedance is that the acquisition timewill increase. The low input capaci-tance (20pF) of the LTC1418 allowsfull-speed operation with resistancesup to 2k. Above 2k the sample ratemust be lowered (see Figure 2b).

Differential Inputswith Wideband CMRRThe differential input of the LTC1418has excellent common mode rejec-tion, eliminating the need for someinput-conditioning circuitry. Op ampsand instrumentation amplifiers areoften used to reject common modenoise from EMI, AC power and switch-ing noise. Although these circuitsperform well at low frequencies, theirrejection at high frequencies deterio-rates substantially. Figure 3 showsthe CMRR of the LTC1418 vsfrequency.

Single-Supply orDual-Supply OperationSingle-supply ADCs can be cumber-some to work with in a dual-supplysystem. A signal with a common modeof zero volts has to be shifted up to thecommon mode of the ADC. Shiftingthe common mode can be accom-plished with AC coupling, but DCinformation is lost. Alternatively, anop amp level shifter can be used, butthis adds circuit complexity and

additional errors. The LTC1418 canoperate with single or dual suppliesand allows direct coupling to theinputs in both cases. The ADC isequipped with circuitry that auto-matically detects when –5V is presentat the VSS pin. With a –5V supply, theADC operates in bipolar mode and thefull-scale range becomes ±2.048V for+AIN with respect to –AIN. With a singlesupply, VSS = 0V and the ADC oper-ates in unipolar mode with an inputrange of 0V to 4.096V.

On-Chip ReferenceThe on-chip reference of the LTC1418is a standard 2.5V and is compatiblewith many system references; it isavailable on the REF output (pin 3).An internal amplifier boosts the 2.5Vreference up to 4.096V; this sets thespan for the ADC. The 4.096V outputis available on the REFCOMP output(pin4) and may be used as a referencefor other external circuitry. With atemperature coefficient of 10ppm/°C,both REF and REFCOMP are suited toserve as the master reference for thesystem. However, if an external refer-ence circuit is required, its easy tooverdrive either reference output. The2.5V reference output is resistive (4k)and can be easily overdriven by anyreference with low output impedanceby directly connecting the externalreference to the REF pin. If REFCOMP(the 4.096V reference) is to beoverdriven, tie the REF pin to ground.This disables the output drive of theREFCOMP amplifier, allowing it to beeasily overdriven.

Parallel Data Outputfor High SpeedThe parallel output mode of theLTC1418 allows the lowest digital over-head. A microcontroller can strobe theADC to start the conversion and per-form other tasks while the conversionis running. The ADC will then signalthe microcontroller after the conver-sion is complete with the BUSY signal,at which time valid data is available onthe parallel output bus. BUSY mayalso be used to clock latches or a FIFOdirectly, since data is guaranteed to bevalid with the rising edge of BUSY.

Serial Data Outputfor Minimal WiringThe serial output mode of the LTC1418is simple, requiring just three pins fordata transfer: a data-out pin, a serialclock pin and a control pin. However,its simplicity doesn’t sacrifice flexibil-ity. Serial data can be clocked withthe internal shift clock for minimalhardware or an external shift clockfor synchronization. Additionally, datacan be clocked out during the conver-sion for the highest throughput rateor after the conversion for maximumnoise immunity.

Perfect for Telecom:Wide Dynamic RangeTelecommunications systems requirewide dynamic range. With its lownoise and low distortion, the LTC1418offers extremely wide dynamic rangeover its entire Nyquist bandwidth.Spurious free dynamic range is typi-cally 95dB and only starts to drop offat input frequencies above Nyquist.The ultralow jitter of the sample-and-hold circuit, 5psRMS, keeps the SNRflat from DC to 1MHz, making thisdevice useful for undersamplingapplications.

Another important requirement fortelecom systems is a low error rate. Inany ADC, there is a finite probabilitythat a large conversion error (greaterthan 1% of full scale) will occur. Invideo or flash converters, these largeerrors are called “sparkle codes.” Largeerrors are a problem in telecom sys-tems such as ISDN, because theyresult in errors in data transmission.All ADCs have a rate at which errorsoccur, referred to as the error rate.The error rate is dependent on theADC architecture, design and pro-cess. Error rates vary greatly and canbe as low as 1 in 10 billion to as highas 1 is 1 million. Telecom systemstypically require error rates to be 1 in1 billion or better.

The LTC1418 is designed to haveultralow error rates. The error rate isso low that it is difficult to measurebecause of the time in between errors.To make measurement more practi-cal, the error rate was measured at anelevated temperature of 150°C,

INPUT FREQUENCY (Hz)1k

COM

MON

MOD

E RE

JECT

ION

(dB)

1M

1418_03.EPS

20

40

60

80

100

010k 100k

Figure 3. Input common mode rejection vsinput frequency


DESIGN FEATURES

because error rate increases withtemperature. Even at this high tem-perature, the error rate was 1 in 100billion. The projected error rate at roomtemperature is 1 in 2,000,000 billionor about 1 error every 320 years ifrunning at full conversion rate.

Ideal forLow Power ApplicationsLTC1418 is especially well suited forapplications that require low powerand high speed. The normal operat-ing power is low—only 15mW. Powermay be further reduced if there areextended periods of time between con-versions. During these inactive periodswhen the ADC is not converting, theLTC1418 may be shut down. Thereare two power shutdown modes: NAPand SLEEP.

NAP mode shuts down 85% of thepower and leaves only the referenceand logic powered up. The LTC1418can wake up from NAP mode veryquickly; in just 500ns it can be readyto start converting. In NAP mode, all

data-output control is functional; datafrom the last conversion prior to start-ing NAP mode can be read during NAPmode. RD also controls the state ofthe output buffers. NAP mode is use-ful for applications that must be readyto immediately take data after longinactive periods.

With slow sample rates, power canbe saved by automatically invokingNAP mode between conversions.Referring to Figure 4, the SHDN pinand CONVST pin are driven together.A conversion will be started with thefalling edge of this signal; once theconversion is completed, the ADC willautomatically shut down. Before thenext conversion can start, theCONVST and SHDN pins must bebrought high early enough to allowfor the 500ns wake-up time. Powerdrops with the sample frequency untilit approaches the power of thereference circuit, about 2mW at fre-quencies less than 10kHz.

The SLEEP mode is used when theNAP-mode current drain is too high orif wake-up time is not critical. In

5V

5V

0V

3mAIDD

IDDCONVST = SHDN

1418_04a.EPS

CONVERSION TIME

NAP

WAKE-UP AND

AQUISITION TIME

NAP

CONVST

LTC1418

SHDN

CS0

Figure 4a. NAP mode between conversions

SAMPLE RATE (SPS)1k

2mW

POW

ER D

ISSI

PATI

ON

15mW

10k

1418_04b.EPS

100k 200k

Figure 4b. Power dissipation vs sample ratewith NAP mode between conversions

SLEEP mode, all bias currents areshut down, the reference is shut downand the logic outputs are put in a highimpedance state. The only currentthat remains is junction leakage cur-rent, less than 1µA. Wake-up fromthe SLEEP mode is much slower, sincethe reference circuit must power upand settle to 0.01% for full accuracy.The wake-up time is also dependenton the value of the compensationcapacitor used on the REFCOMP pin;with the recommended 10µF capaci-tor the wake up time is 10ms. SLEEPmode is useful for long inactive peri-ods, that is, times greater than 10ms.

ConclusionThe new LTC1418 low power, 14-bitADC will find uses in many types ofapplications, from industrial ins-trumentation to telephony. TheLTC1418’s adaptable design reducesthe need for expensive support cir-cuitry. This can result in a smaller,lower cost system.

Authors can be contacted at (408) 432-1900


DESIGN FEATURES

A 10MB/s Multiple-Protocol Chip SetSupports Net1 and Net2 Standards

by David SooIntroductionWith the increase in multinationalcomputer networks comes the needfor the network equipment to supportdifferent serial protocols. One solu-tion is to provide a different serialinterface board for each market. Thiscan become unmanageable as prod-uct volume increases. The issues ofboard swapping and inventory areoften discounted. Another solution isto place all of the serial interfaces,each isolated, on a single board. Forexample, when the product is soldwith V.35, the serial cable is mappedto that section of the board. Thisrequires a large connector plus signalrouting and board space.

The best solution is to support manydifferent serial protocols on one con-nector, but that requires the circuitryfor each serial protocol to share thesame connector pins. At first glancethis may not appear to be difficult.Further examination reveals conflict-ing line-termination standards thatrequire resistors to be switched to theconnector pins. As the designerbecomes occupied with the details ofthe interface specification, there isalways the possibility that one smalldetail will be missed. This complianceheadache causes designers to seekout a cost-effective integrated solution.

With the LTC1543, LTC1544 andLTC1344A, LTC has taken the inte-grated approach to multiple-protocol.It does not make sense to use a hand-ful of standard interface parts whenNet1 and Net2 compliance is guaran-teed with the LTC1543, LTC1544 andLTC1344A. Detecon, Inc. documentsthis compliance in Test Report No.NET2/102201/97. With this chip set,network designers can concentrateon functions that increase theend-product value rather than onstandards compliance.

Typical ApplicationLike the LTC1343 software-selectablemultiprotocol transceiver, introducedin the August, 1996 issue of LinearTechnology , the LTC1543/LTC1544/LTC1344A chip set creates a com-plete software-selectable serialinterface using an inexpensive DB-25 connector. The main differencebetween these parts is the division offunctions: the LTC1343 can be con-figured as a data/clock chip or as acontrol-signal chip using the CTRL/CLK pin, whereas the LTC1543 is adedicated data/clock chip and theLTC1544 is a control-signal chip. Thechip set supports the V.28 (RS232),V.35, V.36, RS449, EIA-530, EIA-530Aand X.21 protocols in either DTE orDCE mode.

Figure 1 shows a typical applica-tion using the LTC1543, LTC1544and LTC1344A. By just mapping thechip pins to the connector, the designof the interface port is complete. Thefigure shows a DCE mode connectionto a DB-25 connector.

The LTC1543 contains three driversand three receivers, whereas theLTC1544 contains four drivers andfour receivers. The LTC1344Acontains six switchable resistive ter-minators that are connected only tothe high speed clock and data sig-nals. When the interface protocol is

changed via the mode selection pins,M2, M1 and M0, the drivers, receiversand line terminators are placed intheir proper configuration. The modepin functions are summarized inTable 1. There are internal 50µA pull-up current sources on the mode selectpins, DCE/DTE and the INVERT pins.

DTE vs DCE OperationThe LTC1543/LTC1544/LTC1344Achip set can be configured for eitherDTE or DCE operation in one of twoways. The first way is when the chipset is a dedicated DTE or DCE portwith a connector of appropriate gen-der. The second way is when the porthas one connector that can be config-ured for DTE or DCE operation byrerouting the signals to the chip setusing a dedicated DTE or DCE cable.

Figure 1 is an example of a dedi-cated DCE port using a female DB-25connector. The complement to this portis the DTE-only port using a male DB-25 connector, as shown in Figure 2.

If the port must accommodate bothDTE and DCE modes, the mapping ofthe drivers and receivers to connectorpins must change accordingly. Forexample, in Figure 1, driver 1 in theLTC1543 is connected to pin 3 andpin 16 of the DB-25 connector. In DTEmode, as shown in Figure 2, driver 1is mapped to pins 2 and 14 of the DB-25 connector. A port that can beconfigured for either DTE or DCEoperation is shown in Figure 3. Thisconfiguration requires separate cablesfor proper signal routing.

Cable-SelectableMultiprotocol InterfaceThe interface protocol may be selectedby simply plugging the appropriateinterface cable into the connector. Acable-selectable multiprotocol DTE/DCE interface is shown in Figure 4.

4451CTL/3451CTLemaNedoM 2M 1M 0M

desUtoN 0 0 0A035-AIE 0 0 1

035-AIE 0 1 012.X 0 1 153.V 1 0 0

63.V/944SR 1 0 182.V/232SR 1 1 0

elbaCoN 1 1 1

Table 1. Mode pin functions

text continued on page 32/figures on pp. 18–22


DESIGN FEATURES

1

7

8

10

20

23

13

5

RXD

RXC

TXC

SCTE

TXD

CTS

DSR

DCD

DTR

RTS

LL

M2M1M0

14

2

11

24

12

15

6

22

4

19

18

22

21

20

19

25

26

27GND

28VEE

24

23

18

17

16

15NC

9

17

16

3

15

16

17

18

19

20

21

22

23

24

25

2627

28

1

DB-25 FEMALE CONNECTOR

24232220191718151610976452

3 8 11 12

31

24

5

6

7

8

9

10

11121314

12

3

4

5

6

7

M0M1M2

INVERT

DCE/DTE

8

9

11121314

NC

10

NC

14

LTC1344A

RXD A (104)

RXD B

RXC A (115)

RXC B

TXC A (114)

TXC B

SCTE A (113)

SCTE B

TXD A (103)

TXD B

SGND (102)

SHIELD (101)

CTS A (106)

CTS B

DSR A (107)

DSR B

DCD A (109)

DCD B

DTR A (108)

DTR B

RTS A (105)

RTS B

LL A (141)

VCC

5.0V VCC

VCC

VCC

V CC

MO

M1

M2

V EE

VDD

C1 1.0µF

C3 1.0µF

C2 1.0µF C4 3.3µF

C5 1µF

C8 100pF

C7 100pF

C6 100pF

++ +

+

13

DCE/DTE

LTC1543

LTC1544

DCE/

DTE

M2M1M0

CHARGE PUMP

D1

D2

D3

R1

R2

R3

D1

D2

D3

R1

R2

R3

R4

D4

1544_01.eps

21LATCH

+

Figure 1. Controller-selectable DCE port with DB-25 connector


DESIGN FEATURES

1

7

8

10

6

22

19

4

TXD

SCTE

TXC

RXC

RXD

RTS

DTR

DCD

DSR

CTS

LL

M2M1M0

16

3

9

17

12

15

20

23

5

13

18

22

21

20

19

25

26

27GND

28VEE

24

23

18

17

16

15NC

11

24

14

2

15

16

17

18

19

20

21

22

23

2425

2627

28

1

DB-25 MALE CONNECTOR

24232220191718151610976452

3 8 11 12

31

24

5

6

7

8

9

10

11121314

12

3

4

5

6

7

M0M1M2

INVERT

DCE/DTE

8

9

11121314

10

14

LTC1344A

VCC

5.0V VCC

VCC

V CC

MO

M1

M2

V EE

VDD

C1 1.0µF

C3 1.0µF

C2 1.0µF

C4 3.3µF

C5 1µF

C8 100pF

C7 100pF

C6 100pF

++ +

+

13

DCE/DTE

LTC1543

LTC1544

DCE/

DTE

M2M1M0

CHARGE PUMP

D1

D2

D3

R1

R2

R3

D1

D2

D3

R1

R2

R3

R4

D4

1544_02.eps

TXD A (103)

TXD B

SCTE A (113)

SCTE B

TXC A (114)

TXC B

RXC A (115)

RXC B

RXD A (104)

RXD B

SGND (102)

SHIELD (101)

RTS A (105)

RTS B

DTR A (108)

DTR B

DCD A (109)

DCD B

DSR A (107)

DSR B

CTS A (106)

CTS B

LL A (141)

21LATCH

+

Figure 2. Controller-selectable multiprotocol DTE port with DB-25 connector


DESIGN FEATURES

1

7

8

10

6

22

19

4

DTE_TXD/ DCE_RXD

DTE_SCTE/ DCE_RXC

DTE_TXC/ DCE_TXC

DTE_RXC/ DCE_SCTE

DTE_RXD/ DCE_TXD

DTE_RTS/ DCE_CTS

DTE_DTR/ DCE_DSR

DTE_DCD/ DCE_DCD

DTE_DSR/ DCE_DTR

DTE_CTS/ DCE_RTS

DTE_LL/ DCE_LL

M2DCE/DTE

M1M0

16

3

9

17

12

15

20

23

5

13

18

22

21

20

19

25

26

27GND

28VEE

24

23

18

17

16

15NC

11

24

14

2

15

16

17

18

19

20

21

22

23

2425

2627

28

1

DB-25 CONNECTOR

24232220191718151610976452

3 8 11 12

31

24

5

6

7

8

9

10

11121314

12

3

4

5

6

7

M0M1M2

INVERT

DCE/DTE

8

9

11121314

10

14

LTC1344A

VCC

5.0V VCC

VCC

V CC

MO

M1

M2

V EE

VDD

C1 1.0µF

C3 1.0µF

C2 1.0µF

C4 3.3µF

C5 1µF

C8 100pF

C7 100pF

C6 100pF

++ +

+

13

DCE/DTE

LTC1543

LTC1544

DCE/

DTE

M2M1M0

CHARGE PUMP

D1

D2

D3

R1

R2

R3

D1

D2

D3

R1

R2

R3

R4

D4

1544_03.eps

TXD A DTE DCE

TXD BSCTE A

SCTE B

RXD A

RXD BRXC A

RXC B

TXC A

TXC B

RXC A

RXC B

RXD A

RXD B

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

SGND

SHIELD

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

DCD A

DCD B

DSR A

DSR B

CTS A

CTS B

LL A

DCD A

DCD B

DTR A

DTR B

RTS A

RTS B

LL A

21LATCH

+

Figure 3. Controller-selectable DTE/DCE port with DB-25 connector


DESIGN FEATURES

1

7

8

10

6

22

19

4

DTE_TXD/ DCE_RXD

DTE_SCTE/ DCE_RXC

DTE_TXC/ DCE_TXC

DTE_RXC/ DCE_SCTE

DTE_RXD/ DCE_TXD

DTE_RTS/ DCE_CTS

DTE_DTR/ DCE_DSR

DTE_DCD/ DCE_DCD

DTE_DSR/ DCE_DTR

DTE_CTS/ DCE_RTS

16

3

9

17

12

15

20

23

5

13

22

21

20

19

25

26

27GND

28VEE

24

23

18

17

16

15NC

11

24

14

2

15

16

17

18

19

20

21

22

23

2425

2627

28

1

DB-25 CONNECTOR

24232220191718151610976452

3 8 11 12

31

24

5

6

7

8

9

10

11121314

12

3

4

5

6

7

M0M1M2

INVERT

DCE/DTE

8

9

11121314

10

14

LTC1344A

TXD A DTE DCE

TXD BSCTE A

SCTE B

RXD A

RXD BRXC A

RXC B

TXC A

TXC B

RXC A

RXC B

RXD A

RXD B

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

SG

SHIELD

RTS A

RTS B

DTR A

21

25

18

DCE/DTE

M1

M0

DTR B

CTS A

CTS B

DSR A

DSR B

DCD A

DCD B

DSR A

DSR B

CTS A

CTS B

DCD A

DCD B

DTR A

DTR B

RTS A

RTS B

VCC

VCC

5.0V VCC

VCC

V CC

MO

M1

M2

V EE

VDD

C1 1.0µF

C3 1.0µF

C2 1.0µF C4 3.3µF

C5 1µF

C8 100pF

C7 100pF

C6 100pF

++ +

+

13

DCE/DTE

LTC1543

LTC1544

DCE/

DTE

M2M1M0

CHARGE PUMP

D1

D2

D3

R1

R2

R3

D1

D2

D3

R1

R2

R3

R4

D4

1544_04.eps

CABLE WIRING FOR MODE SELECTION

CABLE WIRING FOR DTE/DCE SELECTION

MODE PIN 18 MODE PIN 25

DTE PIN 7

DCE NC

PIN 21

V.35

RS449, V.36

RS232

PIN 7 PIN 7

NC PIN 7

PIN 7 NC

NC

21LATCH

+

Figure 4. Cable-selectable multiprotocol DTE/DCE port


DESIGN FEATURES

3 8 11 12

LTC1344A

V CC

MO

M1

M2

V EE

C8 100pF

C7 100pF

C6 100pF

13

DCE/

DTE

1

7

25

8

10

6

22

19

4

DTE_LL/ DCE_TM

DTE_TXD/ DCE_RXD

DTE_SCTE/ DCE_RXC

DTE_TXC/ DCE_TXC

DTE_RXC/ DCE_SCTE

DTE_RXD/ DCE_TXD

DTE_TM/ DCE_LL

DTE_RTS/ DCE_CTS

DTE_DTR/ DCE_DSR

DTE_DCD/ DCE_DCD

DTE_DSR/ DCE_DTR

DTE_CTS/ DCE_RTS

DTE_RL/ DCE_RL

M2DCE/DTE

M1M0

16

39

17

12

15

20

23

5

13

21

22

21

20

19

25

26

27GND

28VEE

24

23

18

17

16

15NC

11

24

14

2

18

29

28

27

26

21191817

24

30

31

32

33

34

37

36

35

38

39

41

4243

441

DB-25 CONNECTOR

2423222019171815161097645212

43

5

6

8

7

9

101213

14

12

3

4

5

6

7

M0M1M2

INVERT

DCE/DTE

8

911121314

10

14

TXD A

LL A TM A

DTE DCE

TXD B

SCTE A

SCTE B

RXD A

RXD B

RXC A

RXC B

TXC A

TXC B

RXC A

RXC B

RXD A

RXD B

TXC A

TXC B

SCTE A

SCTE B

TXD A

TXD B

TM A LL A

SG

SHIELD

RTS A

RTS B

DTR A

DTR B

CTS A

CTS B

DSR A

DSR B

DCD A

DCD B

DSR A

DSR B

CTS A

CTS B

RL A

DCD A

DCD B

DTR A

DTR B

RTS A

RTS B

RL A

VCC

5.0V VCC

VCC

VDD

C1 1.0µF

C3 1.0µF

C2 1.0µF C4 3.3µF

C5 1µF

++ +

+

LTC1343

LTC1544

CHARGE PUMP

15

16

20221125

4023

CTRLLATCHINVERT423SET

GND

DCEM2M1M0

ECLBLB

D1

D2

D3

D4

R1

R2

R3

R4

D1

D2

D3

R1

R2

R3

R4

D4

VCC

1544_05.eps

R1 100k

+

21LATCH

Figure 5. Controller-selectable multiprotocol DTE/DCE port with RLL, LL, TM and DB-25 connector


DESIGN IDEAS

High Clock-to-Center Frequency RatioLTC1068-200 Extends Capabilitiesof Switched Capacitor Highpass Filter

by Frank CoxThe circuit in Figure 1 is a 1kHz

8th order Butterworth highpass filterbuilt with the LTC1068-200, aswitched capacitor filter (SCF) build-ing block. In the past, commerciallyavailable switched capacitor filtershave had limited use as highpassfilters because of their sampled-datanature. Sampled-data systems gen-erate spurious frequencies when thesampling clock of the filter and theinput signal mix. These spurious fre-quencies can include sums anddifferences of the clock and the input,in addition to sums and differences oftheir harmonics. The input of thefilter must be band limited to removefrequencies that will mix with theclock and end up in the passband ofthe filter. Unfortunately, the pass-band of a highpass filter extendsupward in frequency by its verynature. If you have to band limit the

input signal too much you will alsolimit the passband of the filter, andhence its usefulness.

What makes this filter different isthe 200:1 clock-to-center frequencyratio (CCFR) and the internal sam-pling scheme of the LTC1068-200.Figure 2a shows the amplituderesponse of the filter plotted againstfrequency from 100Hz to 10kHz. Forcomparison, Figure 2b shows thesame filter built with an LTC1068-25.This is a 25:1 CCFR part. The 200:1CCFR filter delivers almost 30dB moreultimate attenuation in the stopband.A standard amplitude vs frequencyplot of a highpass filter can be mis-leading because it masks some of theaforementioned spurious signalsintroduced into the passband. Figure3a is a spectrum plot of the 200:1filter with a single 10kHz tone on theinput. This plot shows that the

INV B

HPB/NB

BPB

LPB

SB

NC

AGND

V+

NC

SA

LPA

BPA

HPA/NA

INV A

1

2

3

4

5

6

7

8

9

10

11

12

13

14

INV C

HPC/NC

BPC

LPC

SC

V–

NC

CLK

NC

SD

LPD

BPD

HPD/ND

INV D

28

27

26

25

24

23

22

21

20

19

18

17

16

15

LTC1068-200

RH3 1.47k

R22 10k

R32 24.3k

R42 10k

R44 16.9k

R34 10k

R24 16.9k

RH4 14.7k

R43 11.3k

R23 11.3k

R33 10k

R11 10k

R41 20k

R21 20k

R31 10k

–5V

200kHz

VOUT

5V

VIN

RH2 10k

0.1µF

0.1µF

Figure 1. LTC1068-200 1kHz 8th order Butterworth highpass filter


100Hz

10dB

/DIV

–10dB

DI_1068_02a. EPS

10kHz5kHz

Figure 2a. Amplitude vs frequency response ofFigure 1’s circuit

100Hz

10dB

/DIV

–10dB

DI_1068_02b. EPS

10kHz5kHz

Figure 2b. Amplitude vs frequency responseof comparable filter using the LTC1068-25

200Hz 100kHz

10dB

/DIV

–10dB

DI_1068_03a. EPS

200kHz

Figure 3a. Spectrum plot of Figure 1’s circuitwith a single 10kHz input


DESIGN IDEAS

The LT1533 switching regulator1, 2

achieves 100µV output noise by usingclosed-loop control around its out-put switches to tightly controlswitching transition time. Slowingdown switch transitions eliminateshigh frequency harmonics, greatlyreducing conducted and radiatednoise.

The part’s 30V, 1A output transis-tors limit available power. It is possibleto exceed these limits while main-taining low noise performance byusing suitably designed outputstages.

LT1533 Ultralow Noise SwitchingRegulator for High Voltage orHigh Current Applications

High Voltage Input RegulatorThe LT1533’s IC process limitscollector breakdown to 30V. A com-plicating factor is that the transformercauses the collectors to swing to twicethe supply voltage. Thus, 15V repre-sents the maximum allowable inputsupply. Many applications requirehigher voltage inputs; the circuit inFigure 1 uses a cascoded3 outputstage to achieve such high voltagecapability. This 24V to 5V (VIN = 20V–50V) converter is reminiscent ofprevious LT1533 circuits, except for

the presence of Q1 and Q2.4 Thesedevices, interposed between the ICand the transformer, constitute a cas-coded high voltage stage. They providevoltage gain while isolating the ICfrom their large drain voltage swings.

Normally, high voltage cascodesare designed to simply supply voltageisolation. Cascoding the LT1533 pre-sents special considerations becausethe transformer’s instantaneous volt-age and current information must beaccurately transmitted, albeit at loweramplitude, to the LT1533. If this isnot done, the regulator’s slew-control

SYNC

DUTY

SHDN

PGND

NFB

FBRVSLRCSL

LT1533

VINCOL A COL B14

2 15

16

8

7

4

3

11

5

6

10

1500pF

0.002µF

18k

0.01µF

0.002µF

L2

10µF

10k

1k

+

L1 100µH

L3 100µH

5VOUT

1312

7.5k 1%

2.49k 1%

220µF

MBRS140

L1, L3: COILTRONICS CTX100-3 L2: 22nH TRACE INDUCTANCE, FERRITE BEAD OR INDUCTOR COILCRAFT B-07T TYPICAL Q1, Q2: MTD6N15 T1: COILTRONICS VP4-0860

AN70 F40

100µF

CT

RT

VC

OPTIONAL SEE TEXT( )+10k

12k

GND

9

24VIN (20V TO 50V)

Q3 MPSA42

Q4 2N2222

4.7µF

10k

9

4

3

101

12

2

11

7

6 T1

5

8

Q21k

220Ω10k220Ω

MBRS140

+

+Q1

Figure 1. A low noise 24V to 5V converter (VIN = 20V–50V): cascoded MOSFETs withstand 100V transformer swings, permitting the LT1533 tocontrol 5V/2A output.

by Jim Williams


DESIGN IDEAS

A = 20V/DIV

B = 5V/DIV(AC COUPLED)

C = 100V/DIV

10µs/DIV

SHDN

DUTY

SYNC

COL A

COL B

PGND

RVSL

RCSL

FBNFB

LT1533

GND

VIN

5V

14

2

15

16

13

12

7

11

3

4

5

6

10

1500pF

18k

0.01µF

10k

R2 2.49k 1%

L2

4.7µF

10k

+T1 L1

300µH12V L3

33µH

89

R1 21.5k 1%

+ +100µF 100µF

1N5817

1N5817

1N4148

1N4148

AN70 F42

CT

RT

VC

OPTIONAL FOR LOWEST RIPPLE( )

330Ω

330Ω

0.05Ω

0.05Ω4.7µF+

Q2

Q10.003µF

680Ω

L1: COILTRONICS CTX300-4 L2: 22nH TRACE INDUCTANCE, FERRITE BEAD OR INDUCTOR. COILCRAFT B-07T TYPICAL L3: COILTRONICS CTX33-4 Q1, Q2: MOTOROLA D45C1 T1: COILTRONICS CTX-02-13949-X1 : FERRONICS FERRITE BEAD 21-110J

A = 5mV/DIV

B = 100µV/DIV

2µs/DIV

loops will not function, causing adramatic output noise increase. TheAC-compensated resistor dividersassociated with the Q1–Q2 gate-drainbiasing serve this purpose, prevent-ing transformer swings coupled viagate-channel capacitance fromcorrupting the cascode’s waveform-transfer fidelity. Q3 and associatedcomponents provide a stable DC ter-mination for the dividers whileprotecting the LT1533 from the highvoltage input.

Figure 2 shows that the resultantcascode response is faithful, even with100V swings. Trace A is Q1’s source;traces B and C are its gate and drain,respectively. Under these conditions,at 2A output, noise is inside 400µVpeak.

Current BoostingFigure 3 boosts the regulator’s 1Aoutput capability to over 5A. It doesthis with simple emitter followers (Q1–Q2). Theoretically, the followerspreserve T1’s voltage and currentwaveform information, permitting theLT1533’s slew-control circuitry tofunction. In practice, the transistorsmust be relatively low beta types. At3A collector current, their beta of 20sources ≈150mA via the Q1–Q2 basepaths, adequate for proper slew-loopoperation.5 The follower loss limitsefficiency to about 68%. Higher inputvoltages minimize follower-inducedloss, permitting efficiencies in the low70% range.

Figure 4 shows noise performance.Ripple measures 4mV (Trace A) usinga single LC section, with high fre-

quency content just discernible. Add-ing the optional second LC sectionreduces ripple to below 100µV (traceB), and high frequency content isseen to be inside 180µV (note ×50vertical scale-factor change).

Notes:

1 Witt, Jeff. The LT1533 Heralds a New Class ofLow Noise Switching Regulators. Linear Technol-ogy VII:3 (August 1997).

2 Williams, Jim. LTC Application Note 70: A Mono-lithic Switching Regulator with 100µV OutputNoise. October 1997.

3 The term “cascode,” derived from “cascade tocathode,” is applied to a configuration that placesactive devices in series. The benefit may be higherbreakdown voltage, decreased input capacitance,bandwidth improvement or the like. Cascodinghas been employed in op amps, power supplies,oscilloscopes and other areas to obtain perfor-mance enhancement.

4 This circuit derives from a design by Jeff Witt ofLinear Technology Corp.

5 Operating the slew loops from follower base cur-rent was suggested by Bob Dobkin of LinearTechnology Corp.

Figure 2. MOSFET-based cascode permits the regulator to control100V transformer swings while maintaining a low noise 5V output.Trace A is Q1’s source, Trace B is Q1’s gate and Trace C is the drain.Waveform fidelity through cascode permits proper slew-controloperation.

Figure 4. Waveforms for Figure 3 at 10W output: Trace A showsfundamental ripple with higher frequency residue just discernible. Theoptional LC section results in Trace B’s 180µVP-P wideband noiseperformance.

Figure 3. A 10W low noise 5V to 12V converter: Q1–Q2 provide 5A output capacity while preserving the LT1533’s voltage/current slew control.Efficiency is 68%. Higher input voltages minimize follower loss, boosting efficiency above 71%.


DESIGN IDEAS

A Complete Battery Backup SolutionUsing a Rechargeable NiCd Cell

by L.Y. Lin and S.H. Lim

Battery-powered systems, includ-ing notebook computers, personaldigital assistants (PDAs) and portableinstruments, require backup systemsto keep the memory alive while themain battery is being replaced. Themost common solution is to use anexpensive, nonrechargeable lithiumbattery. This solution requires low-battery detection, necessitates battery

access and invites inadvertent bat-tery removal. The LTC1558 batterybackup controller eliminates theseproblems by permitting the use of asingle, low cost 1.2V rechargeableNickel-Cadmium (NiCd) cell. TheLTC1558 has a built-in fast-/trickle-mode charger that charges the NiCdcell when main power is present.

Figure 1 shows a typical applica-tion circuit with an LTC1558-3.3providing backup power to anLTC1435 synchronous step-downswitching regulator. The backup cir-cuit components consist of the NiCdcell, R11–R14, C11–C12, L11 andQ11. SW11 and R15 provide a soft orhard reset function.

Figure 1. LTC1558 backup system with LTC1435 as main system regulator

C11 47µF 6.3V

L11† 22µH

SW

SW11

1

3

7

LTC1558-3.3

8

5

6

2

4

CTL

GND

FB

VCC

VBAK

RESET

BKUP

+

C12 1µF

FROM µP OPEN DRAIN SOFT RESET

TO µP

CIN 100µF 16V ×2

+

+C2 0.1µF

CC 330pF

CC2 51pF

C3 4.7µF 16V

Q2 Si4412DY

Q1 Si4412DY

+

BACKUP BATTERY NiCd††

1.2V

R14 10k

PUSH-BUTTON RESET

R13 100k

R15 12k

R11 51k 1%

Q11 Si4431DY

MAIN BATTERY 4.5V–10V

R12 21.2k

(20.0k 1% + 1.21k 1%)

VIN TG

SGND PGND

LTC1435

EXTVCC

SFB

VOSENSE

ITH

RUN/SS

COSC

SW

BOOST

INTVCC

SENSE+

SENSE–

BG

9

4

6

3

2

1

5 10

14

13 16

15

12

8

7

11

COSC 68pF

C5 1000pF

CSS 0.1µF

C4 0.1µF

C1 100pF

RC 10k

D1***

L1* 10µH

RSENSE** 0.033Ω

D2 MBRS140T3

COUT 100µF 10V ×2

+

R5 20k 1%

R1 35.7k 1%

C6 100pF

VOUT 3.3V

LOAD CURRENT 3A IN NORMAL MODE 30mA IN BACKUP MODE

SUMIDA CDRH125-100 IRC LR2010-01-R033-F CENTRAL CMDSH-3 SUMIDA CDRH73-220 SANYO CADNICA N-110AA

* **

*** †

††1558 01.eps


DESIGN IDEAS

Normal Mode (Operationfrom the Main Battery)During normal operation, theLTC1435 is powered from the mainbattery, which can range from 4.5V to10V (for example, a 2-series or 2-series × 2-parallel Li-Ion battery pack,or the like) and generates the 3.3Vsystem output. The LTC1558 oper-ates in standby mode. In standbymode, the LTC1558 BKUP (backup)pin is pulled low and P-channel MOS-FET Q11 is on. The NiCd cell is fastcharged by a 15mA current sourceconnected between the LTC1558’s VCCand SW pins. Once the NiCd cell isfully charged (according to theLTC1558’s gas-gauge counter), theLTC1558 trickle charges the NiCdcell. R14 sets the trickle-charge cur-rent according to the formula I(TRICKLE)= 10 • (VNiCd – 0.5)/R14. The trickle-charge current is set to overcome theNiCd cell’s self-discharge current,thereby maintaining the cell’s fullcharge.

Backup Mode (Operationfrom the Backup Battery)The main battery voltage is scaleddown through resistor divider R11–R12 and monitored by the LTC1558

via the FB pin. If the voltage on the FBpin drops 7.5% below the internal1.272V reference voltage (due to dis-charging or exchanging the mainbattery), the system enters backupmode. In backup mode, the LTC1558’sinternal switches and L11 form a syn-chronous boost converter thatgenerates a regulated 4V at VBAK. TheLTC1435 operates from this supplyvoltage to generate the 3.3V outputvoltage. The BKUP pin is pulled highby R13 and Q11 turns off , leaving its

BACKUP CELL VOLTAGE (V)1.00

OUTP

UT P

OWER

(mW

)

80

100

120

1.20 1.25 1.30 1.35 1.40

1558_02

60

40

01.05 1.10 1.15

20

180

160

140

VBAK = 4V VOUT = 3.3V

LOAD CURRENT (mA)0

0

BACK

UP T

IME

(MIN

S)

50

100

150

200

300

5 10 15 20

1558_03

25 30

250

VBAK = 4V VOUT = 3.3V

LTC1558’s undervoltage-lockoutfunction. Table 1 shows several val-ues of VFB vs the VBAK voltage. Figure2 shows the maximum output poweravailable at the 3.3V output vs theNiCd cell voltage. Over 100mW ofoutput power is achieved for a NiCdcell voltage greater than 1V. Figure 3shows the backup time vs the 3.3Vload current using a Sanyo CadnicaN-110AA cell (standard series with acapacity of 110mAhrs). Over one hourof backup time is realized for lessthan 80mW of 3.3V output power.

Recovery fromBackup Mode to Normal ModeWhen a new main battery pack isinserted into the system, Q11’s bodydiode forward biases. Once the volt-age at the FB pin increases to morethan 6% below VREF, the boost con-verter is disabled and the systemreturns to normal mode. The BKUPpin pulls low and turns Q11 back on.This allows the new battery pack tosupply input power to the LTC1435.The LTC1558 now accurately replen-ishes the amount of charge removedfrom the NiCd cell through the internalcharger and gas-gauge counter.

Figure 2. 3.3V output power vs backup cellvoltage

Figure 3. Backup time vs 3.3V outputload current

Table 1. VFB and VBAK voltages

%evitaleRVwoleB FER Vfo% FER V BF V KAB

%0– %001 V272.1

%6– %49 V691.1

%5.7– %5.29 V771.1

4.332V

4.073V

4.008V

Battery-powered systems,including notebook

computers, personal digitalassistants (PDAs) andportable instruments,

require backup systems tokeep the memory alive while

the main battery is beingreplaced. The most common

solution is to use anexpensive, nonrechargeable

lithium battery.

body diode reverse biased. The BKUPpin also alerts the system micropro-cessor. C11, a 47µ F capacitor,provides a low impedance bypass tohandle the boost converter’s tran-sient load current; otherwise, thevoltage drop across the NiCd cell’sinternal resistance would activate the

for the latest information

on LTC products, visit

www.linear-tech.comAuthors can be contacted

at (408) 432-1900


DESIGN IDEAS

Zero-Bias Detector Yields High Sensitivitywith Nanopower Consumption

by Mitchell Lee

RF ID tags, circuits that detect a“wake-up” call and return a burst ofdata, must operate on very low quies-cent current for months or years, yethave enough battery power in reserveto answer an incoming call. For small-est size, most operate in the ultrahighfrequency range, where the design ofa micropower receiver circuit is prob-lematic. Familiar techniques, such asdirect conversion, super regenerationor superhetrodyne, consume far toomuch supply current for long batterylife. A better method involves atechnique borrowed from simple field-strength meters: a tuned circuit anda diode detector.

Figure 1 shows the complete circuit,which was tested for proof-of-conceptat 445MHz. This circuit contains acouple of improvements over the stan-dard L/C-with-whip field-strengthmeter. Tuned circuits aren’t easilyconstructed or controlled at UHF, soa transmission line is used to matchthe detector diode (1N5712) to a quar-ter-wave whip antenna. The 0.23λtransmission-line section transformsthe 1pF (350Ω) diode junction capaci-tance to a virtual short at the base ofthe antenna. At the same time, itconverts the received antenna cur-rent to a voltage loop at the diode,giving excellent sensitivity.

Biasing the detector diode can im-prove sensitivity,1 but only when thediode is loaded by an external DCresistance. Careful curve-tracerexamination of the 1N5712 at theorigin reveals that it follows the idealdiode equation, with scales of milli-volts and nanoamperes. To use azero-bias diode at the origin, the ex-ternal comparator circuitry must notload the rectified output.

The LTC1540 nanopower compara-tor and reference is a good choice forthis application because it not onlypresents no load to the diode, but alsodraws only 300nA from the battery.This represents a 10-times improve-ment in battery life over biaseddetector schemes.2 The input isCMOS, and input bias currentconsists of leakage in a small ESD-protection cell connected between theinput and ground. The input leakagemeasures in the picoampere range,whereas the 1N5712 leaks hundredsof picoamperes. Any rectified outputfrom the diode is loaded by the diodeitself, not by the LTC1540, and thesensitivity can match that of a loaded,biased detector.

The rectified output is monitoredby the LTC1540 comparator. TheLTC1540’s internal reference is usedto set up a threshold of about 18mV

at the inverting input. A rising edge atthe comparator output triggers a one-shot, which temporarily enablesanswer-back and any other pulsedfunctions.

Total supply current is 400nA, con-suming just 7mAH battery life over aperiod of five years. Monolithic one-shots draw significant load current,but the ’4047 is about the best in thisrespect. A one-shot constructed fromdiscrete NAND gates draws negligiblepower.

Sensitivity is excellent, and thecircuit can detect about 200mW froma reference dipole at 100 feet. Range,of course, depends on operating fre-quency, antenna orientation andsurrounding obstacles. Sensitivity isindependent of supply voltage; thisreceiver will work just as well with a9V battery as with a single lithiumcell.

The length of the transmission linedoes not scale with frequency. Owingto a decrease in diode reactance, theelectrical length will shorten as fre-quency increases. Adjust the linelength for minimum feed-pointimpedance at the operating frequency.If an impedance analyzer is used tomeasure the line, a 1pF capacitor canbe substituted for the diode to avoidlarge signal effects in the diode itself.Consult the manufacturer’s data sheetfor accurate characterization of diodeimpedance at the frequency ofinterest.

–

+CMOS ONE-SHOT

(CD4047)

Q

QLTC1540

12M

180k10nF10nF

10kFB

O.23λ

1N5712

λ/4

2V–11V

3

4

56

78

21

Figure 1. Nanopower field detector

Notes:

1. Eccles, W.H. Wireless Telegraphy and Telephony,Second Edition. Ben Brothers Limited, London,1918, page 272.

2. Lee, Mitchell. “Biased Detector Yields High Sen-sitivity with Ultralow Power Consumption.” LinearTechnology VII:1(February 1997), page 21.


DESIGN INFORMATION

Micropower Octal 10-Bit DAC ConservesBoard Space with SO-8 Footprint

IntroductionHistorically, many circuits have reliedon potentiometers for adjustment orcontrol. Increasingly, microcontrol-lers and microprocessors are findingapplications in these circuits. Theinclusion of processors can eliminatepotentiometers, replacing them withdigital-to-analog converters (DACs).Fulfilling this need is the LTC1660.

Features

Eight DACs in 0.045in2

The LTC1660 is the latest multichan-nel DAC from Linear Technology. This10-bit, voltage-output, octal DAC isdesigned to conserve board space.Packaged in a 16-pin narrow SSOP, ithas an 8-pin SO footprint. Figure 1 isa block diagram showing theLTC1660’s major circuit features.

Inherent 10-BitMonotonicity and Linearity(DNL) PerformanceThe LTC1660 uses a DAC architec-ture that features excellent ±0.5dBdif ferential linearity accuracy,ensuring inherently monotonic per-formance. This is important forclosed-loop control applications, sincenonmonotonic operation compro-mises loop stability. Figures 2a and2b show the LTC1660’s INL and DNLperformance, respectively.

Reference InputThe LTC1660 uses a single externalreference voltage for all its internalDACs. This voltage sets its full-scaleoutput range. The reference voltagemagnitude has a range of 0V to VCC.Figure 3 shows a micropower LT1460-2.5 voltage reference setting theLTC1660’s full-scale output to 2.5V.

Rail-to-Rail Output AmplifiersEach internal DAC has an amplifierthat buffers its output. The amplifi-ers’ output voltage can swingrail-to-rail; they can source or sinkup to 5mA while maintaining guaran-teed linearity and monotonicityperformance. Additionally, theamplifiers can easily drive 1000pFand remain stable. Higher capacitiveloads (such as 0.1µF) can be drivenby placing a small value resistor (100Ωtypical) in series with the output pin.

Single Supply, 60µA per DACThe LTC1660 maintains its specifiedoperation over the wide supply rangeof 2.7V to 5.5V. To ensure efficientoperation on this supply range, thetotal typical supply current drawn isjust 480µA. The wide supply rangeand low current requirements makethis DAC ideal for battery-poweredapplications.

by Kevin R. Hoskins

DAC H

DAC G

DAC F

DAC E

DAC A

DAC B

DAC C

DAC D

ADDRESS DECODERCONTROL LOGIC

SHIFT REGISTER

2 VOUT A

3 VOUT B

4 VOUT C

5 VOUT D

VOUT H 15

VOUT G 14

VOUT F 13

VOUT E 12

LTC1660

1

6

7

8

11

9

GND

CS/LD

CLK

CLR

DIN

REF

16

10

VCC

DOUT



DESIGN INFORMATION

SLEEP ModeFurther power saving is possible whenthe LTC1660 is placed in SLEEP mode.Activating SLEEP mode shuts off allinternal bias currents and places theoutput amplifiers in a high imped-ance state. The SLEEP mode reducescurrent consumption to 1µA or less.The digital circuitry remains active,retaining the stored values for eachDAC. There are two ways to take thepart out of SLEEP mode: loading anyADDRESS/CONTROL value otherthan SLEEP mode or applying a logiclow to the CLR pin. The last techniqueawakens the LTC1660 and sets alleight outputs to 0V.

Serial InterfaceThe eight internal DACs are addressedindividually over a 3-wire, SPI-com-patible interface. The three signalsare Chip Select/Load (CS/LD), SerialClock (CLK) and Data In (DIN).

Schmitt Trigger InputsThe LTC1660’s Schmitt trigger digitalinputs prevent false triggers whenresponding to noisy signals or thosehaving slow rise or fall times. Thisquality makes the LTC1660 ideal forremote placement at the end of longserial transmission lines or lines thatuse optoisolators.

DOUT Daisy ChainAnother feature of the LTC1660’s se-rial interface is its DOUT pin. Thecurrent contents of the internal shiftregister are shifted out on this pin asnew data is shifted in on the DIN pin.This pin makes it possible to connect

multiple LTC1660s and other LTCDACs to the same serial data line. Thedaisy chain is linked by connecting apart’s DOUT pin to the DIN pin of thenext part in the chain. The advan-tages of the single serial data lineinclude reduced circuit board space,reduced radiation that results fromfewer circuit traces and conservationof limited microcontroller or micro-processor I/O lines.

Power-On ResetThe LTC1660’s power-on reset en-sures that the output voltage on eachDAC is set to 0V when power (2.7V–5.5V) is first applied to the VCC pin.

lortnoC/sserddAnoitcA

tiB 41 tiB 31 tiB 21 tiB 11

0 0 0 0 etadpUoN0 0 0 1 ACADdaoL0 0 1 0 BCADdaoL0 0 1 1 CCADdaoL0 1 0 0 DCADdaoL0 1 0 1 ECADdaoL0 1 1 0 FCADdaoL0 1 1 1 GCADdaoL1 0 0 0 HCADdaoL1 0 0 1 enoN1 0 1 0 enoN1 0 1 1 enoN1 1 0 0 enoN1 1 0 1 enoN1 1 1 0 edoMPEELS1 1 1 1 edoctib-01emasehthtiwsSCADlladaoL

Table 1. DAC address/control functions

Asynchronous CLEARThis active low input will asynchro-nously reset all eight DAC outputs to0V when a logic low is applied to thispin. It also deactivates the SLEEPmode.

ApplicationsThe LTC1660 shines brightly inapplications that take advantage ofits micropower, l inearity andversatility. The applications includeoffset and gain adjust in industrialcontrol systems and AGC and transmitpower adjustment in wirelesscommunication.

VOUT A

VOUT B

VOUT C

VOUT D

VOUT E

VOUT F

VOUT G

VOUT H

2

3

4

5

12

13

14

15

16

6

1

11

7

8

9

10

VCC

REF

GND

CLR

CS/LD

CLK

DIN

DOUT

LT1460-2.5

16k

5V

0.1µF

0.1µF

LTC1660

SERIAL INTERFACE

Figure 3. An LT1460 2.5V reference sets theLTC1660’s full-scale output to 2.5V.CODE

0

INL

ERRO

R (L

SB)

0

0.50

1024

1660_XX.EPS

–0.50

–1.00

0.25

0.75

–0.25

–0.75

256 512 768128 384 640 896

1.00

CODE0

DNL

ERRO

R (L

SB)

0

0.50

1024

1660_YY.EPS

–0.50

–1.00

0.25

0.75

–0.25

–0.75

256 512 768128 384 640 896

1.00

Figure 2a. LTC1660 integral nonlinearityerror

Figure 2b. LTC1660 differential nonlinearityerror



DESIGN INFORMATION

Tiny MSOP Dual Switch Driveris SMBus Controlled by Peter Guan

IntroductionThe LTC1623 SMBus™ switchcontroller offers an inexpensive,space-saving alternative for control-ling peripherals in today’s complexportable computer systems. Pin-to-pin connections between the systemcontroller and each peripheral devicenot only result in complicated wiring,but also limit the number and type ofperipheral devices connected to thesystem controller. Using the SMBusarchitecture, the LTC1623 eliminatesthese problems by requiring only twobus wires and allowing easy upgradesand additions of new peripherals.

The SMBusThe SMBus is a low power serial busdeveloped by Intel and Duracell. Onlytwo bus lines, DATA and CLK, areneeded to establish a set of protocolsfor communication between the busmaster and slaves. Using the SENDBYTE protocol of the SMBus to re-ceive and execute commands fromthe bus master, each LTC1623 con-trols the operation of two independentexternal switches. To identify itselfon the SMBus, the LTC1623 has twothree-state address pins. In otherwords, up to eight LTC1623s can beprogrammed to control up to sixteendifferent switches.

LTC1623 Design InformationA timing diagram of the SEND BYTEprotocol is shown in Figure 1. Afterdetecting the Start signal from thebus master (a high-to-low transitionon the DATA line while CLK is high),the LTC1623 shifts in the addressbyte, which consists of seven address

bits and one read/write bit. If theaddress byte matches, the LTC1623acknowledges the master and thenshifts in the command byte whose twoLSBs are the controlling signals forthe two external switches. Afterwards,the LTC1623 again acknowledges themaster so that the master can termi-nate the transaction by sending aStop signal (a DATA transition fromlow to high while CLK is high).

The LTC1623 adheres strictly tothe SMBus specification of 0.6V VILand 1.4V VIH over the entire operatingrange of 2.7V to 5.5V. The two built-incharge pump triplers with micropowerfeedback networks guarantee full en-hancement of the two external

CLK

STARTDATA

1 1 10 0 0 0 0 0 0 0 0 0 0 1

(GB ON)(GA ON)

1623 TD02COMMAND BYTEADDRESS BYTE

1 ACK STOPACK(PROGRAMMABLE) (WRITE)

VCC 2.7V TO 5.5V

10µF

(PROGRAMMABLE)

PRINTERDISPLAY

1623 F02

(FROM SMBus)

LTC1623

GND

VCC

AD0

AD1

CLK

DATA

GA

GB0.1µF

Q1 Si3442DV

Q1 Si3442DV

0.1µF

1k

1k

10µF5V

1623 TA02

LTC1623

GND

VCC

AD0

AD1

CLK

DATA

GA

GB

0.1µF

0.1µF

1µF

Q1 Si3442DV

Q2*

Q3*

1k

1k

3.3V

10k

TO PC CARD VCC 0V/3.3V/5V

*1/2 Si6926DQ

logic-level MOSFET switches withoutexcess gate overdrive. The output gate-drive voltage is regulated to amaximum of 6V above VIN.

ApplicationsThe main application of the LTC1623is to control two external high-side N-channel switches (Figure 2). As seenin the figure, a 0.1µF capacitor and a1k resistor are placed on each gate-drive output to respectively slow downthe turn-on time of the external switchand to eliminate any oscillationscaused by the parasitic capacitanceof the external switch and the para-sitic inductance of the connectingwires.

Figure 1. SMBus SEND BYTE protocol timing diagram

Figure 2. LTC1623 controlling two high-side switches

Figure 3. PC Card 3.3V/5V switch matrix.

SMBus is a trademark of Intel Corp.


CONTINUATIONS

VCC 2.7V TO 5.5V

10µF

(PROGRAMMABLE)

FANDISPLAY

1623 F02

(FROM SMBus)

LTC1623

GND

VCC

AD0

AD1

CLK

DATA

GA

GB0.1µF

Q1 Si3442DV

Q2 Si6433DQ

0.1µF

1k

1k

Figure 4. LTC1623 controlling a P-channel switch (Q2)

Tracking the growing popularity ofportable communication systems, theLTC1623 makes a very handy single-slot 3.3V/5V PC Card switch matrix.As shown in Figure 3, this circuitenables a system controller to switcheither a 3.3V or a 5V supply to any ofits SMBus-addressed peripherals.Besides N-channel switches, theLTC1623 can also be used to controla P-channel switch, as shown in Fig-ure 4. As a result, the load connectedto the P-channel switch will be turnedon upon power-up of the LTC1623,whereas the other load must wait fora valid address and command to bepowered.

The mode pins are routed to theconnector and are left unconnected(1) or wired to ground (0) in the cable.The internal pull-up current sourcesensure a binary 1 when a pin is leftunconnected and also ensure thatthe LTC1543/LTC1544/LTC1344Aenter the no-cable mode when thecable is removed. In the no-cablemode, the LTC1543/LTC1544 powersupply current drops to less than200µ A and all of the LTC1543/LTC1544 driver outputs will be forcedinto the high impedance state.

Adding Optional Test SignalIn some cases, the optional test sig-nals local loopback (LL), remoteloopback (RL) and test mode (TM) arerequired but there are not enoughdrivers and receivers available in the

LTC1543/LTC1544 to handle theseextra signals. The solution is to com-bine the LTC1544 with the LTC1343.By using the LTC1343 to handle theclock and data signals, the chip setgains one extra single-ended driver/receiver pair. This configuration isshown in Figure 5.

Compliance TestingA European standard EN 45001 testreport is available for the LTC1543/LTC1544/LTC1344A chip set. Thereport provides documentation on thecompliance of the chip set to Layer 1of the NET1 and NET2 standard. Acopy of this test report is availablefrom LTC or from Detecon, Inc. at1175 Old Highway 8, St. Paul, MN55112.

ConclusionIn the world of network equipment,the product differentiation is mostlyin the software and not in the serialinterface. The LTC1543, LTC1544 andLTC1344A provide a simple yet com-prehensive solution to standardscompliance for multiple-protocolserial interface.

LTC1543, continued from page 17

ConclusionWith a standby current of only 17µAand a tiny 8-lead MSOP (or SO) foot-print, the LTC1623 offers a simple

and efficient solution for managingsystem peripherals using the SMBusarchitecture.

Quadruple 3rd Order 100kHzButterworth Lowpass FilterAnother example of the flexibility ofthe virtual-ground inputs is the abil-ity to add an extra, independent realpole by replacing the input resistor inFigure 2 with an R-C-R “T” network.In Figure 10, a 10k input resistor hasbeen split into two parts and theparallel combination of the two formsa 100kHz real pole with the 680pF

external capacitor. Four such 3rd or-der Butterworth lowpass filters canbe built from one LTC1562. The sametechnique can add additional realpoles to other filter configurations aswell, for example, augmenting Figure4’s circuit to obtain a dual 5th orderfilter from a single LTC1562.

LTC1562 continued from page 5

ConclusionThe LTC1562 is the first truly com-pact universal active filter, yet it offersinstrumentation-grade performancerivaling much larger discrete-compo-nent designs. It serves applicationsin the 10kHz–150kHz range with anSNR as high as 100dB or more (16+equivalent bits). The LTC1562 is idealfor modems and other communica-tions systems and for DSP antialiasingor reconstruction filtering.

Authors can be contacted at (408) 432-1900


Accessing the FunctionalityTable 1 shows the DAC ADDRESS/CONTROL codes that update each ofthe DACs, activate the SLEEP mode,cause “No Update”, or update all DACswith the same 10-bit value.

The four MSBs (Bit15–Bit12) of the16-bit data word sent to the LTC1660select a DAC for updating or a controlfunction such as SLEEP. The next tenbits (Bit11–Bit2) are the data that setsthe selected DAC’s output voltage.For example, with a 2.5V referencevoltage applied to the LTC1660’s pin6, a value of 819 (1100110011) onBit11–Bit2 sets the DAC’s output volt-age to 819/1024 • 2.5V, = 2.0V. Thelast two bits (Bit1–Bit0) are “don’t care.”When a 4-bit “no update” code is sent(Bit15–Bit12 = 0000 and 1001–1101),the contents of Bit11–Bit0 are ignored.The SLEEP mode is selected by send-ing Bit15–Bit12 = 1110. The LTC1660is awakened by applying a logic low tothe CLR pin or by completing a dataload cycle. To awaken the part with aload cycle and return to the same

output voltages as before SLEEP, useaddress/control locations Bit15–Bit12= 0000 or 1001–1101. Using CLR toawaken the LTC1660 changes thecontents of all DAC registers to zerosand the output voltage to 0V. Finally,all DACs can be forced to the sameoutput voltage by using address/con-trol location Bit15–Bit12 = 1111.

Layout, Bypassing andGrounding ConsiderationsLike all data converters, the LTC1660performs best when it is properlygrounded, bypassed and placed on aPCB layout optimized for low noise.Proper grounding is achieved by plac-ing the part over an analog groundplane. Ideally, no traces should cutthrough the analog ground plane. If adigital ground plane is present, itshould make contact with the analogground plane at only one point, usu-ally where the board is grounded tothe power supply ground. If the boardconsists of multiple layers, the digital

and analog ground planes should notoverlap each other. The ground pin(pin 1) should be connected to theanalog ground plane.

Two 0.1µ F bypass capacitorsshould be connected between theLTC1660 and the analog groundplane. One capacitor is connected tothe VCC input (pin 16) and the other isconnected to the reference input (pin6). Lead lengths should be as short aspossible.

To help ensure that digital switch-ing noise does not contaminate theanalog output, pins 7–11 should beplaced over the digital ground planeand not cross the analog ground plane.

ConclusionThe LTC1660 10-bit octal DAC fea-tures a very small narrow SSOP-16package, micropower operation andpower saving SLEEP mode. These fea-tures make this the ideal part fordense circuit boards and battery-pow-ered applications.

spurious free dynamic range (SFDR)of the LTC1068 highpass filter is inexcess of 70dB. In fact, the filter hasa 70dB SFDR for all input signals upto 100kHz. In a 200kHz sampled-data system, you would normally needto band limit the input below 100kHz,

200Hz 100kHz

10dB

/DIV

–10dB

DI_1068_03b. EPS

200kHz 100Hz

10dB

/DIV

–10dB

DI_1068_04. EPS

25kHz12.5kHz

the Nyquist frequency. Because theLTC1068 uses double sampling tech-niques, its useful input frequencyrange extends to the Nyquist fre-quency and even above, albeit withsome care. Figure 3b shows theLTC1068-200 highpass filter with aninput frequency of 150kHz. There is aspurious signal at 50kHz, but eventhough there is no input filtering, theSFDR is still 60dB. For input signalsfrom 100kHz to 150kHz, the filterdemonstrates an SFDR of at least60dB. The SFDR plot of the samefilter built with the LTC1068-25 isshown in Figure 4. Note that the lowerCCFR (25:1) part still manages arespectable 55dB SFDR with a 10kHzinput. The LTC1068-25 is used pri-marily for band-limited applications,such as lowpass and bandpassfilters.

LTC1068-200 continued from page 23

Figure 3b. Spectrum plot of Figure 1’s circuitwith a single 150kHz input

Figure 4. Spectrum plot of a comparable filterusing the LTC1068-25 with a single 10kHzinput shows a respectable 55dB SFDR.

Note:

The filters for this article were designed usingLinear Technology’s FilterCAD™ (version 2.0) forWindows®. This program made the design andoptimization of these filters fast and easy.

LTC1660 continued from page 30

CONTINUATIONS


NEW DEVICE CAMEOS

Ultralow IQ LTC1474,LTC1475 Stepdown DC/DCConverter Family GrowsThe LTC1474/LTC1475 family hasbeen expanded to cover a completerange of output voltage, package andoperating-temperature options. Allmembers of the family feature 3V to18V (20V Absolute Maximum) opera-tion, 10µA typical quiescent currentand programmable peak inductor cur-rent. The LTC1474 is controlled by arun pin and features a low-batterycomparator that remains active inshutdown. The LTC1475 adds an on/off latch, allowing push-button con-trol of power.

Both the LTC1474 and LTC1475are available with 3.3V, 5V or adjust-able output voltages. All versions areoffered in two packages: the industry-standard small outline 8-pin plasticpackage and the tiny 8-pin MSOPpackage. MSOP-packaged parts arespecified for the commercial tempera-ture range, whereas all LTC1474 S8versions and the LTC1475 S8 adjust-able version are also available specifiedfor the industrial temperature range(see table).

noitpO 8SMC 8SC 8SI

JDA-4741CTL

3.3-4741CTL

5-4741CTL

JDA-5741CTL

3.3-5741CTL

5-5741CTL

Every member of the LTC1474/LTC1475 family features operatingefficiencies exceeding 90% and a com-bination of cycle-by-cycle inductorcurrent control and ultralow quies-cent current previously unavailablein switching regulators. Strapping twopins together defines a 400mA peakinductor current with no externalcurrent sense resistor, allowing up to300mA output currents. Adding aninexpensive external resistor allowsthe user to program the peak inductorcurrent to as low as 10mA for efficientlow current operation with smallinductors.

The LTC1474/LTC1475 are idealfor many quiescent-current-sensitiveapplications, such as battery-pow-ered, handheld devices, keep-alivepower supplies and industrial 4–20mAloops.

LT1534 Ultralow Noise2A RegulatorThe LT1534 is the next in the line of“stealth switchers,” DC/DC convert-ers designed to significantly reduceconducted and radiated electromag-netic interference (EMC, EMI). Byadjusting the output switch voltageand current slew rates, noise can bereduced to unprecedented levels.These converters can then be used togenerate power in applications thatpreviously excluded switchers,including precision instrumentationsystems, medical instruments, single-board data acquisition systems and

wireless communications. TheLT1534 is specifically designed forsingle-output topologies such asboost, SEPIC and Cuk.

The LT1534 uses a current modearchitecture; it includes a single 2Apower switch along with all necessaryoscillator, control and protection cir-cuitry. Unique error amp circuitrycan regulate both positive and nega-tive voltages. The internal oscillatormay be synchronized to an externalclock. Protection features includecycle-by-cycle short-circuit protec-tion, undervoltage lockout andthermal shutdown. Low shutdowncurrent (12µA typical) and low mini-mum input voltage requirements(2.7V) make this part suitable forbattery-operated applications. TheLT1534 is offered in an SO-16 pack-age in a commercial temperaturegrade.

The user can independently adjustthe output switch current slew rateand voltage slew rate. This allows theuser to optimally trade off noise andefficiency. Because the slew controlreduces the source of switcher noise,it can reduce or eliminate the need forpower supply shielding and filteringcomponents.

New Device Cameos

For further information on anyof the devices mentioned in thisissue of Linear Technology, usethe reader service card or callthe LTC literature servicenumber:

1-800-4-LINEAR

Ask for the pertinent data sheetsand Application Notes.


DESIGN TOOLS

Applications on DiskNoise Disk — This IBM-PC (or compatible) programallows the user to calculate circuit noise using LTC opamps, determine the best LTC op amp for a low noiseapplication, display the noise data for LTC op amps,calculate resistor noise and calculate noise using specsfor any op amp. Available at no charge

SPICE Macromodel Disk — This IBM-PC (or compat-ible) high density diskette contains the library of LTCop amp SPICE macromodels. The models can be usedwith any version of SPICE for general analog circuitsimulations. The diskette also contains working circuitexamples using the models and a demonstration copyof PSPICE™ by MicroSim. Available at no charge

SwitcherCAD™ — The SwitcherCAD program is a pow-erful PC software tool that aids in the design andoptimization of switching regulators. The program cancut days off the design cycle by selecting topologies,calculating operating points and specifying compo-nent values and manufacturer’s part numbers. 144page manual included. $20.00

SwitcherCAD supports the following parts: LT1070series: LT1070, LT1071, LT1072, LT1074 and LT1076.LT1082. LT1170 series: LT1170, LT1171, LT1172 andLT1176. It also supports: LT1268, LT1269 and LT1507.LT1270 series: LT1270 and LT1271. LT1371 series:LT1371, LT1372, LT1373, LT1375, LT1376 andLT1377.

Micropower SwitcherCAD™ — The MicropowerSCADprogram is a powerful tool for designing DC/DC con-verters based on Linear Technology’s micropowerswitching regulator ICs. Given basic design param-eters, MicropowerSCAD selects a circuit topology andoffers you a selection of appropriate Linear Technologyswitching regulator ICs. MicropowerSCAD also per-forms circuit simulations to select the other componentswhich surround the DC/DC converter. In the case of abattery supply, MicropowerSCAD can perform a bat-tery life simulation. 44 page manual included.

$20.00

MicropowerSCAD supports the following LTC micro-power DC/DC converters: LT1073, LT1107, LT1108,LT1109, LT1109A, LT1110, LT1111, LT1173, LTC1174,LT1300, LT1301 and LT1303.

Technical Books1990 Linear Databook, Vol I —This 1440 page collec-tion of data sheets covers op amps, voltage regulators,references, comparators, filters, PWMs, data conver-sion and interface products (bipolar and CMOS), inboth commercial and military grades. The catalogfeatures well over 300 devices. $10.00

1992 Linear Databook, Vol II — This 1248 pagesupplement to the 1990 Linear Databook is a collectionof all products introduced in 1991 and 1992. Thecatalog contains full data sheets for over 140 devices.The 1992 Linear Databook, Vol II is a companion to the1990 Linear Databook, which should not be discarded.

$10.00

1994 Linear Databook, Vol III —This 1826 page supple-ment to the 1990 and 1992 Linear Databooks is acollection of all products introduced since 1992. A totalof 152 product data sheets are included with updatedselection guides. The 1994 Linear Databook Vol III is acompanion to the 1990 and 1992 Linear Databooks,which should not be discarded. $10.00

1995 Linear Databook, Vol IV —This 1152 page supple-ment to the 1990, 1992 and 1994 Linear Databooks isa collection of all products introduced since 1994. Atotal of 80 product data sheets are included withupdated selection guides. The 1995 Linear DatabookVol IV is a companion to the 1990, 1992 and 1994Linear Databooks, which should not be discarded.

$10.00

1996 Linear Databook, Vol V —This 1152 page supple-ment to the 1990, 1992, 1994 and 1995 LinearDatabooks is a collection of all products introducedsince 1995. A total of 65 product data sheets areincluded with updated selection guides. The 1996Linear Databook Vol V is a companion to the 1990,1992, 1994 and 1995 Linear Databooks, which shouldnot be discarded. $10.00

1997 Linear Databook, Vol VI —This 1360 page supple-ment to the 1990, 1992, 1994, 1995 and 1996 LinearDatabooks is a collection of all products introducedsince 1996. A total of 79 product data sheets areincluded with updated selection guides. The 1997Linear Databook Vol VI is a companion to the 1990,1992, 1994, 1995 and 1996 Linear Databooks, whichshould not be discarded. $10.00

1990 Linear Applications Handbook, Volume I —928 pages full of application ideas covered in depth by40 Application Notes and 33 Design Notes. This catalogcovers a broad range of “real world” linear circuitry. Inaddition to detailed, systems-oriented circuits, thishandbook contains broad tutorial content together withliberal use of schematics and scope photography. Aspecial feature in this edition includes a 22-page sec-tion on SPICE macromodels. $20.00

1993 Linear Applications Handbook, Volume II —Continues the stream of “real world” linear circuitryinitiated by the 1990 Handbook. Similar in scope to the1990 edition, the new book covers Application Notes40 through 54 and Design Notes 33 through 69. Refer-ences and articles from non-LTC publications that wehave found useful are also included. $20.00

1997 Linear Applications Handbook, Volume III —This 976 page handbook maintains the practical outlookand tutorial nature of previous efforts, while broaden-ing topic selection. This new book includes ApplicationNotes 55 through 69 and Design Notes 70 through 144.Subjects include switching regulators, measurementand control circuits, filters, video designs, interface,data converters, power products, battery chargers andCCFL inverters. An extensive subject index referencescircuits in LTC data sheets, design notes, applicationnotes and Linear Technology magazines. $20.00

Interface Product Handbook — This 424 page hand-book features LTC’s complete line of line driver and

receiver products for RS232, RS485, RS423, RS422,V.35 and AppleTalk® applications. Linear’s particularexpertise in this area involves low power consumption,high numbers of drivers and receivers in one package,mixed RS232 and RS485 devices, 10kV ESD protec-tion of RS232 devices and surface mount packages.

Available at no charge

Power Solutions Brochure — This 84 page collectionof circuits contains real-life solutions for commonpower supply design problems. There are over 88circuits, including descriptions, graphs and perfor-mance specifications. Topics covered include batterychargers, PCMCIA power management, microproces-sor power supplies, portable equipment power supplies,micropower DC/DC, step-up and step-down switchingregulators, off-line switching regulators, linear regula-tors and switched capacitor conversion.


High Speed Amplifier Solutions Brochure —This 72 page collection of circuits contains real-lifesolutions for problems that require high speedamplifiers. There are 82 circuits including descrip-tions, graphs and performance specifications. Topicscovered include basic amplifiers, video-related appli-cations circuits, instrumentation, DAC and photodiodeamplifiers, filters, variable gain, oscillators and currentsources and other unusual application circuits.


Data Conversion Solutions Brochure — This 52 pagecollection of data conversion circuits, products andselection guides serves as excellent reference for thedata acquisition system designer. Over 60 productsare showcased, solving problems in low power, smallsize and high performance data conversion applica-tions—with performance graphs and specifications.Topics covered include ADCs, DACs, voltage refer-ences and analog multiplexers. A complete glossarydefines data conversion specifications; a list of se-lected application and design notes is also included.


Telecommunications Solutions Brochure — This 72page collection of circuits, new products and selectionguides covers a wide variety of products targeted forthe telecommunications industry. Circuits solving reallife problems are shown for central office switching,cellular phone, base station and other telecom applica-tions. New products introduced include high speedamplifiers, A/D converters, power products, interfacetransceivers and filters. Reference material includes atelecommunications glossary, serial interface stan-dards, protocol information and a complete list of keyapplication notes and design notes.



DESIGN TOOLS

Information furnished by Linear Technology Corporationis believed to be accurate and reliable. However, LinearTechnology makes no representation that the circuitsdescribed herein will not infringe on existing patent rights.


Acrobat is a trademark of Adobe Systems, Inc.; Windowsis a registered trademark of Microsoft Corp.; Macintoshand AppleTalk are registered trademarks of Apple Com-puter, Inc. PSPICE is a trademark of MicroSim Corp.

CD-ROMLinearView — LinearView™ CD-ROM version 2.0 isLinear Technology’s latest interactive CD-ROM. It al-lows you to instantly access thousands of pages ofproduct and applications information, covering LinearTechnology’s complete line of high performance ana-log products, with easy-to-use search tools.

The LinearView CD-ROM includes the complete prod-uct specifications from Linear Technology’s Databooklibrary (Volumes I–V) and the complete ApplicationsHandbook collection (Volumes I–III). Our extensivecollection of Design Notes and the complete collectionof Linear Technology magazine are also included.

A powerful search engine built into the LinearView CD-ROM enables you to select parts by various criteria,such as device parameters, keywords or part numbers.All product categories are represented: data conver-sion, references, amplifiers, power products, filtersand interface circuits. Up-to-date versions of LinearTechnology’s software design tools, SwitcherCAD,

DESIGN TOOLS, continued from page 39 Micropower SwitcherCAD, FilterCAD, Noise Disk andSpice Macromodel library, are also included. Every-thing you need to know about Linear Technology’sproducts and applications is readily accessible viaLinearView. LinearView 2.0 runs under Windows® 3.1,Windows 95 and Macintosh® System 7.0 or later.

Available at no charge.

World Wide Web SiteLinear Technology Corporation’s customers can nowquickly and conveniently find and retrieve the latesttechnical information covering the Company’s prod-ucts on LTC’s new internet web site. Located atwww.linear-tech.com, this site allows anyone withinternet access and a web browser to search throughall of LTC’s technical publications, including data sheets,application notes, design notes, Linear Technologymagazine issues and other LTC publications, to findinformation on LTC parts and applications circuits.Other areas within the site include help, news andinformation about Linear Technology and its salesoffices.

Other web sites usually require the visitor to downloadlarge document files to see if they contain the desiredinformation. This is cumbersome and inconvenient. Tosave you time and ensure that you receive the correctinformation the first time, the first page of each datasheet, application note and Linear Technology maga-zine is recreated in a fast, download-friendly format.This allows you to determine whether the document iswhat you need, before downloading the entire file.

The site is searchable by criteria such as part numbers,functions, topics and applications. The search is per-formed on a user-defined combination of data sheets,application notes, design notes and Linear Technologymagazine articles. Any data sheet, application note,design note or magazine article can be downloaded orfaxed back. (Files are downloaded in Adobe Acrobat™PDF format; you will need a copy of Acrobat Reader toview or print them. The site includes a link from whichyou can download this program.)

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