linear technologlinear technology - analog devices...linear technology enters the delta-sigma1, 2...

LINEAR TECHNOLOGYLINEAR TECHNOLOGYLINEAR TECHNOLOGYNOVEMBER 1998 VOLUME VIII NUMBER 4

, LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load,FilterCAD, Hot Swap, LinearView, Micropower SwitcherCAD, No RSENSE, PolyPhase, SwitcherCAD and UltraFast aretrademarks of Linear Technology Corporation. Other product names may be trademarks of the companies thatmanufacture the products.

World’s Smallest 24-Bit ADCPacks High Accuracy,Ease of Use, into SO-8

by Michael K. Mayes

IntroductionLinear Technology enters the delta-sigma1, 2 analog-to-digital convertermarket with a tiny, high performance,24-bit ADC, the LTC2400. Thedevice’s superiority to existing delta-sigma ADC’s results from thecombination of an accurate analogmodulator with an innovative newdigital architecture. Typically, fine-line, digitally optimized processes arerequired for a delta-sigma ADC’son-chip digital filter. The resultingICs have high pin counts, large pack-ages and complex interfaces. TheLTC2400’s breakthrough in digitalfiltering allows the use of an analog-optimized process. The result is thesmallest (SO-8 package), lowest pincount (8) simplest to use delta-sigmaconverter on the market. A highlyaccurate on-chip oscillator, usingLinear’s high performance CMOS pro-cess, sets the digital filter’s notchfrequency, eliminating the need foran external crystal. Additionally, thepart offers exceptional INL, DNL, noiseand 50Hz/60Hz rejection. The inno-vation does not end here; this articlewill show how performance, ease ofuse and functionality make this partthe new state of the art in high reso-lution delta-sigma ADCs.

OverviewThe analog modulator is critical to theperformance of a delta-sigma ADC.For high DC accuracy, 1st or 2ndorder modulators provide insufficientdifferential nonlinearity (DNL). TheLTC2400 achieves optimum DC per-formance from a 3rd order delta-sigmamodulator (see Figure 1). Feedfor-ward compensation and analogprocessing within the modulator elimi-nate instability issues associated withhigh order modulators. The 1-bit ADCand DAC within the modulator guar-antee monotonicity and exceptionalINL performance of 4ppm.

The output of the delta-sigmamodulator is applied to a decimatingfilter. The sinc4 filter removes thequantization noise from the modula-tor output. Additionally, this filterrejects the fundamental frequency andits harmonics. This notch frequencyis set by an on-chip oscillator, typi-cally at line frequency for DCapplications. The combination of a4th order sinc filter with a precisionthin-film, factory-trimmed oscillatorguarantees at least 120dB rejectionof line frequency ±2%. Several con-verters on the market use sinc3 orsinc1 filters. Since line frequenciescan vary up to 2% over a 24-hourperiod, converters using these lowerorder filters cannot achieve 120dB

continued on page 3

Authors can be contacted at (408) 432-1900

IN THIS ISSUE…COVER ARTICLEWorld’s Smallest 24-Bit ADC PacksHigh Accuracy, Ease of Use, into SO-8..................................................... 1

Michael K. Mayes

Issue Highlights ............................ 2

LTC® in the News ........................... 2

DESIGN FEATURESWide Input Range,High Efficiency Step-DownSwitching Regulators .................... 5Jeff Schenkel

A 4.5ns, 4mA, Single-Supply,Dual Comparator Optimized for3V/5V Operation .......................... 10Joseph G. Petrofsky

250MHz RGB Video Multiplexer inSpace-Saving Package Drives Cables,Switches Pixels at 100MHz ......... 16John Wright and Frank Cox

LT®1468: An Operational Amplifierfor Fast, 16-Bit Systems .............. 18George Feliz

LTC1622: Low Input Voltage, CurrentMode PWM Buck Converter .......... 21San-Hwa Chee

LTC1531 Isolated Comparator .... 24Wayne Shumaker

DESIGN IDEASPolyPhase™ Switching RegulatorsOffer High Efficiency in Low Voltage,High Current Applications .......... 27Craig Varga

Level Shift Allows CFA VideoAmplifier to Swing to Groundon a Single Supply ...................... 30Frank Cox

DESIGN INFORMATIONComponent and MeasurementAdvances Ensure 16-Bit DAC SettlingTime (Part Two) ........................... 31Jim Williams

Net1 and Net2 Serial Interface ChipSet Supports Test Mode ............... 34 David Soo

New Device Cameos ..................... 37

Design Tools ................................ 39

Sales Offices ............................... 40

Linear Technology Magazine • November 19982

EDITOR’S PAGE

a

Be a Linear Insider! Visit our web site

(www.linear-tech.com/insider) or use the response card in this issue to

register. We will notify you via email about new information on the

web site that matches your interests

Issue HighlightsOur cover article for this issue in-

troduces Linear Technology’s entryinto the delta-sigma analog-to-digitalconverter market: the tiny, high per-formance, 24-bit LTC2400. TheLTC2400’s superiority to existingdelta-sigma ADC’s results from thecombination of an accurate analogmodulator with an innovative newdigital architecture. The LTC2400’sbreakthrough in digital filtering allowsthe use of an analog-optimized pro-cess. The result is the smallest (SO-8package), lowest pin count (8) sim-plest to use delta-sigma converter onthe market.

Our Design Features section debutsthree new power products. TheLT1676 and LT1776 are LinearTechnology’s latest offerings for highvoltage (to 60V) step-down switchingregulator applications. The LT1676/LT1776 operate in a fixed frequencymode (100kHz for the LT1676 vs200kHz for the LT1776) and can beexternally synchronized to a higherswitching frequency. The internal out-put switch is rated at a nominal peakcurrent of 700mA, which typicallyaccommodates DC output currentsof up to 500mA.

The LTC1622step-down DC/DCcontroller isdes i gned toharness all theenergy fromlithium-ionbatteries. Itswide input-voltagerange and100% duty cycleallow low dropout formaximum energy extraction fromthe battery. Its low quiescent currentextends battery life. High frequencyoperation allows the use of smallinductors, making it ideal for com-munications products.

In addition, this issue introducestwo new comparators. The LT1720 isan UltraFast™, low power, single-supply, dual comparator designed tooperate on a single 3V or 5V supply.

The comparators feature internal hys-teresis, making them easy to use,even with slowly moving input signals.The LT1720 is fabricated in LinearTechnology’s 6GHz complementarybipolar process, resulting in unprec-edented speed for its low powerconsumption.

The LTC1531 is an isolated, self-powered comparator that receivespower and communicates throughinternal isolation capacitors. The iso-lation capacitors provide 3000VRMS ofisolation between the comparator andits output. This allows the part to beused in applications that require highvoltage isolated sensing without theneed for an isolated power source.

In the amplifier arena, we premierthe LT1468, a single op amp optimizedfor accuracy and speed in 16-bit sys-tems. Operating from ±15V supplies,the LT1468 in a gain of –1 configura-tion will settle in 900ns to 150µV fora 10V step. It also features the excel-lent DC specifications required for16-bit designs. Two key applicationsare current-to-voltage (I/V) conver-sion following a fast, 16-bit currentoutput digital-to-analog converter

(DAC) and buffering the inputof an analog-to-digitalconverter (ADC).

One of the firstproducts from LTC’snew proprietary high

speed b ipo lar process is a250MHz RGB

(red, green, blue) multiplexer that is

optimized for switchingspeed. This new MUX, the

LT1675, is designed for pixel switch-ing in video graphics and for RGBrouting. It is configured with threeSPDT RGB video switches and threecurrent feedback amplifiers for directdriving of cables.

Our two Design Ideas for this issueare a PolyPhase supply based on twoLTC1430As operating 180° out ofphase, and a current feedback video

LTC in the News…Linear Technology Corporationannounced its first quarterfinancial results on October 13,1998, reporting net sales of$116,032,000––an increase of 6%compared to the same period lastyear. The Company’s net incomefor the quarter, $44,382,000 or$0.56 diluted earnings per share,was up 9% compared to the firstquarter of last year. LinearTechnology also reported that dur-ing the quarter it purchased back1,800,000 shares of its commonstock at a cost of approximately$100,000,000. In discussing theresults, President and CEO RobertH. Swanson noted that theCompany continued to have out-standing profitability and LinearTechnology’s return on sales forthe quarter “was both a record forthe Company and the strongest inthe industry.”

Linear Technology’s new delta-sigma analog-to-digital converter,the LTC2400 (see page 1), was thecover story of the September issueof Electronic Design. The articledetailed the LTC2400’s exceptionalspeed, precision and ease-of-use,and included a range of illustra-tions highlighting the LTC2400’s24-bit differential nonlinearity withno missing codes. The article alsounderscored this new part’sgroundbreaking design, allowingit to be housed in a tiny SO-8package yet deliver superior per-formance compared to competingparts more than twice its size.

amplifier with a level shifter forground-referenced signals.

Our Design Information sectionfeatures the conclusion of JimWilliams’s exposition on measuring16-bit DAC settling time, and alsointroduces the LTC1545, a Net1 andNet2 compliant serial interface chipthat supports the optional Test Mode,Remote Loopback and Local Loop-back functions.

We conclude with a septet of NewDevice Cameos.

Linear Technology Magazine • November 1998 3

DESIGN FEATURES

rejection, even with exact externaloscillators (refer to Figure 6a).

A simple, SPI-compatible 3-wireinterface outputs data with single-cycle settling. This simplifies the userinterface by eliminating latency andredundant data normally associatedwith delta-sigma ADCs. As a blackbox, the converter resembles tradi-tional, easy-to-use converters.

PerformanceDesigned on a 2µ , single-metal, ana-log CMOS process, the LTC2400 isimplemented with a die size under10kmil2. The key to Linear attainingthe nearly impossible is the highlyefficient sinc4 filter. Once the tinydigital circuitry was completed, theanalog circuitry was optimized forultrahigh performance.

The result is 24-bit DNL with nomissing codes guaranteed. As shownin Figure 2, the integral nonlinearityis a mere ±2ppm or 0.0002%. Thiscompares favorably with other 24-bitdevices’ INL performance of 15ppm–30ppm. Transparent to the user, theconverter continuously executes self-calibration algorithms automaticallyadjusting the offset and full-scale.With an initial accuracy of 1ppm, theoffset drifts less than 0.01ppm/°Cand the full scale drifts less than0.02ppm/°C (see Figures 3 and 4).Combining these DC parameters withRMS noise performance of 0.3ppm(see Figure 5), the LTC2400 resemblesa 6-digit digital voltmeter on a chip.

The modulator consists of opera-tional amplifiers and switchedcapacitor circuits. Previous delta-sigma converters place limitations onthese circuits. Since the LTC2400was designed on an analog process,these limitations are removed. This

allows a power supply range of 2.7Vto 5.5V and a reference range of frombelow 10mV to 90% of VCC. At VCC =3V, the power consumption is 750µW;it falls to 45µW in power-down mode.

In many applications, the inputsignal may exceed VREF or fall belowground. Conventional delta-sigmaconverters are unable to provide theuser with any indication of these over-range conditions. The LTC2400 hason-chip overrange circuitry. It con-tinues to output 24-bit valid dataover an effective input range of–12.5% × VREF to 112.5% × VREF.

One of the main advantages ofdelta-sigma converters over SAR orflash-type architectures is the inher-ent rejection of line frequency. In orderto achieve good rejection, past delta-sigma converters required an accurateexternal oscillator or crystal with aprecise, uncommon value. TheLTC2400 incorporates an on-chiposcillator eliminating the need for

∫ ∫ ∫

AUTOCALIBRATION AND

CONTROL

SERIAL INTERFACE

INTERNAL OSCILLATOR

DECIMATING FIR

FILTER

Σ

fO (INT/EXT)

DOUT

SCLK

CS

ADC

DAC

VREF

VIN

GND

VCC

0.00E+00 4.19E+06 8.39E+06 1.26E+07 1.68E+07OUTPUT CODE (DECIMAL)

INTE

GRAL

NON

LINE

ARIT

Y (p

pm)

5

4

3

2

1

0

–1

–2

–3

–4

–5

VCC = 5V VREF = 2.5V TA = 25°C fO = GND

–40 –15 10 35 60 85TEMPERATURE (°C)

OFFS

ET E

RROR

(ppm

)

5

4

3

2

1

0

–1

–2

–3

–4

–5

VCC = 5V VREF = 5V fO = GND

–40 –15 10 35 60 85TEMPERATURE (°C)

FULL

-SCA

LE E

RROR

(ppm

)

5

4

3

2

1

0

–1

–2

–3

–4

–5

VCC = 5V VREF = 5V fO = GND

Figure 1. LTC2400 block diagram

Figure 2. LTC2400 integral nonlinearity error Figure 3. Offset drift Figure 4. Full-scale drift

LTC2400, continued from page 1


DESIGN FEATURES

external components. The internaloscillator is so precise that the ADCrejects line frequency over a ±2%range, independent of supply or oper-ating temperature (see Figure 6a,where sinc1, sinc2 and sinc3 filters areshown for comparison). Line frequen-cies of 50Hz or 60Hz are selectable bysimply tying the fO pin to VCC orground. Other rejection frequenciescan be obtained by driving the fO pinwith an external clock.

The converter is so robust that thenoise performance and line rejectionare insensitive to layout. As shown inFigure 7, large noise errors applied toVCC, VREF or VIN (1.25VP-P, 60Hz, ±2%)have no effect on the ADC’s noise andlinearity performance.

Ease of UseAt a glance, the LTC2400 looks morelike an op amp than a delta-sigmaconverter. With only eight pins, it’s

–1.2 –1 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0 1.2OUTPUT CODE (ppm OF VREF)

NUM

BER

OF O

CCUR

RENC

ES A

T V I

N =

OV

1400

1200

1000

800

600

400

200

0

VDD = 5V VREF = 5V TA = 25°C fO = GND

RMS NOISE = 0.3ppm =1.5µV PEAK-TO-PEAK NOISE = 1.8ppm = 9µV OFFSET ERROR = 0.28ppm

about as easy to use as a common opamp (see Figure 8). Superior noiserejection and internal analog circuitryenable the use of one supply pin, oneground pin and a single-ended input.The internal oscillator eliminatesexternal crystals/capacitors andadded device pins. The remaining pinsform a standard 3-wire interface, con-sisting of a three-statable serial dataoutput (DOUT) under the control of achip select pin (CS) and a serial dataoutput clock (SCLK).

Applications currently using tradi-tional ADCs can easily migrate to theLTC2400. Single-cycle settling yieldsa one-to-one correspondence betweenthe start of a conversion and theoutput word. This allows the user toplace a multiplexer in front of theADC without worrying about latencyor data statistically dependent onprevious conversion results.

FunctionalityDespite its small size and low pincount, the LTC2400 provides manyflexible modes of operation. Forexample, tying CS low forces a con-tinuous conversion mode. With CStied high, the device enters a 45µWpower-down mode. For applicationsrequiring ultralow power, a capacitorcan be tied to CS. Under this

0 50 100 150 200 250 300

0

–20

–40

–60

–80

–100

–120

–140

FREQUENCY (Hz)

REJE

CTIO

N (d

B)

SINC

SINC2

SINC3

SINC4 (LTC2400)

–5.8% –3.3% 60 +3.3% +5.8%

0

–20

–40

–60

–80

–100

–120

–140

REJE

CTIO

N (d

B)

FREQUENCY (Hz)

1VRMS

60Hz

VIN

VCC

VREF

20

10

0

–10

–20

CODE

OUT

(ppm

)

ONE-SHOT OUTPUT CODE (NO AVERAGING)

INJECTED NOISE

TIME

Figure 5. Noise histogramFigure 6a. Filter response vs filter order

Figure 6b. Filter response at line frequency

Figure 7. Noise injection

continued on page 36


DESIGN FEATURES

Wide Input Range, High EfficiencyStep-Down Switching Regulators

by Jeff SchenkelIntroductionThe LT1676 and LT1776 are LinearTechnology’s latest offerings for highefficiency step-down switching regu-lator applications. These two partsare pin-for-pin compatible and virtu-ally identical in operation, the onlydifference being their internal oscil-lator frequencies—100kHz for theLT1676 vs 200kHz for the LT1776.They operate in a fixed frequencymode (as opposed to constant off-time or on-time, for instance) and canbe externally synchronized to a higherswitching frequency.

The internal output switch is ratedat a nominal peak current of 700mA,which typically accommodates DCoutput currents of up to 500mA. Theinput voltage range is 7.4V to 60V.Maintaining acceptable efficiency inthe upper half of this input voltagerange requires very fast output-switchedge rates. The LT1676/LT1776 con-tain specialized output circuitry todeliver this performance. Addition-ally, they contain circuitry to monitor

output load level and reduce leading-edge switch rate (turn-on) when theoutput load is light. This arrange-ment helps avoid pulse skipping atlight load, with its consequent sub-harmonic behavior.

True current mode operation issupported, with all its well knownadvantages for switching regulatoroperation. The shutdown pin imple-ments a pair of functions. Pulling itdown to near ground turns off thepart almost completely and reducesthe quiescent current to a few tens ofmicroamperes. The second shutdownpin function acts at a threshold ofroughly 1.25V. Below this level, thepart operates normally, except thatoutput switching action is inhibited.This allows the implementation of anundervoltage lockout function set by,for instance, an external resistordivider. The LT1676/LT1776 are avail-able in both 8-pin SO and PDIPpackages.

Theory of OperationThe LT1676/LT1776 are currentmode switching regulator ICs opti-mized for high efficiency operation inhigh input voltage, low output voltagebuck topologies. The block diagramin Figure 1 shows an overall view ofthe system. Several of the blocks arestraightforward and similar to thosefound in traditional designs, includ-ing the internal bias regulator,oscillator and feedback amplifier. Thenovel portion includes an elaborateoutput switch section and a logicsection to provide the control signalsrequired by the switch section.

The LT1676/LT1776 operate muchthe same as traditional current modeswitchers, the major difference beingtheir specialized output switchsection. Due to space constraints,this discussion will not reiterate thebasics of current mode switcher/con-trollers and the step-down topology.A good source of information on thesetopics is Linear Technology Applica-tion Note 19.

SWDR

SWDR

SWON

SWON

BOOST

1776 BD

BOOSTSWOFF

SWOFF

LOGICOSC

BIAS

VTH

VB

VBG

VBG

FB

VC

GND

SYNC

SHDN

VCC

FB AMP

BOOST COMP

gm I

I

I I

R1 RSENSE

I COMP

Q4

Q3

Q2

Q1

Q5

VSW

D1

VIN5

3

2

1

6

4

8

7

Figure 1. LT1776 block diagram


DESIGN FEATURES

One of the classic problems indelivering low output voltage from ahigh input voltage at good efficiencyis that minimizing AC switching lossesrequires very fast voltage (dV/dt) andcurrent (dI/dt) transitions at the out-put device. This is in spite of the factthat in a cost-effective bipolar IC pro-cess implementation, slow lateralPNPs must be included in the switch-ing signal path.

Fast, positive-going slew rate actionis provided by lateral PNP Q3 drivingthe Darlington arrangement of Q1and Q2. The extra β available from Q2greatly reduces the drive requirementsof Q3. Although desirable for dynamicreasons, this topology alone will yielda large DC forward voltage drop. Asecond lateral PNP, Q4, acts directlyon the base of Q1 to reduce the volt-age drop after the slewing phase hastaken place. To achieve the desiredhigh slew rate, PNPs Q3 and Q4 are“force-fed” packets of charge via thecurrent sources controlled by theBOOST signal.

Please refer to the timing diagramof Figure 2a. A typical oscillator cycleis as follows: The logic section firstgenerates a SWDR signal, which pow-

ers up the current comparator andallows it time to settle. About 1µslater, the SWON signal is assertedand the BOOST signal is pulsed for afew hundred nanoseconds. After ashort delay, the VSW pin slews rapidlyto VIN. Later, after the peak switchcurrent, indicated by the control volt-age VC, has been reached (currentmode control), the SWON and SWDRsignals are turned off and SWOFF ispulsed for a few hundred nanosec-onds. The use of an explicit turn-offdevice (Q5) improves turn-off responsetime and thus aids both controllabil-ity and efficiency.

The system described previouslyhandles heavy loads (continuousmode) at good efficiency, but is actu-ally counterproductive for light loads.The method of jamming charge intothe PNP bases makes it difficult toturn them off rapidly and achieve thevery short switch ON times requiredby light loads in discontinuous mode.Furthermore, the high leading edgedV/dt rate has a similar adverse effecton light load controllability.

The solution is to employ a “boostcomparator” whose inputs are the VCcontrol voltage and a fixed internal

threshold reference, VTH. (Rememberthat in a current mode switchingtopology, the VC voltage determinesthe peak switch current.) When theVC signal is above VTH, the previouslydescribed “high dV/dt” action is per-formed. When the VC signal is belowVTH, the BOOST pulses are absent, ascan be seen in Figure 2b. Now the DCcurrent activated by the SWON signalalone drives Q4 and this transistordrives Q1 by itself. The absence of aBOOST pulse plus the lack of a sec-ond NPN driver results in a muchlower slew rate, which aids light loadcontrollability.

A further aid to overall efficiency isprovided by the specialized bias regu-lator circuit, which has a pair ofinputs, VIN and VCC. The VCC pin isnormally connected to the switchingsupply output. During start-up con-ditions, the LT1676/LT1776 powerthemselves directly from VIN. How-ever, after the switching supply outputvoltage reaches about 2.9V, the biasregulator uses this supply as its input.Previous generation step-down con-troller ICs without this provisiontypically required hundreds of milli-watts of quiescent power when

SWOFF1776 TD01

BOOST

SWON

SWDR

0

VIN

VSW

SWOFF1776 TD02

BOOST

SWON

SWDR

0

VIN

VSW

VINVCCVSW

LT1676FBVC

SHDN

SYNC

C1: PANASONIC HFQ (201) 348-7522 C2: AVX D CASE TPSD107M010R0080 (803) 946-0362 C4, C5: X7R OR COG/NPO D1: MOTOROLA 100V, 1A, SMD SCHOTTKY (800) 441-2447 L1: COILCRAFT DO3316P-224 (847) 936-6400

2

C1 39µF 63V

5

4

1676 F04a

3

7

8

1

VIN 12V TO

48V

6

GND

+

C2 100µF 10V

+D1 MBRS1100

R1 36.5k 1%

VOUT 5V 0mA to 500mA

R2 12.1k 1%

R3 22k 5%

L1 220µH

C3 2200pF X7R

C4 100pF

C5 100pF

FOR 3.3V VOUT VERSION: R1: 24.3k, R2: 14.7k L1: 150µH, DO3316P-154 IOUT: 0mA TO 500mA

LOAD CURRENT (mA)1

60

EFFI

CIEN

CY (%

)

70

80

90

10 100 1000

1676 F04b

50

40

30

20

VIN = 12V

VIN = 24V

VIN = 36VVIN = 48V

Figure 2a. Timing diagram: high dV/dt mode Figure 2b. Timing diagram: low dV/dt mode

Figure 3a. Minimum component-count application Figure 3b. Efficiency of Figure 3a’s circuit


DESIGN FEATURES

operating at high input voltages. Thisboth degraded efficiency and limitedavailable output current due to inter-nal heating.

Choosing Between theLT1676 and LT1776 As previously mentioned, the LT1676and LT1776 devices are pin-for-pincompatible and, in fact, nearly iden-tical. The only real difference is intheir internal oscillator frequencies,nominally 100kHz for the LT1676and 200kHz for the LT1776. A usermust decide which version is bestsuited for his or her particular appli-cation. Generally, the LT1776 isfavored, as its higher switching fre-

quency allows for a lower valued andpossibly physically smaller and lesscostly inductor. However, the higherswitching frequency of the LT1776increases AC switching losses,adversely affecting efficiency andinternal power dissipation. In fact,certain combinations of high inputvoltage and output current may yieldunacceptable internal power dissipa-tion and consequent thermal rise. Inthese cases, the slower switching fre-quency of the LT1676 may yieldacceptable operation. (A more thor-ough treatment of input voltage vsoperating frequency considerationscan be found in the LT1776 datasheet.)

Applications

Minimum Component-Count ApplicationFigure 3a shows a basic “minimumcomponent count” application usingthe LT1676. The circuit produces 5.0Vat up to 500mA IOUT with input volt-ages in the range of 12V to 48V. Thetypical POUT/PIN efficiency is shown inFigure 3b. No pulse skipping isobserved down to zero external load.(The several milliamperes drawn bythe VCC pin acts as a sufficient pre-load.) As shown, the SHDN and SYNCpins are unused, however either (orboth) can be optionally driven byexternal signals as desired.

Minimum PC BoardArea ApplicationThe previous application exampleused the LT1676 to demonstratesimultaneously the maximum inputvoltage and output current capabil-ity. As such, the input bypasscapacitor choice was a high frequencyaluminum electrolytic type, rated to

VINVCCVSW

LT1776FBVC

SHDN

SYNC

C1: AVX D CASE 15µF 35V TPSD156M035R0300 (803) 946-0362 C2: AVX D CASE 100µF 10V TPSD107M010R0080 C3: 2200pF, X7R

2

C1 15µF 35V

5

4

1776 F07a

3

7

8

1

VIN 10V–30V

6

GND

+C2 100µF 10V

+D1 MBRS- 1100

R1 36.5k 1%

VOUT 5V 0mA to 400mA

R2 12.1k 1%

R3 22k 5%

L1 68µH

C3 2200pF

C4 100pF

C5 100pF

C4, C5: 100pF, X7R OR COG/NPO D1: MOTOROLA 100V, 1A, SMD SCHOTTKY MBRS1100 (800) 441-2447 L1: COILCRAFT DO1608C-683 (847) 936-6400

FOR 3.3V VOUT VERSION: IOUT: 0mA TO 500mA L1: 47µH, DO1608C-473 R1: 24.3k, R2: 14.7k

LOAD CURRENT (mA)1

60

EFFI

CIEN

CY (%

)

70

80

90

10 100 1000

1776 F07b

50

40

30

20

VIN = 10V

VIN = 20V

VIN = 30V

VIN

VIN 12V–48V

VCCVSW

U1 LT1676

FBVC

SYNC2

C1 39µF 63V

NC

Q1 PN2484

Q2 2N2369

5

4

1676 F06

3

7

8

6

1

GNDSHDN

V+

V–

IN–

IN+U2

LTC1440REF

HYST

OUT4

7

12

3

6

5

8

GND

+

C2 100µF 10V

+D1 MBRS1100

R1 39k 5%

VOUT 5V

R2 10k 5%

R6 22k

R7 2.4M

R3 323k 1%

R4 100k 1%

L1 220µH

C3 100pF

R7 10M

C1: PANASONIC HFQ (201) 348-2552 C2: AVX D CASE TPSD107M010R0080 (803) 946-0362) C4, C5: X7R OR COG/NPO D1: MOTOROLA 100V, 1A, SMD SCHOTTKY (800) 441-2447 L1: COILCRAFT DO3316-224 (847) 639-6400

LOAD CURRENT (mA)1

60

EFFI

CIEN

CY (%

)

70

80

90

10 100 1000

1676 F07b

50

40

30

20

VIN = 12V

VIN = 36VVIN = 48V

VIN = 24V

Figure 4a. Minimum PC board area application

Figure 4b. Efficiency of Figure 4a’s circuit

Figure 5a. Burst Mode operation configuration Figure 5b. Efficiency of Figure 5a’s circuit


DESIGN FEATURES

63V. Also, the 100kHz switching rateof the LT1676 requires an inductor ofabout 220µH. The DO3316 devicesize was chosen to support the outputcurrent requirements. However, bothof these components are physicallylarge.

The application example in Figure4a shows a circuit that is much smallerphysically than the previous mini-mum component count application.The nominal 200kHz switchingfrequency of the LT1776 allows theuse of a physically smaller 68µHinductor—a Coilcraft DO1608C-683.This inductor will support outputcurrent to 400mA at 5V. However, thepart is incapable of withstanding anindefinite short circuit to ground.(Momentary shorts of a few secondsor less can still be tolerated.)Additionally, the bulky aluminum

electrolytic capacitor previously onVIN has been replaced by a compact35V-rated tantalum type. The resultis a postage-stamp-sized circuit withefficiency as shown in Figure 4b.

Burst Mode ApplicationThe minimum component countapplication demonstrates that powersupply efficiency degrades with loweroutput load current. This is notsurprising, as the LT1676 itself rep-resents a fixed power overhead. Apossible way to improve light loadefficiency is to use Burst Mode™operation.

Figure 5a shows the LT1676 con-figured for Burst Mode operation.Output voltage regulation is now pro-vided in a “bang-bang” digital manner,via comparator U2, an LTC1440.Resistor divider R4/R5 provides ascaled version of the output voltage,which is compared against U2’sinternal reference. Intentional hys-teresis is set by the R6/R7 divider. Asthe output voltage falls below theregulation range, the LT1676 is turnedon. The output voltage rises and, as itclimbs above the regulation range,the LT1676 is turned off. Efficiency ismaximized as the LT1676 is only pow-ered up while it is providing heavyoutput current. Figure 5b shows thatefficiency is typically maintained at75% or better down to a load currentof 10mA. Even at a load current of

VIN

VCC

VSW

U1 LT1776

U3 LT1121-5

FB

VC

SHDN

SYNC

C1: PANASONIC HFQ (201) 348-7522 C2: AVX TPSD107M010R0080 (803) 946-0362 L1: COILCRAFT DO3316P-104 (847) 639-6400

7

C1 39µF 63V

5

4

1776 TA02

2

3

8

1

VIN 11V TO 30V (SEE TEXT)

6

GND

VCC

IN+PROG

U2 LT1620

IOUT

IN–NC

AVG

SENSE

2

5

4

6

3

8

1

7

GND

+

D1 MBRS1100

R1 57.6k 1%

3-CELL LEAD-ACID BATTERY

R2 12.1k 1%

R3 22k

R5 3k

R6 12k

L1 100µH

R4 0.5Ω

C4 2200pF

C3 100pF

C7 0.1µF

C5 100pF

C6 0.33µF

C2 100µF 10V

C8 1µF

+

+

7.2V

2mA, efficiency is still a respectable65% to 75% (depending on VIN).

Resistor divider R1/R2 is stillpresent, but does not directly influ-ence output voltage. It is chosen toensure that the LT1676 delivers highoutput current throughout the volt-age regulation range. Its presence isalso required to maintain propershort-circuit protection. TransistorsQ1 and Q2 and resistor R7 form ahigh VIN, low quiescent current volt-age regulator to power U2.

Battery Charger ApplicationFigure 6a shows the LT1776 con-figured as a constant-current/constant-voltage battery charger. AnLT1620 rail-to-rail current senseamplifier (U2) monitors the differen-tial voltage across current senseresistor R4. As this equals and exceedsthe voltage across resistor R5 in theR5/R6 divider, the LT1620 respondsby sinking current at its IOUT pin. Thisis connected to the VC control node ofthe LT1776 and therefore acts toreduce the amount of power deliveredto the load. The overall constant-current/constant-voltage behaviorcan be seen in Figure 6b.

Target voltage and current limitsare independently programmable. Theoutput voltage of 7.2V, which corre-sponds to the charging voltage of a3-cell lead-acid battery, is set by theR1/R2 divider and the internal refer-

OUTPUT CURRENT (mA)0

OUTP

UT V

OLTA

GE (V

)

8

7

6

5

4

3

2

1

050 100 150 250200

1776 TA05

Figure 6a. Wide VIN range, high efficiency battery charger

Figure 6b. Battery charger output voltage vsoutput current for Figure 6a’s circuit


DESIGN FEATURES

ence of the LT1776. Output current,presently 200mA, is set by currentsense resistor R4 and the R5/R6 di-vider. (A 16-pin version of the LT1620that implements end-of-cycle detec-tion is also available. This is useful forimplementing lead-acid battery “top-off” charger behavior or the like. Seethe LT1620 data sheet for furtherinformation.)

The circuit as shown accommo-dates an input voltage range of 11V to30V. The upper input voltage limit of30V is determined not by the LT1776,but by the LT1121-5 regulator (U3).(A regulated 5V is required by theLT1620.) This regulator was chosenfor its micropower behavior, whichhelps maintain good overall efficiency.However, the basic catalog part isonly rated to 30V. Substitution of theindustry standard LM317, forexample, extends the allowable inputvoltage to 40V (or more with the HVversion), but its greater quiescentcurrent drain degrades efficiency fromthat shown.

Dual Output SEPIC ConverterAll of the previous applications pro-vide a single positive output voltage.Real world situations often requiredual supply voltages. The SEPICtopology (single-ended primary induc-tance converter) offers a cost-effectiveway to simultaneously generate anegative voltage with a single piece of

magnetics. The circuit in Figure 7uses an LT1776 to generate both posi-tive and negative 5V. The twoinductors shown are actually just twowindings on a standard Coiltronicsinductor. Capacitor C3 creates theSEPIC topology, which improves regu-lation and reduces ripple current inL1.

For the best negative supply volt-age regulation, this output shouldhave a preload of at least 1% of themaximum positive load. Total avail-able current from both outputs islimited to 500mA. Maximum negativesupply current is limited by the posi-tive 5V load. A typical limit is one-halfof the positive current, but a more

exact calculation includes the inputvoltage. For this and further details ofthis topology, see Linear TechnologyDesign Note 100.

Positive-to-Negative ConverterThe previous example used a dualinductor to create a pair of outputvoltages, one positive and the othernegative. The positive-to-negative con-verter topology illustrated in Figure 8generates a single negative outputvoltage from a positive input voltage,using just an ordinary inductor. Thetopology is somewhat similar to theoriginal step-down arrangement, butthe inductor is grounded and theLT1776 ground is now referred to thenegative output voltage. Note that theintegrated circuit must now be ratedfor the worst case sum of the inputvoltage plus the absolute value of theoutput voltage. The relatively highinput voltage rating of the LT1676/LT1776 parts along with their goodefficiency under such conditions makethem an excellent choice for imple-menting this topology. The circuit asshown converts an input voltage inthe range of 10V to 28V to a –5Voutput. Available output current is300mA at the worst case VIN of 10V.

The user should exercise cautionin modifying this circuit for otherapplications. The positive-to-negativetopology is not as straightforward asthe step-down topology. It is actuallymore like a flyback topology, in thatcurrent is delivered to the output in

+

+

+

+ C1 15µF 35V

C7 100pF

VCC

VSW

FB

VC

2

3

7

8

1

6

SHDN

SYNC

5

4

VIN

GND

C5 2200pF X7R

R3 22k 5%

C6 100pF

C3 100µF 10V

C4 100µF 10V

C2 100µF 10V

L1* 100µH

R1 36.5k 1%

R2 12.1k 1%

L1* 100µH

D2 MBR1100

D1 MBR- 1100

VOUT –5V†

VOUT 5V†

VIN 10V–28V

†TOTAL AVAILABLE CURRENT IS LIMITED TO 500mA (SEE TEXT)

LT1776

AVX D CASE TPSD156M035R0300 (803) 946-0362 AVX D CASE TPSD107M010R0080 X7R OR COG/NPO MOTOROLA MBRS1100 100V, 1A, SMD SCHOTTKY (800) 441-2447 COILTRONICS CTX100-3 SINGLE CORE WITH 2 WINDINGS (561) 241-7876

C1:

C2, C3, C4: C6, C7: D1, D2:

*L1:

+

+ C1 15µF 35V

C5 100pF

VCC

VSW

FB

VC

2

3

7

8

1

6

SHDN

SYNC

5

4

VIN

GNDC3 2200pF X7RR3

22k 5%

C4 100pF

C2 100µF 10V

L1 100µHR1 36.5k 1%

R2 12.1k 1%D1

MBRS1100

VOUT –5V 0mA–300mA

VIN 10V–28V

AVX D CASE TPSD156M035R0300 (803) 946-0362 AVX D CASE TPSD107M010R0080 X7R OR COG/NPO MOTOROLA MBRS1100 100V, 1A, SMD SCHOTTKY (800) 441-2447 COILCRAFT D03316-104 (847) 639-6400

C1:

C2: C4, C5:

D1:

L1:

LT1776

Figure 7. Dual-output SEPIC converter

Figure 8. Positive-to-negative converter



DESIGN FEATURES

A 4.5ns, 4mA, Single-Supply,Dual Comparator Optimized for3V/5V OperationIntroductionThe LT1720 is an UltraFast™ (4.5ns),low power (4mA/comparator), single-supply, dual comparator designed tooperate on a single 3V or 5V supply.These comparators feature internalhysteresis, making them easy to use,even with slowly moving input sig-nals. The LT1720 is fabricated inLinear Technology’s 6GHz com-plementary bipolar process, resultingin unprecedented speed for its lowpower consumption. Table 1 summa-rizes the LT1720’s performancespecifications.

The LT1720 is offered in SO-8,with just three pins per comparatorplus power and ground. For afull-featured, 7ns, single-supply com-parator with dual complementaryoutputs and internal latch, theLT1394 is available from this samehigh speed process.

These fast, small, low power com-parators are versatile building blocksfor a variety of high speed, single-supply applications, such as clockgenerators, window comparators, tim-ing skew generators, coincidencedetectors and pulse stretchers.

Circuit DescriptionThe block diagram of one comparatorin the LT1720 is shown in Figure 1.There are differential inputs (+IN/–IN), an output (OUT), a single posi-tive supply (VCC) and ground (GND).The two comparators are completelyindependent, sharing only the powerand ground pins. The circuit topologyconsists of a differential input stage,a gain stage with hysteresis and acomplementary common-emitter out-

put stage. All of the internal signalpaths utilize low voltage swings forhigh speed at low power.

The input stage topology maximizesthe input dynamic range availablewithout requiring the power, com-plexity and die area of two completeinput stages such as are found in rail-to-rail input comparators. With a 2.7Vsupply, the LT1720 still has arespectable 1.6V of input commonmode range. The differential inputvoltage range is rail-to-rail, withoutthe large input currents found in com-peting devices. The input stage alsofeatures phase reversal protection toprevent false outputs when the inputsare driven below the –100mV com-mon mode voltage limit.

The internal hysteresis is imp-lemented by positive, nonlinearfeedback around a second gain stage.Until this point, the signal path hasbeen entirely differential. The signalpath is then split into two drive sig-nals for the upper and lower outputtransistors. The output transistorsare connected common emitter forrail-to-rail output operation. The

by Joseph G. Petrofsky

–

+

–

+

–

+

–

+

+IN

–IN

AV1 AV2

NONLINEAR STAGE

OUT

GND

VCC

Σ

Σ

++

++

retemaraP snoitidnoC eulaV

yaleDnoitagaporP Vm02=evirdrevO sn5.4

yaleDnoitagaporP Vm5=evirdrevO sn7

tnerruCylppuS V CC V5= rotarapmoCrepAm4

egatloVylppuS stimiLegnaRerutarepmeTlluF V6otV7.2

egnaRegatloVtupnI stimiLegnaRerutarepmeTlluF V(otV1.0– CC )V2.1–

egatloVtesffOtupnI V CC V,V5= MC V1= Vm1

siseretsyHderrefeR-tupnI V CC V,V5= MC V1= Vm5.3

)woL(egatloVtuptuO I KNIS Am01= xaMV4.0

)hgiH(egatloVtuptuO I ECRUOS Am4= V( CC niM)V4.0–

Table 1. Typical LT1720 specifications, TA = 25°C

Figure 1. LT1720 block diagram


DESIGN FEATURES

Schottky clamps limit the output volt-ages at about 300mV from the rail,not quite the 50mV or 15mV of LinearTechnology’s rail-to-rail amplifiersand other products. But the output ofa comparator is digital, and this out-put stage can drive TTL or CMOSdirectly. It can also drive a host ofother loads, as will be demonstratedin the applications below.

The bias conditions and signalswings in the output stages aredesigned to turn their respective out-put transistors off faster than on.This nearly eliminates the surge ofcurrent from VCC to ground that occursat transitions, keeping the powerconsumption low even with high out-put-toggle frequencies. In fact, theinternal-frequency-dependent cur-rent drain is the equivalent of puttingjust 15pF on the output. The lowsurge current also helps keep theLT1720 well behaved in high speedapplications.

Internal HysteresisThe LT1720 includes internal hyster-esis, eliminating the linear regionwhere high speed comparators aremost temperamental. The input-output transfer characteristic isillustrated in Figure 2, which showsthe definitions of VOS and VHYST basedupon the two measurable trip points.The 3.5mV (typical) hysteresis bandmakes the LT1720 well behaved, evenwith slowly moving inputs.

The exact amount of hysteresis willvary from unit-to-unit; the LT1720specifications include both upper andlower limits that are guaranteed over

temperature. The hysteresis will alsovary slightly with changes in supplyvoltage and common mode voltage. Ifa comparator is used to detect athreshold crossing in one directiononly, only that trip point is signifi-cant. Therefore, a stable offset voltagewith an unpredictable level of hyster-esis, as seen in many competingcomparators, is useless. The LT1720is many times better than prior com-parators in this regard. Figure 3 showsa typical LT1720’s input voltages vssupply voltages. The VOS shift is only320µV, corresponding to a typicalPSRR of 80dB.

Speed LimitsThe LT1720 comparators are intendedfor high speed applications, where itis important to understand a few limi-tations. These limitations can roughlybe divided into three categories: inputspeed limits, output speed limits andinternal speed limits.

There are no significant input speedlimits except the shunt capacitanceof the input nodes. If the 2pF typicalinput nodes are driven, the LT1720will respond.

The output speed is constrained bythe slew currents available from theoutput transistors. To maintain lowpower quiescent operation, theLT1720 output transistors are sizedto deliver 25mA–45mA typical slewcurrents. This is sufficient to drivesmall capacitive loads and logic gateinputs at extremely high speeds. Butthe slew rate will slow dramatically

with heavy capacitive loads. Becausethe propagation delay (tPD) definitionends at the time the output voltage ishalfway between the supplies, thefixed slew current actually makes theLT1720 faster at 3V than 5V with20mV of input overdrive.

The internal speed limits manifestthemselves as dispersion. All com-parators have some degree ofdispersion, defined as a change inpropagation delay vs input overdrive.The propagation delay of the LT1720will vary with overdrive, from a typicalof 4.5ns at 20mV overdrive to 7ns at5mV overdrive (typical). The LT1720’sprimary source of dispersion is thehysteresis stage. As a change ofpolarity arrives at the gain stage, thepositive feedback of the hysteresisstage subtracts from the overdriveavailable. Only when enough timehas elapsed for a signal to propagateforward through the gain stage, back-wards through the hysteresis stageand forward through the gain stageagain, will the output stage receivethe same level of overdrive that itwould have received in the absence ofhysteresis.

With 5mV of overdrive, the LT1720is faster with a 5V supply than with a3V supply, the opposite of what istrue with 20mV overdrive. This is dueto the internal speed limit, becausethe gain stage is faster at 5V than 3Vdue primarily to the reduced junctioncapacitances with higher reverse volt-age bias.

In many applications, as shown inthe following examples, there is plentyof input overdrive. Even in applica-

VHYST (= VTRIP

+ – VTRIP–)

VHYST/2

VOL

VOH

VTRIP– VTRIP

+

∆VIN = VIN+ – VIN

–

VTRIP+ + VTRIP

–

2VOS =

V OUT

0

SUPPLY VOLTAGE (V)2.5

V OS

AND

TRIP

VOL

TAGE

(mV)

3

2

1

0

–1

–2

–34.0 5.0

1720 G01

3.0 3.5 4.5 5.5 6.0

VTRIP+

VOS

VTRIP–

TJ = 25°C VCM = 1V

–

+1/2 LT1720

VCC 2.7V–6V

2k

620Ω220Ω

1MHz–10MHz CRYSTAL (AT-CUT)

1.8k

2k

0.1µF

GROUND CASE

OUTPUT

Figure 2. Hysteresis I/O characteristicsFigure 3. The LT1720’s hysteresis isinsensitive to supply-voltage variations.

Figure 4. Simple 1MHz–10MHzcrystal oscillator


DESIGN FEATURES

tions providing low levels of over-drive, the LT1720 is fast enough thatthe absolute dispersion of 2.5ns (= 7– 4.5) is small enough to ignore.

The gain and hysteresis stage ofthe LT1720 is simple, short and highspeed to minimize dispersion. Thisinternal “self-latch” can be usefullyexploited in many applicationsbecause it occurs early in the signalchain, in a low power, fully differen-tial stage. It is therefore highly immuneto disturbances from other parts ofthe circuit, either in the same com-parator, on the supply lines or fromthe other comparator in the samepackage. Once a high speed signaltrips the hysteresis, the output willrespond, after a fixed propagationdelay, without regard to these exter-nal influences that can cause troublein nonhysteretic comparators.

Applications

Crystal OscillatorsFigure 4 shows a simple crystal oscil-lator using one half of an LT1720. The2k–620Ω resistor pair set a bias pointat the comparator’s noninvertinginput. The 2k–1.8k–0.1µF path setsthe inverting input node at an appro-priate DC average level based on theoutput. The crystal’s path provides

resonant positive feedback and stableoscillation occurs. Although theLT1720 will give the correct logic out-put when one input is outside thecommon mode range, additionaldelays may occur when it is so oper-ated, opening the possibility ofspurious operating modes. Therefore,the DC bias voltages at the inputs areset near the center of the LT1720’s

common mode range and the 220Ωresistor attenuates the feedback tothe noninverting input. The circuitwill operate with any AT-cut crystalfrom 1MHz to 10MHz over a 2.7V to6V supply range.

The output duty cycle for the cir-cuit of Figure 4 is roughly 50% but itis affected by resistor tolerances and,to a lesser extent, by comparator off-sets and timings.

The circuit of Figure 5 creates apair of complementary outputs with aforced 50% duty cycle. Crystals arenarrow-band elements, so the feed-back to the noninverting input is afiltered analog version of the squarewave output. Changing the nonin-verting reference level can thereforevary the duty cycle. C1 operates as inthe previous example, whereas C2creates a complementary output bycomparing the same two nodes withthe opposite input polarity. A1 com-pares band-limited versions of theoutputs and biases C1’s negative in-put. C1’s only degree of freedom torespond is variation of pulse width;hence the outputs are forced to 50%duty cycle. This circuit works wellbecause of the two matched delaysand rail-to-rail style outputs.

–

+

–

+

–

+

C1 1/2 LT1720

C2 1/2 LT1720

A1 LT1636

VCC 2.7V–6V

2k

620Ω220Ω


100k

100k

2.2k

1.3k

2k

1k

0.1µF

0.1µF

0.1µF

OUTPUT 0

OUTPUT 1

GROUND CASE

OPTIONAL— SEE TEXT

–

+

–

+

–

+

C1 1/2 LT1720

C2 1/2 LT1720

A1 LT1636

VCC 2.7V–6V

2k

620Ω220Ω


100k

100k

1.8k

2k

1k

0.1µF

0.1µF

0.1µF

OUTPUT

OUTPUT

GROUND CASE

Figure 5. Crystal oscillator with complementary outputs and 50% duty cycle

Figure 6. Crystal-based nonoverlapping 10MHz clock generator


DESIGN FEATURES

The circuit in Figure 6 shows acrystal oscillator circuit that gener-ates two nonoverlapping clocks bymaking full use of the two indepen-dent comparators of the LT1720. C1oscillates as before, but with a lowerreference level, C2’s output will toggleat different times. The resistors setthe degree of separation between theoutput’s high pulses. With the valuesshown, each output has a 44% highand 56% low duty cycle, sufficient toallow 2ns between the high pulseswhere both are at logic low. Figure 7shows the two outputs.

The optional A1 feedback networkshown can be used to force identicaloutput duty. Because the referencelevel set for C2 is lower than that setfor C1, the steady state duty cycleswill be 44% rather than 50%. Note,though, that the addition of this net-work only adjusts the percentage oftime each output is high to be thesame, which can be important in

switching circuits requiring identicalsettling times. It cannot adjust therelative phases between the two out-puts to be exactly 180° apart becausethe signal at the input node driven bythe crystal is not an exact sinusoid.

Timing SkewsFor a number of reasons, the LT1720is an excellent choice for applicationsrequiring differential timing skew. Thetwo comparators in a single packageare inherently well matched, with just300ps ∆tPD typical. Monolithic con-struction keeps the delays wellmatched vs supply voltage and tem-perature. Crosstalk between thecomparators, usually a disadvantagein monolithic duals, has minimaleffect on the LT1720 timing due to theinternal hysteresis, as discussedearlier.

The circuits of Figure 8 show basicbuilding blocks for differential timingskews. The 2.5k resistance interactswith the 2pF typical input capaci-tance to create at least ±4ns delay,controlled by the potentiometer set-ting. A differential and a single-endedversion are shown. In the differentialconfiguration, the output edges canbe smoothly scrolled through ∆t = 0with negligible interaction.

Fast Waveform SamplerFigure 9 uses a diode-bridge-typeswitch for clean, fast waveform sam-pling. The diode bridge, because of itsinherent symmetry, provides lower

–

+

–

+

LT1720

DIFFERENTIAL ±4ns RELATIVE SKEW

CIN

CIN

CIN

CIN

VREF

2.5k

2.5k

INPUT

–

+

–

+

LT1720

0ns–4ns SINGLE-ENDED DELAY

CIN

CIN

CIN

CIN

VREF

INPUT

AC errors than other semiconductor-based switching technologies. Thiscircuit features 20dB of gain, 10MHzfull power bandwidth and 100µV/°Cbaseline uncertainty. Switching delayis less than 15ns and the minimumsampling window width for full powerresponse is 30ns.

The input waveform is presentedto the diode bridge switch, the outputof which feeds the LT1227 widebandamplifier. The LT1720 comparators,triggered by the sample command,generate phase-opposed outputs.These signals are level shifted by thetransistors, providing complementarybipolar drive to switch the bridge. Askew compensation trim ensuresbridge-drive signal simultaneitywithin 1ns. The AC balance correctsfor parasitic capacitive bridge imbal-ances. A DC balance adjustment trimsbridge offset.

The trim sequence involves ground-ing the input via 50Ω and applying a100kHz sample command. The DCbalance is adjusted for minimal bridgeON vs OFF variation at the output.The skew compensation and AC bal-ance adjustments are then optimizedfor minimum AC disturbance in theoutput. Finally, unground the inputand the circuit is ready for use.

Coincidence DetectorHigh speed comparators are especiallysuited for interfacing pulse-outputtransducers, such as particle detec-tors, to logic circuitry. The matched

Q02V/DIV

Q12V/DIV

10ns/DIV

Figure 7, Nonoverlapping outputsof Figure 6’s circuit

Figure 8. Timing-skew generation is easy with the LT1720.


DESIGN FEATURES

delays of a monolithic dual are wellsuited for those cases where the coin-cidence of two pulses needs to bedetected. The circuit of Figure 10 is acoincidence detector that uses anLT1720 and discrete components asa fast AND gate.

The reference level is set to 1V, anarbitrary threshold. Only when bothinput signals exceed this will a coin-cidence be detected. The Schottkydiodes from the comparator outputsto the base of the MRF-501 form theAND gate, while the other two

Schottkys provide for fast turn-off. Alogic AND gate could instead be used,but would add considerably moredelay than the 300psec contributedby this discrete stage.

This circuit can detect coincidentpulses as narrow as 2.5ns. For nar-rower pulses, the output will degradegracefully, responding, but with nar-row pulses that don’t rise all the wayto high before starting to fall. Thedecision delay is 4.5ns with inputsignals 50mV or more above the ref-erence level. This circuit creates a

–

+

5V

2.2k2.2k

INPUT ±100mV FULL SCALE

1k LT1227

909Ω

100Ω

OUTPUT ±1V FULL SCALE

5V

AC BALANCE

3pF

3.6k1.5k

0.1µF

CIN

CIN

2k

2k

10pF

SKEW COMP

2.5k

1.1k

1.1k

1.1k

1.1k

820Ω820Ω

MRF501 MRF501

LM3045

11

9 6

8

DC BALANCE

500Ω

51Ω 51Ω

10 7

680Ω

–5V

13

= 1N5711

= CA3039 DIODE ARRAY (SUBSTRATE TO –5V)

–

+1/2 LT1720

–

+1/2 LT1720

SAMPLE COMMAND

TTL compatible output but it cantypically drive CMOS as well.

Pulse StretcherFor detecting short pulses from asingle sensor, a pulse stretcher isoften required. The circuit of Figure11 acts as a one-shot, stretching thewidth of an incoming pulse to a con-sistent 100ns. Unlike a logic one-shot,this LT1720-based circuit requiresonly 100pV-s of stimulus to trigger.

The circuit works as follows: Com-parator C1 functions as a threshold

Figure 9. Fast waveform sampler using the LT1720 for timing-skew compensation


DESIGN FEATURES

5V3.9k

1k

0.1µF

51Ω

51Ω

300Ω

300Ω

5V 5V

4× 1N5711

MRF501 (GROUND CASE LEAD)

OUTPUT

COINCIDENCE COMPARATORS 300ps AND GATE

1/2 LT1720

–

+

–

+1/2 LT1720

–

+

–

+PULSE SOURCE C1

1/2 LT1720

C2 1/2 LT1720

50Ω51Ω

6.8k

1N5711

24Ω

15k

R 1k

2k 2k

2k

C 100pF

0.01µFOUTPUT

100ns

5V

detector, whereas comparator C2 isconfigured as a one-shot. The firstcomparator is prebiased with a thresh-old of 8mV to overcome comparatorand system offsets and establish alow output in the absence of an inputsignal. An input pulse sends the out-put of C1 high, which in turn latchesC2’s output high. The output of C2 isfed back to the input of the firstcomparator, causing regeneration andlatching both outputs high. Timingcapacitor C now begins chargingthrough R and, at the end of 100ns,C2 resets low. The output of C1 alsogoes low, latching both outputs low. Anew pulse at the input of C1 can nowrestart the process. Timing capacitorC can be increased without limit forlonger output pulses.

This circuit has an ultimatesensitivity of better than 14mV with5ns–10ns input pulses. It can evendetect an avalanche generated testpulse of just 1ns duration withsensitivity better than 100mV.1 Itcan detect short events better thanthe coincidence detector abovebecause the one-shot is configured tocatch just 100mV of upwardmovement from C1’s VOL, whereasthe coincidence detector’s 2.5nsspecification is based on a full, legiti-mate logic high.

ConclusionThe new LT1720 dual 4.5ns single-supply comparators feature highspeeds and low power consumption.They are versatile and easy-to-usebuilding blocks for a wide variety ofsystem design challenges.

1 See Linear Technology Application Note 47,Appendix B. This circuit can detect the output ofthe pulse generator described after 40dB ofattenuation.

Figure 10. A 2.5ns coincidence detector

Figure 11. A 1ns pulse stretcher

for the latest information

on LTC products, visit

www.linear-tech.comAuthors can be contacted

at (408) 432-1900


DESIGN FEATURES

250MHz RGB Video Multiplexer inSpace-Saving Package DrivesCables, Switches Pixels at 100MHz

by John Wright andFrank CoxIntroduction

One of the first products from LTC’snew proprietary high speed bipolarprocess is a 250MHz RGB (red, green,blue) multiplexer that is optimized forswitching speed and makes excellentuse of the new complementary 6GHztransistors. This new MUX, theLT1675, is designed for pixel switch-ing in video graphics and for RGBrouting. It is configured with threeSPDT (single pole, double throw) RGBvideo switches and three current feed-back amplifiers for direct driving ofcables.

The new RGB MUX is similar to theLT1203/LT1205 video switches com-bined with the LT1260 triple CFA, butwith greatly enhanced performancein far less space. The boost over theolder configuration is a factor of fivein switching speed and a factor of 2.5in bandwidth, while the PCB foot-print is reduced by more than five.This “juiced” performance is accom-plished with one-third less supplycurrent than required by the equiva-lent multichip design.

Dense Process YieldsBig Performance fromTiny PC Board SpaceOne advantage of the dense, highspeed bipolar process is that it resultsin a reduced die size for the LT1675,even though it has well over 300active devices. The benefit to the useris that the LT1675 comes in a small16-pin SSOP package, which is thesame size as an SO-8. To enhance thesmall PC board theme, the LT1675 isconfigured for a fixed gain of two,eliminating six external gain settingresistors. The fixed gain of two in theCFA is ideal for driving double termi-nated 50Ω or 75Ω cables. Additionally,stray PCB capacitance on the sensi-tive feedback node is no longer aproblem. Figure 1 shows a typicalapplication switching between twoRGB sources and driving 75Ω cables.In contrast, some competitive solu-tions are housed in bulky 24-pin,wide-SO packages and draw signifi-cantly more supply current.

RED 1

GREEN 1

BLUE 1

RED 2

GREEN 2

BLUE 2

75Ω

75Ω

75Ω

75Ω

CABLE

CABLE

CABLE

V+

V–

SELECT RGB1/RGB2

1675 TA01

ENABLE

75Ω

75Ω

75Ω

75Ω

75Ω

75Ω

VOUT RED

75Ω

75Ω

VOUT GREEN

VOUT BLUE

+1

+1+2

+2

+2

+1

+1

+1

+1

CABLE

R2 75Ω

R2 75Ω

1675 F05

750Ω75Ω

750Ω

OFF

750Ω75Ω

750Ω

OFF

750Ω

R1 75Ω

R1 75Ω

750Ω

ON

n . . .

⇒1575 n – 1

n = NUMBER OF LT1675s IN PARALLEL

Figure 1. LT1675 typical application: switching betweentwo RGB sources and driving three cables

Figure 2. Select pin switches inputsat 100MHz. RED 1 = 0V, RED 2 =1V, RL = 100Ω, 10pF scope probe;measured between 50Ω backtermination and 50Ω load

Figure 3. Input-referred switchingtransient. RL = 150Ω, 10pF scopeprobe

Figure 4. Each off channel loads the cable terminationwith the 1575Ω.

3V

0V

1V

0V

SELECTLOGICPIN 10

RED OUTPIN 15

2ns/DIV

3V

0V

0V

SELECTLOGICPIN 10

RED OUTPIN 15

5ns/DIV

50mV


DESIGN FEATURES

The LT1675’s internal switcheschange state in less than 1ns but theoutput of the MUX switches in 2.5ns.This increased time is due to the finitebandwidth of the current feedbackamplifier that drives the cable. Totoggle at 100MHz, as shown in Figure2, implies a pixel width of 5ns; accom-plishing this requires a slew rate inexcess of 1000V/µs. In Figure 2, theSelect pin (pin 10) is driven from asine wave generator, since only cross-ings of the logic threshold are required.

The fast current steering break-before-make SPDT tee switchesminimize switching glitches. Theswitching transients of Figure 3,measured between the 75Ω back ter-mination and the 75Ω load, showwhat the monitor receives. The glitchis only 50mVp-p, the duration is only5ns and nature of this transient issmall and fast enough to not be visibleeven on quality graphics terminals.Additionally, the break-before-makeSPDT switch is open before the alter-nate channel is connected, whichmeans there is no input feedthroughor crosstalk during switching.

R1

R2

R3

R4

CHIP SELECT

1675 F06

ENABLELT1675 #1

75Ω

AV = 2

LT1675 #2

74HC04

ENABLE

75Ω

RED OUT

AV = 2

75Ω

Expanding Inputs Does NotIncrease Power DissipationIn video routing applications, wherethe ultimate in speed is not manda-tory, as it is in pixel switching, it ispossible to expand the number ofMUX inputs by shorting the LT1675outputs together and switching withthe ENABLE pins. This technique doesnot increase the power dissipationbecause LT1675s draw virtually zerocurrent when disabled. The internalgain-set resistors have a nominalvalue of 750Ω and cause a 1500Ωshunt across the 75Ω cable termina-tion. Figure 4 shows schematicallythe effect of expanding the number ofinputs. The effect of this loading is tocause a gain error that can be calcu-lated by the following formula:

75Ω + 75Ω1575Ω n – 1 ||

75Ω1575Ω n – 1 ||( (6dB + 20log dB

GAIN ERROR (dB) =

where n is the total number ofLT1675s.

For example, using ten LT1675s(20 red, 20 green, 20 blue) the gainerror is only –1.7dB per channel.

Figure 5 shows a 4-input RGBrouter. The response from red 1 inputto red output is shown in Figure 6, for

1V

0V

1V

0V

RED 1INPUT

REDOUTPUT

5V

0V

0V

CHIPSELECT

REDOUTPUT

retemaraP snoitidnoC seulaVlacipyT

htdiwdnaBBd3– RL = 51 0Ω zHM052

ssentalFniaGBd1.0 RL 51= 0Ω zHM07

klatssorC zHM01taslennahCevitcAneewteB Bd06–

etaRwelS RL 51= 0Ω sµ/V0011

niaGlaitnereffiD RL 51= 0Ω %70.0

esahPlaitnereffiD RL 51= 0Ω ˚50.0

emiTtceleSlennahC RL 51= 0Ω V, NI V1= sn5.2

emiTelbanE RL 51= 0Ω sn01

gniwSegatloVtuptuO RL 51= 0Ω V3±rorrEniaG RL 51= 0Ω V, NI V1±= %4

egatloVtesffOtuptuO Vm02

tnerruCylppuS slennahCeerhTllA Am03

delbasiDtnerruCylppuS Aµ1

Table 1. LT1675 performance, VS = ±5V

Active

a 25MHz square wave with Chip Select= 0V. In this example, the gain error isjust –0.23dB. The response to tog-gling between IC1 and IC2 with ChipSelect is shown in Figure 7. In thiscase red 1 input is connected to 0V,and red 3 is connected to an uncor-related sine wave.

Figure 5. Two LT1675s build a 4-inputRGB router.

Figure 6. Square wave response: chipselect = 0V, IC 2 disabled

Figure 7. Toggling the 4-input router:Red 1 input = 0V; Red 3 input =uncorrelated sine wave



DESIGN FEATURES

LT1468: An Operational Amplifierfor Fast, 16-Bit Systems by George Feliz

IntroductionThe LT1468 is a single operationalamplifier that has been optimized foraccuracy and speed in 16-bit sys-tems. Operating from ±15V supplies,the LT1468 in a gain of –1 configura-tion will settle in 900ns to 150µV fora 10V step. The LT1468 also featuresthe excellent DC specificationsrequired for 16-bit designs. Input off-set voltage is 75µV max, input biascurrent is 10nA maximum for theinverting input and 40nA maximumfor the noninverting input and DCgain is 1V/µV minimum. The LT1468specifications are summarized inTable 1. Two key applications thatillustrate its use are current-to-volt-age (I/V) conversion following a fast,16-bit current output digital-to-ana-log converter (DAC), such as LTC1597(Figure 1), and buffering the input ofan analog-to-digital converter (ADC),such as the 333ksps LTC1604 (Fig-ure 2). Both applications will bediscussed in detail to highlight theLT1468 design requirements andtrade-offs.

16-Bit DACCurrent-to-Voltage Converterwith 1.7µs Settling TimeThe key AC specification of the circuitof Figure 1 is settling time as it limitsthe DAC update rate. The settlingtime measurement is an exception-ally difficult problem that has beenably addressed by Jim Williams,beginning in the August 1998 issue

and concluding in this issue of LinearTechnology magazine and, in greaterdetail, in Linear Technology Applica-tion Note 74. Minimizing settling timeis limited by the need to null the DACoutput capacitance, which varies from70pF to 115pF, depending on code.This capacitance at the amplifier inputcombines with the feedback resistorto form a zero in the closed-loop fre-quency response in the vicinity of200kHz–400kHz. Without a feedbackcapacitor, the circuit will oscillate.The choice of 20pF stabilizes the cir-cuit by adding a pole at 1.3MHz tolimit the frequency peaking and ischosen to optimize settling time. Thesettling time to 16-bit accuracy istheoretically bounded by 11.1 timeconstants set by the 6kΩ and 20pF.Figure 1’s circuit settles in 1.7µs to150µV for a 10V step. This comparesfavorably with the 1.33µs theoreticallimit and is the best result obtainablewith a wide variety of LTC and com-petitive amplifiers. This excellentsettling requires the amplifier to befree of thermal tails in its settlingbehavior.

The LTC1597 current output DACis specified with a 10V reference input.The LSB is 25.4nA, which becomes153µ V after conversion by theLT1468, and the full-scale output is1.67mA, which corresponds to 10Vat the amplifier output. The zero-scale offset contribution of the LT1468is the input offset voltage and the

inverting input current flowingthrough the 6k feedback resistor. Thisworst-case total of 135µV is less thanone LSB. At full-scale there is aninsignificant additional 10µV of errordue to the 1V/µV minimum gain ofthe amplifier. The low input offset ofthe amplifier ensures negligible deg-radation of the DAC’s outstandinglinearity specifications.

With its low 5nV/√Hz input voltagenoise and 0.6pA/√Hz input currentnoise, the LT1468 contributes onlyan additional 23% to the DAC outputnoise voltage. As with any precisionapplication, and particularly with widebandwidth amplifiers, the noise band-width should be minimized with anexternal filter to maximize resolution.

ADC BufferThe important amplifier specificationsfor an analog-to-digital converterbuffer application (Figure 2) are lownoise and low distortion. The LTC160416-bit ADC signal-to-noise ratio (SNR)

–

+LTC1597

DAC INPUTS

10V

VREF6k

20pF

DAC COUT 70pF–115pF

LT1468

–15V

15V

2k

50pF

OPTIONAL NOISE FILTER

VOUT

16

1LSB = 25.4nA FULL SCALE = 1.67mA 10V

153µV

Table 1. LT1486 key specifications

egatloVtesffOtupnI xaMVµ57

tnerruCsaiBtupnIgnitrevnI xaMAn01saiBtupnIgnitrevninoN

tnerruCxaMAn04

niaGCD niMVµ/V1

RRMC niMBd69

egatloVesioNtupnI zH/Vn5

tnerruCesioNtupnI zH/Ap6.0

htdiwdnaBniaG zHM09

etaRwelS sµ/V22

V10rofDHT P-P zHk001, Bd6.59–,Vµ051otemiTgniltteSCAD

petSV01sµ7.1

AV otemiTgniltteS1–=petSV01,Vµ051

sn009

V,tnerruCylppuS S V51±= xaMAm2.5

(Figure 1's Circuit)

Figure 1. 16-bit DAC I/V converter with 1.7µs settling time


DESIGN FEATURES

of 90dB implies 56µVRMS noise at theinput. The noise for the amplifier,100Ω/3000pF filter and a high value10kΩ source is 15µVRMS, whichdegrades the SNR by only 0.3dB. TheLTC1604 total harmonic distortion(THD) is a low –94dB at 100kHz. Thebuffer/filter combination alone has2nd and 3rd harmonic distortion bet-ter than –100dB for a 5VP-P, 100kHzinput, so it does not degrade the ACperformance of the ADC.

The buffer also drives the ADCfrom a low source impedance. With-out a buffer, the LTC1604 acquisitiontime increases with increasing sourceresistance above 1k and therefore themaximum sampling rate must bereduced. With the low noise, low dis-tortion LT1468 buffer, the ADC canbe driven at maximum speed fromhigher source resistances withoutsacrificing AC performance.

The DC requirements for the ADCbuffer are relatively modest. Theinput offset voltage, CMRR (96dBminimum) and noninverting inputbias current through the source resis-tance, RS, affect the DC accuracy,

but these errors are an insignificantfraction of the ADC offset and full-scale errors.

Circuit DescriptionA simplified schematic of LT1468 isshown in Figure 3. The circuit is asingle, folded-cascode gain stage forfast settling and high bandwidth. Theinputs are PNP transistors Q1 and Q2with bias current cancellation fromcurrent source I7–Q12 to match Q1and Q2, and the current mirror com-posed of Q13, Q14 and Q15. I7 istrimmed to minimize the invertinginput current (critical for errors inDAC I/V circuits). The input devicesare protected by 100Ω resistors andback-to-back diodes D1 and D2. Thecollectors of Q1 and Q2 are loaded bycurrent sources I3 and I4 and theemitters of cascode transistors Q3and Q4. I3 and I4 are trimmed to nullthe input offset voltage.

The mirror formed by Q5 and Q6performs differential-to-single endedconversion into the high gain node atthe collectors of Q4 and Q6. Toincrease the gain of this single stage,

–

+VINRS

LT1468

15V

–15V

100Ω

3000pF

530kHz NOISE FILTER

LTC160416

ADC OUTPUTS

5V

–5V

I7 50µA

I1 100µA

I2 400µA

I5 350µA

2mA

Q12

Q13

Q3

Q2

Q4

Q5

Q14

Q15

Q1

Q6

C1 4pF

Q7

Q8Q9

Q11

Q10

D2

D1100Ω 100Ω

I3 150µA

I4 150µA

I6 350µA

OUT

+IN –IN

BIAS

C2 10pF

2k 2k 1k

V–

V+

the Q5–Q6 mirror is bootstrapped byfollower Q7 and current source I2 sothat the mirror floats with the outputlevel. With this scheme, Q6 neversees a change in base-collector volt-age and does not degrade the gainwith its output impedance, which is afactor of 5–10 lower than that of NPNsQ3 and Q4. By choosing I2 so that Q7runs at twice the collector current ofQ5–Q6, the base current of Q7 bal-ances the combined base currents ofQ5 and Q6. A benefit of this balanceddesign is low offset voltage drift(2µV/°C maximum).

The output stage is formed by Q8,Q9, Q10 and Q11 and current sourcesI5 and I6. This stage further buffersthe gain node from the output. Thepath from the emitter of Q7 to theoutput has symmetrical current gain,as it contains both an NPN and PNP,whether sourcing or sinking current.This balance reduces 2nd harmonicdistortion.

Frequency compensation is set bycapacitor C1 on the gain node for a90MHz gain bandwidth at 100kHz.Capacitor C2 rolls off the mirror gain,which produces a pole-zero pair sothat the open-loop response reachesunity gain at 25MHz with 42° of phasemargin. C2 is bootstrapped to theoutput so that it does not degradeslew rate. The gain and phase versusfrequency are shown in Figure 4. Slewrate is set by I1 and C1 and is typi-cally 22V/µs.

Design Trade-OffsPrevious precision designs hadmultiple gain stages and highly bal-anced configurations. The price paidby these classic designs is lack of

FREQUENCY (Hz)

GAIN

(dB)

10M

1418_02a.EPS

70

60

50

40

30

20

10

0

–1010k 100k 1M 100M

PHASE

GAIN

100

80

60

40

20

0

–20

–40

–60

PHASE (DEGREES)

Figure 2. ADC buffer

Figure 3. LT1468 simplified schematic

Figure 4. LT1468 gain and phase vs frequency


DESIGN FEATURES

bandwidth, slew rate and settling time.The LT1468 uses a single stagetopology to obtain excellent AC speci-fications with high bandwidth andstate-of-the-art 16-bit settling. Thedemands of precision dictate a fullybalanced design and painstaking carein the die layout. The AC perfor-mance is ultimately limited, however,by the need for high gain and lowinput bias current. High gain requiresbootstrapping the current mirror inthe signal path, which degrades phasemargin at high frequency. For thisreason the mirror is compensated tolower the unity-gain frequency of theamplifier, which reduces bandwidthat low closed-loop gains.

To obtain low input bias current,the choice of operating currents islimited by the accuracy of the inputbias current cancellation circuitry.With trimming, up to a 50× reduction

VS = ±15V TA = 25°C f = 10kHz

SOURCE RESISTANCE, RS (Ω)

TOTA

L NO

ISE

VOLT

AGE

(nV/

√Hz)

100k

1468_05.eps

100 1k 10k

100

10

1

0.1

RESISTOR NOISE ONLY

TOTAL NOISE

RS

–

+

in IB can be achieved. This constraintsets the maximum value of currentsource I1, which also places limits onbandwidth, slew rate, noise voltageand noise current. The LT1468 totalnoise is best with source resistance inthe 1kΩ to 20kΩ region, where any

increase in noise is due to the resistor(Figure 5).

It should be noted that the inputbias current cancellation current isnot bootstrapped to the input stage toprovide constant IB vs input commonmode voltage. The reason is simple:this circuitry runs at submicroampcurrent levels and has no chance ofsettling if it is allowed to move withthe inputs. The IB is optimized forinverting configurations with a con-stant input voltage and providesexcellent settling.

ConclusionThe LT1468 has an unequaled blendof speed and precision that is ideal for16-bit applications. Its unique virtuesalso provide outstanding performancein low distortion active filters andprecision instrumentation.

Figure 5. Total noise vs unmatchedsource resistance

discrete pulses. The output capacitormust supply the entire load currentfor at least a portion of the switchingcycle, so output capacitor ripple cur-rent rating and ESR may be an issue.Maximum available output currentwill usually be a strong function ofinput voltage. Supporting low VIN-to-VOUT ratios may require additionalcomponents for maintaining control-

loop stability. A detailed theoreticalanalysis of this topology and itsbehavior can be found in Linear Tech-nology Application Note 44.

ConclusionThe LT1676 and LT1776 provide ex-cellent efficiency in high input voltage/low output voltage switching regula-tor applications. This LT1776’s 8-pin

SO package and 200kHz switchingrate are especially useful in imple-menting compact power supplysolutions. These devices’ innate abil-ity to avoid pulse skipping under lightloads, plus the optional sync func-tion, aid in controlling the frequencyspectrum of switching-generatednoise.

LT1676/LT1776, continued from page 9


PerformanceTable 1 summarizes the major per-formance specifications of theLT1675; Figure 8 shows a graph ofcrosstalk.

ConclusionBy taking full advantage of LTC’s newcomplementary high speed bipolarprocess, the LT1675 RGB multiplexerdramatically raises the level of per-

FREQUENCY (Hz)

CROS

STAL

K RE

JECT

ION

(dB)

100M

1418_02a.EPS

20

10

0

–10

–20

–30

–40

–50

–60

–70

–80100k 1M 10M 1G

RS = 75Ω RL = 150Ω GREEN 1 DRIVEN RED 1 SELECTED

RS = 75Ω RL = 150Ω GREEN 1 DRIVEN RED 1 SELECTED

formance while saving PC boardspace. A channel-to-channel togglerate of 100MHz makes the LT1675perfect for pixel switching and thesimple expansion feature using theENABLE pin is ideal for RGB routing.A fixed gain of two for driving doubleterminated cables simplifies PC boardlayout and boosts performance. Thesehigh per formance multiplexerscomplement the large number of videoproducts offered by LTC.

Figure 8. LT1675 crosstalk rejection vsfrequency

LT1675, continued from page 17


DESIGN FEATURES

LTC1622: Low Input Voltage,Current Mode PWM Buck Converter

by San-Hwa CheeIntroductionThe push for 2.5V system suppliescontinues unabated as manufactur-ers introduce more parts that operateat this low voltage. The rewards aregreat, especially for battery-poweredequipment, since the lower voltagereduces power consumption andthereby extends the time betweenbattery replacements or recharges.With a 2.5V system supply, operationfrom a single lithium-ion batterybecomes highly attractive, becauseits end-of-charge voltage is 2.7V andit has the most energy per volumecompared to NiCd and NiMH.

The 8-pin LTC1622 step-down DC/DC controller is designed to help sys-tem designers harness all of theavailable energy from lithium-ionbatteries in several ways. Its wideoperating input-voltage range (2.0Vto an absolute maximum of 10V) and100% duty cycle allows low dropoutfor maximum energy extraction fromthe battery. The part’s low quiescentcurrent, 400µA, with a shutdown cur-rent of 15µA, extends battery life. Itsuser-selectable Burst Mode opera-tion enhances efficiency at low loadcurrent.

For portable applications whereboard space is a premium, theLTC1622 operates at a constant fre-quency of 550kHz and can besynchronized to frequencies of up to

750kHz. High frequency operationallows the use of small inductors,making this part ideal for communi-cations products. The LTC1622 comesin a tiny 8-lead MSOP package, pro-viding a complete power solution whileoccupying only a small area.

The LTC1622 uses a pulse-width,current mode architecture, whichprovides excellent AC and DC loadand line regulation. Peak inductorcurrent is set by an external senseresistor. This allows the design to beoptimized for each application. A soft-start pin allows the LTC1622 to powerup gently.

A Detailed Lookat the LTC1622The LTC1622 is a constant-frequency,pulse-width-modulated, currentmode switching regulator. In normaloperation, the external P-channelpower MOSFET is turned on duringeach cycle when the oscillator sets alatch and turned off when the currentcomparator resets the latch. The peakinductor current at which the currentcomparator resets the latch is con-trolled by the voltage on the ITH pin,which is the output of the erroramplifier, gm. An external resistivedivider connected between VOUT andground allows gm to receive an outputfeedback voltage, VFB. When the load

current increases, it causes a slightdecrease in VFB relative to the 0.8Vreference, which, in turn, causes theITH voltage to increase until the aver-age inductor current matches the newload current. (For a more detaileddescription, please refer to theLTC1622 data sheet.)

The value of the RSENSE is chosenbased on the required output current.The LTC1622 current comparator hasa maximum threshold of 100mV/RSENSE. The current-comparatorthreshold sets the peak of the induc-tor current, yielding a maximumaverage output current equal to thepeak value minus one-half the peak-to-peak inductor ripple current. Forapplications where the duty cycle is

+

+ SENSE–

PDRV

GND

VFB

VIN

ITH

SYNC/MODE

RUN/SS

1

7

6

3

8

2

5

4

C1 10µF 16V R1

10kC3

220pF

470pF

R2 0.03Ω

Si3443DV

D1

L1 4.7µH

R3 159k

R4 75k

C2 47µF 6V

VOUT 2.5V/1.5A

LTC1622VIN 2.5V–8.5V

C1: MURATA CERAMIC GRM235Y5V106Z (814) 236-1431 C2: SANYO POSCAP 6TPA47M (619) 661-6835 L1: MURATA LQN6C-4R7M04

D1: IR10BQ015 (310) 322-3331 R2: DALE, 0.25W (605) 665-9301

LOAD CURRENT (A)

60EFFI

CIEN

CY (%

)

70

80

90

100

0.001 1.000

50

0.01040

0.100

VIN = 3.3V

VIN = 6V

VIN = 4.2V

VIN = 8.4V

VOUT = 2.5V RSENSE = 0.03Ω

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

0.001 1.0000.010 0.100

VIN = 3.3V

VIN = 6V

VIN = 4.2V

VIN = 8.4V


100

90

80

70

60

50

40

Figure 1. LTC1622 typical application: 2.5V/1.5A converter

Figure 2. Efficiency vs load current for Figure1’s circuit (Burst Mode enabled)

Figure 3. Efficiency vs load current for Figure1’s circuit (Burst Mode disabled)


DESIGN FEATURES

Figure 4. Transient response with Burst Modeenabled; load step = 50mA to 1.2A

Figure 5. Transient response with Burst Modeinhibited; load step = 50mA to 1.2A

high (> 80%), the value of the senseresistor is set to approximately 50mV/IOUTMAX to account for the effect ofslope compensation. Under short-cir-cuit conditions, the frequency of theoscillator will be reduced to about120kHz. This low frequency allowsthe inductor current to safely dis-charge, thereby preventing currentrunaway.

The LTC1622 includes protectionagainst output overvoltage conditionsor transients. An overvoltage com-parator monitors the output voltageand forces the external MOSFET offwhen the feedback voltage has risento 8% above the reference voltage(0.8V).

Burst Mode OperationThe LTC1622’s Burst Mode operationis enabled at low load currents simplyby connecting the SYNC/MODE pinto VIN or letting it float. In this mode,the minimum peak current of theinductor is set to 0.36V/RSENSE eventhough the voltage at the ITH pin wouldindicate a lower value. If the inductor’saverage current is greater than theload requirement, the voltage at theITH pin will drop as VOUT rises slightly.When the ITH voltage goes below 0.12V,a sleep signal is generated, turningoff the external MOSFET. The loadcurrent is now supported by the out-put capacitor. The LTC1622 willresume normal operation when theITH voltage goes above 0.22V. For fre-quency-sensitive applications, BurstMode operation is inhibited by con-

necting the SYNC/MODE pin toground. In this case, constant-fre-quency operation will be maintainedat a lower load current together withlower output ripple. If the load cur-rent is low enough, cycle skipping willoccur to maintain regulation.

Frequency SynchronizationThe LTC1622 can be externally drivenby a clock signal of up to 750kHz.Synchronization is inhibited when thefeedback voltage is below 0.3V. Thisis done to prevent inductor currentbuild-up under short-circuit condi-tions. Burst Mode operation isinhibited when the LTC1622 is drivenby an external clock.

Undervoltage Lockout andDropout OperationAn undervoltage lockout circuit isincorporated into the LTC1622. Whenthe input voltage drops below 2.0V,most of the LTC1622 circuitry will beturned off, reducing the quiescentcurrent from 400µA to several micro-amperes and forcing the externalMOSFET off.

The LTC1622 is capable of turningthe external P-channel MOSFET oncontinuously (100% duty cycle) whenthe input voltage falls to near theoutput voltage. In dropout, the out-put voltage is determined by the inputvoltage minus the voltage drop acrossthe MOSFET, the sense resistor andthe inductor resistance.

RUN/Soft-Start PinThe RUN/SS pin is a dual-functionpin that provides the soft-start func-tion and a means to shut down theLTC1622. An internal current sourcecharges an external capacitor. Whenthe voltage on the Run/SS pin reaches0.65V, the LTC1622 begins operat-ing. As the voltage on the RUN/SScontinues to increase linearly from0.65V to 1.8V, the internal currentlimit also increases proportionally.The current limit begins at 0A (atVRUN/SS = 0.65V) and ends at 0.10V/RSENSE (VRUN/SS > 1.8V); therefore,this pin can be used for power supplysequencing.

2.5V/1.5AStep-Down RegulatorA typical application circuit using theLTC1622 is shown in Figure 1. Thiscircuit supplies a 1.5A load at 2.5Vwith an input supply between 2.7Vup to 8.5V. The 0.03Ω sense resistoris selected to ensure that the circuit iscapable of supplying 1.5A at a lowinput voltage. In addition, a sublogicthreshold MOSFET is used, since thecircuit operates at input voltages aslow as 2.7V. The circuit operates atthe internally set frequency of 550kHz.A 4.7µH inductor is chosen so thatthe inductor’s current remains con-tinuous during burst periods at lowload current. For low output voltageripple, a low ESR capacitor (100mΩ)is used.

OUTPUT VOLTAGE(AC COUPLED)

0.1V/DIV

0.1ms/DIV


0.1V/DIV

0.1ms/DIV


DESIGN FEATURES

Efficiency ConsiderationsThe efficiency curves for Figure 1’scircuit are shown in Figures 2 and 3.Figure 2 shows the efficiency withBurst Mode enabled, whereas Figure3 has Burst Mode defeated. Note that,at low load currents, the efficiency ishigher with Burst Mode operation.However, constant frequency opera-tion is still achievable at a lower loadcurrents with Burst Mode operationdefeated. The kinks in the efficiencycurves indicate the transition out ofBurst Mode operation.

The components of Figure 1 havebeen carefully chosen to provide theamount of output power using a mini-mum of board space. Efficiency isalso a prime consideration in select-ing the components, as illustrated inFigures 2 and 3. Figures 4 and 5 showthe transient response of VOUT with aload step from 50mA to 1.2A. Figure4 has Burst Mode enabled, while Fig-ure 5 has it defeated. Note that theoutput voltage ripple (in the middleportion of the photographs) is higher

for Burst Mode operation than withBurst Mode disabled at 50mA loadcurrent.

Applications that require bettertransient response can use the cir-cuit in Figure 6, whose componentsare selected specifically for thisrequirement. Figures 7 and 8 showthe response with and without BurstMode operation, respectively. Notethat the transient response has beenenhanced significantly. However, thiscomes at the expense of slightlyreduced efficiency at low load cur-rents, as indicated by the efficiencycurves of Figures 9 and 10.

ConclusionAlthough the LTC1622 comes in atiny 8-pin MSOP, it is packed withfeatures that are not normally foundin other DC/DC converters. Its abilityto operate from input voltages as lowas 2.0V makes it attractive for singlelithium-ion battery-powered applica-tions. Features like Burst Mode and100% duty cycle ensure that energy

from the battery is used efficientlyand charge is extracted down to thelast coulomb. For telecommunicationsproducts, where noise generated by aswitching regulator may spell trouble,the synchronizable LTC1622 canoperate at a constant frequency, mak-ing noise a nonissue for systemdesigners.

Figure 7. Transient response with Burst Modeenabled; load step = 50mA to 1.2A

Figure 8. Transient response with Burst Modeinhibited; load step = 50mA to 1.2A

+

+ SENSE–

PDRV

GND

VFB

VIN

ITH

SYNC/MODE

RUN/SS

1

7

6

3

8

2

5

4

C1 47µF 16V R1

22kC3

100pF

470pF

R2 0.03Ω

Si3443DV

D1

L1 1.3µH

R3 159k

R4 75k

C2 100µF 6V

VOUT 2.5V/1.5A

LTC1622VIN 2.5V–8.5V

C1: AVX TPSD476M016R0150 (803) 946-0362 C2: AVX TPSD476M016R0065 L1: MURATA LQN6C-1R5M04 (814) 237-1431

D1: IR10BQ015 (310) 322-3331 R2: DALE, 0.25W (605) 665-9301

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

100

90

80

70

60

50

400.001 1.0000.010 0.100

VIN = 3.3V

VIN = 6V

VIN = 8.4V


VIN = 4.2V

LOAD CURRENT (A)

EFFI

CIEN

CY (%

)

100

90

80

70

60

50

400.001 1.0000.010 0.100

VIN = 3.3V

VIN = 6V

VIN = 8.4V


VIN = 4.2V

Figure 9. Efficiency vs load current forFigure 6’s circuit (Burst Mode enabled)

Figure 10. Efficiency vs load current forFigure 6’s circuit (Burst Mode disabled)

Figure 6. 2.5V/1.5A converter with improved transient response

0.1ms/DIV


0.1V/DIV


0.1V/DIV

0.1ms/DIV


DESIGN FEATURES

LTC1531 Isolated Comparator

IntroductionThe LTC1531 is an isolated, self-pow-ered comparator that receives powerand communicates through internalisolation capacitors. The internal iso-lation capacitors provide 3000VRMSof isolation between the comparatorand its output. This allows the part tobe used in applications that requirehigh voltage isolated sensing withoutthe need to provide an isolated powersource. The isolated side provides a2.5V pulsed reference output thatcan deliver 5mA for 100µs using thepower stored on the isolated externalcapacitor. A 4-input, dual-differen-tial comparator samples at the end ofthe reference pulse and transmits theresult back to the nonisolated side.The nonisolated, powered side latchesthe result of the comparator and pro-vides a zero-cross comparator outputfor triggering a triac. Typical applica-tions include isolated temperaturesensing and control, isolated voltagemonitoring and other sensing appli-cations riding on top of high commonmode voltages, such as the AC powerline.

Basic OperationThe block diagram in Figure 1 showsthe basic components of the LTC1531.The nonisolated powered side togglesbetween pumping AC voltage throughthe capacitive barrier to the isolatedside, where it is rectified and storedon an external capacitor tied to VPW,and listening for a comparison result.When the isolated-side VPW voltagereaches 3.3V, the comparison cir-cuitry is enabled. On the next listencycle, the 2.5V VREG output pulses onfor 100µs, at the end of which acomparison is done, with the resulttransmitted back to the nonisolatedside. If a valid result is received, theDATA output is updated and theVALID output pulses on for 1ms. Whenthe latched DATA output is high, thezero-cross comparator output is en-abled for firing a triac whenever thezero-cross comparator inputs passthrough 0V.

Figure 2 represents a typical VPWstart-up sequence, showing VREG out-put pulses after VPW reaches 3.3V.Thereafter, whenever VPW reaches3.3V the comparator samples during

the next listen period in the power/listen cycle. Figure 2 shows typicalsampling with light loading on VREG.Sampling is not uniform but dependson the combination of VPW = 3.3V andthe 800Hz power/listen cycle. Thecomparator samples at a typical rateof 200Hz–300Hz. The actual sam-pling rate depends on the internaland external loading on the 2.5V VREGoutput and the charging rate to the

VOLTAGE PUMP

TRANSMIT AND

DRIVER

TIMING

POWERED SIDE ISOLATED SIDE

TIMING

DECODE

POWER-ON RESET

VALID

Q D

R

25

VCC

VCC

1

DATA 26

ZCDATA

ZERO-CROSS COMPARATOR

27

GND

ZCPOS ZCNEG SHDN

28 4 3 2

LATCH

12CMPOUT

14

ISOGND

ISOLATION BARRIER

1531 BD

V2

18V1

Σ

Σ

13VREG

11VPW

–

+

–

+

2.5V REG

3.3V DET

COMPARE

17

15V4

16V3VCC

VCC

TIME (ms)0

V PW

(V)

3.3

2.5

1531 F01

100 200 300

NOTES: VRIPPLE DEPENDS ON CVPW AND IVPW + IVREG tSAMPLE DEPENDS ON IVPW + IVREG

tSAMPLE

VREF

VPW

VCC = 5V CVPW = 1µF IVREG = 5mA

VRIPPLE

Figure 1. LTC1531 block diagram

Figure 2. Typical VPW power-up and VREGsamples

by Wayne Shumaker


DESIGN FEATURES

external capacitor on VPW. This charg-ing rate, through the internal isolationcapacitors to VPW, can be modeled asa 100k source resistance and a 5.5Vsource with VCC = 5V. Figure 4 showstypical sampling periods for differentload currents and supply voltages.The sample rate does not depend onthe external storage capacitor, whosevalue should be chosen to minimizeripple on VPW for different VREG loads.VPW can also be used to power con-tinuous, low current circuits, such asthe LT1495 op amp or the LTC1540comparator, provided that such cir-cuits do not prevent VPW from reaching3.3V.

Isolated ComparatorThe LTC1531 isolated switchedcapacitor comparator has four inputsthat sum the voltages together toperform the following comparison:

(V1 + V2)/2 > (V3 + V4)/2By rearranging the equation, for

example, a dual differential compari-son can be performed:(V1 – V4) > (V3 – V2) or (V1 – V3) > (V4– V2)

The comparator inputs have a rail-to-rail input range. They sample onceat the end of the 100µs VREG pulse.Their summing nature allows mid-VREG referencing, for example, byconnecting V3 to VREG and V4 toISOGND, which sums together to pro-vide 1.25V for the negative comparatorinput. In the isolated temperaturecontrol application (Figure 5), thecomparator is used to compare thevoltage across the thermistor to thevoltage across R4, with (V1 – V3) > (V4– V2).

The isolated comparator has anisolated output, CMPOUT, which canbe used for hysteresis. This output isHi-Z except when VREG is on; then theoutput is either 2.5V or 0V, depend-ing on the result of the previouscomparison. This output, in combi-nation with the comparator, can beused to create a delta-sigma modula-tor for transmitting isolated voltagesignals across the isolation barrier,as in the isolated voltage sense appli-cation (Figure 6).

ApplicationsThe LTC1531 can be used to isolatesensors such as in the isolated ther-mistor temperature controller inFigure 5. In this circuit, a comparisonis made between the voltages across a

thermistor and a resistor that is drivenby the 2.5V VREG output. As thethermistor resistance rises with tem-perature, the voltage across thethermistor increases. When it exceedsthe voltage across R4, the compara-tor output becomes zero and the triaccontrol to the heater is turned off.Hysteresis can be added in the tem-perature control by using CMPOUTand R5. A 10° phase-shifted AC linesignal is supplied through R1, R2 andC1 to the zero-cross comparator forfiring the triac.

In the overtemperature detectapplication in Figure 6, an isolatedthermocouple is cold junction com-pensated with the micropower LT1389reference and the Yellow Springs ther-mistor. The micropower LT1495 opamp provides gain to give an overall0°C–200°C temperature range,adjustable by changing the 10M feed-back resistor. The isolated comparatoris connected to compare at 1.25V or

TIME (ms)0

V REG

(V)

2.5

3.3

0

1531 F02

2010 30 40

VCC = 5V, CVPW = 1µF IVREG = 100µA

NOTE: NONPERIODIC SAMPLES DUE TO DEPENDENCE ON VPW > 3.3V AND THE POWER-LISTEN CYCLE SAMPLING

IVREG (mA)

t SAM

PLE

(ms)

1531 F03

30

25

20

15

10

5

00 1 2 3 4

VCC = 4.5V

VCC = 5.5V

VCC = 5V

5.6V

AC 120V

NEUTRAL

HEATER 25Ω

ISOGND

V1

V2

V3

V4

ISOLATION BARRIER

1531 TA01

VALID

GND

390Ω

R5 HYSTERESIS

1M

R1/(R1 + R2) = ATTENUATION R2 • C1 = Tan(θ)/(2π60Hz) θ = DESIRED PHASE LAG

COMPARISON V1 – V3 > V4 – V2R = RO • exp (B/T – B/TO) B = 3807 TO = 298°K

2.5V

100µF

1µF

LTC1531

R2 47k

R1 680k

150Ω

+

–

THERM 30k YSI 44008

R4 50k

VPWVCC SHDN

CMPOUT

VREG

ZCDATA

ZC + ZC –

DATA

LED1k

Q D

C1 0.01µF2.5k

5W

+

+

IN4004

TECCOR Q4008L4

OR EQUIVALENT

2N2222 OR

2N3904

Figure 3. Typical VREG and VPWwith IVREG

= 100µA

Figure 4. Typical average tSAMPLE vs IVREG

Figure 5. Isolated thermistor temperature controller


DESIGN FEATURES

ISOGND

V1

V2

V3

V4

1531 TA08

VALID

GND

ISOLATION BARRIER

10M

33k10.2k

1M

2.5V

2.2µF LT1389

LTC1531

+

–

VPWVCC

VCC

VTRIP

SHDN

CMPOUT

VREG

ZCDATA

ZC + ZC –

DATAQ D

+

–

+

–

+

LT1495

1.74M

1.13k

GAIN SET FOR 0°C TO 200°C

UNUSED OP AMP

10.7k

K

THERM 30k YSI 44008

–

+

LT1495COLD JUNCTION COMPENSATES 0°C TO 60°C OUTPUT, VTRIP = 1 AT ≥100°C RESPONSE TIME = 10 sec RESOLUTION = 4mV ≥ 0.5°C

the center of the temperature range.In this case, VTRIP goes high when thetemperature exceeds 100°C.

The LTC1531 can use the highimpedance nature of CMPOUT as aduty-cycle modulator, as in the iso-lated voltage sense application inFigure 7. The duty-cycle output of thecomparator is smoothed with the

LT1490 rail-to-rail op amp to repro-duce the voltage at VIN. The outputtime constant, R2 • C2, shouldapproximately equal the input timeconstant, 35 • R1 • C1. The factor of35 results from CMPOUT being on foronly 100µs at an average sample rateof 300Hz.

ConclusionThe LTC1531 is a versatile part forsensing signals that require large iso-lation voltages. The ability of theLTC1531 to supply power throughthe isolation barrier simplifies appli-cations; it can be combined with othermicropower circuits in a variety ofisolated signal conditioning and sens-ing applications.

VOUT 0V – VCC

FULL-SCALE OUTPUT

ISOGND

V1

V2

V3

V4

1531 TA05

VALID10k

GND R1 1M

ISOLATION BARRIER RESOLUTION = 4mV

SETTLING TIME CONSTANT = 10 sec

2.5V

2.2µF

0V TO 2.5V FULL-SCALE INPUT

C1 0.22µF

VIN

LTC1531

+

–

VPWVCC

VCC

VCC

VCC

SHDN

CMPOUT

VREG

ZCDATA

ZC + ZC –

DATA

10k

R3 10M

Q D

R2 10M

C2, 1µF

+

–

+

LT1490

Figure 6. Overtemperature detect

Figure 7. Isolated voltage detect



www.linear-tech.com


DESIGN IDEAS

PolyPhase Switching RegulatorsOffer High Efficiency in Low Voltage,High Current Applications by Craig Varga

IntroductionIn recent years, there has been atendency in the digital world towardsmaller device geometries and highergate counts. This has led to require-ments for lower voltages and highercurrents for logic supplies. As thistrend continues, to levels under 2Vand over 30A, the conventional buckregulator approach ceases to be viable.Switch currents are too high for asingle device to handle, inductorenergy storage exceeds what is avail-

able in surface mount technology andripple current requirements on inputcapacitors dictate the use of manycapacitors in parallel. Although allthis may seem like enough of achallenge, the transient responserequirements also become much moresevere. The question that arises is: “isthere a topology that can solve all ofthese problems simultaneously? ” Theanswer is “PolyPhase™.”

What is PolyPhase, Anyway?Since it is apparent that multipleFETs need to be paralleled to handlethe current requirements, the ques-tion is whether there is a way to drivethem intelligently, rather than bybrute force. The solution is to staggerthe turn-on times so that the deadbands in the input current waveformare “filled up,” so to speak. In thesimplest implementation, there areessentially two independent synchro-nous buck regulators operating 180°

5 4 6 8

12

AST AST –T +T RET RCC3

1

Q

SYNC1

SYNC2

ISENSE2

ISENSE1

ISENSE1

ISENSE2

SYNC1

SYNC2

Q

OSC

10

11

13

5V

5V

12V 5V

C23 0.47µF

CHARGE PUMP OPTIONAL

U4

CD4047

(POWER FROM 5V)

2 RXRST

CX

9

C6, 100pF, NPO, 5%

R6 3.09k 1%

R3 1k

C22 1µF 10V

C3 22µF 25V

C13 180pF

C21 47µF 10V

C1 1µF 16V

R1 51Ω

R4 1k

C28 0.1µF

+ C7 470µF 6.3V

+

R10 10Ω

R24 39k

+

C35 1µF 10V

C34 1µF 10V

C36 1µF 10V

+VINR13

0.002Ω TRACE

Q1 MMBT3906LT1

D1 BAW56LT1

R12 10k

D4 BAT54

D2 BAT54

D3 BAT54

C18 1000pF

+

R5 9.76k

1% +VOUT 2.5V/30A

OUTPUT RTN

+VIN

INPUT RTN

7 8 5 6

2 1 4 3

U2

LTC1430ACS8

C14 1500pF

C11 470µF 6.3V

+

R14 10k

R28 1Ω

C25 1µF 16V

C19 6800pF

C5 1µF 10V

PVCC2 G2 SHDN COMP

PVCC1 G1 FB

GND

R22 1Ω

R23 1Ω

5V12V

CHARGE PUMP OPTIONAL

R20 1Ω

Q2 Si4410DY

Q3 Si4410DY

L2 0.8µH

ETQP1F0R8LB

Q5 Si4410DY

Q4 Si4410DY

R21 1Ω

C10 470µF

6.3V

C32 470µF 6.3V+

7 8 5 6

2 1 4 3

U3

LTC1430ACS8C15 1500pF

C8 470µF 6.3V

C17 1000pF

+

R15 10k

C2 1µF 16V

R29 1Ω

R2 9.76k 1%

C16 180pF

C24 1µF 16V

C20 6800pF

C4 1µF 10V

PVCC2 G2 SHDN COMP

PVCC1 G1 FB

GND

C12 470µF 6.3V

R26 1Ω

R27 1Ω

R19 1Ω

C27, 0.47µF

Q6 Si4410DY

Q7 Si4410DY

L1 0.8µH

ETQP1F0R8LB

Q9 Si4410DY

Q8 Si4410DY

R25 1Ω

R16 10Ω

C9 470µF

6.3V

C33 470µF 6.3V

++

R17 10k, 1%

R11 0.002Ω TRACE

R18 10k 1%

R7 51k

(4)

C30 0.022µF

12V R32 10Ω

R8 4.3k

C26 22µF 25V

+ C29 1µF 16V

C31 0.022µF

C38 3300pF

C37 3300pF

2 76

××

×

48

13+

–

U1 LT1006 SHARE AMPLIFIER

NOTES: 1. ALL RESISTORS = ±5% UNLESS NOTED OTHERWISE. 2. INPUT/OUTPUT CAPACITORS = KEMET T510 SERIES (408) 986-0424 3. TRACE RESISTORS R11, R13 = 0.1" WIDE x 0.675" LONG

R9 4.3k

R31 1k

R30 1k

+

CLOCK

Figure 1. 2-phase synchronous buck regulator



DESIGN IDEAS

out of phase. The net effect of this isthat the input and output ripple cur-rents of the two channels tend tocancel during steady-state operation.This results in significant reductionsin both input and output capacitorrequirements. There is also a fourfoldreduction in the total inductor energystorage requirement, which meansmuch smaller inductors and vastlyimproved transient dynamics. Dur-ing a large load step, the two channelsoperate at maximum duty factor in anattempt to maintain the desired out-put voltage. Both inductor currentsslew rapidly and are now additive,since they are going in the same direc-tion. Hence, the slew rate is doublewhat a single channel could do forequal inductor values. However, dueto the ripple current cancellation dur-ing steady-state conditions, the twoinductors can be reduced to approxi-mately one-half the value that a singlechannel design would require for equalripple currents. Since during slewthey appear to be operating in paral-

lel, the actual slew rate is four timesthat of a single channel design withequal steady-state output ripple cur-rent. Both input and output ripplefrequencies are double those of asingle-channel design, further sim-plifying filtering requirements.

Why Stop at Two?If two channels are good, aren’t morechannels better? In a word, yes. Inprinciple, there is no limit to the num-ber of parallel channels that can beadded. As the number of channels, n,increases, the ripple frequencyincreases to n times the single-chan-nel frequency. Input and output RMSripple currents continue to decrease.Diminishing returns are reached as nrises above three. At three stages, theripple reductions are very substan-tial and dynamic performance isexcellent. Adding more channels pro-duces slight improvements but thedramatic gains will have been real-ized by n = 3. The only real penalty isadded complexity.

Another aspect worth consideringis expandability. It is reasonable withtoday’s technology to build a singlestage, all surface mount, synchro-nous buck regulator capable ofapproximately 15 amps continuousoutput current. At higher current lev-els, power dissipation in individualdevices becomes difficult to manage.Gate drive capability of driver ICs issomewhat limited and is incapable ofdriving enough paralleled MOSFETsto handle larger currents at high fre-quencies. Inductors capable of greater

energy storage cannot be obtained insurface mount technology. Therefore,if currents substantially greater than15 amps are required, it is a simplematter of paralleling additional stagesto obtain the higher currents. For 30amps, use two stages. At 45 amps,use three stages and so on. As morestages are added, the ripple currentsare further reduced, so there is noneed to add large quantities of inputor output capacitors to handle thehigher current capability.

The bottom line is that PolyPhasedesigns offer a considerable reduc-tion in the cost and volume of thepower devices at the expense of a littleadded complexity in the controlcircuitry.

2-Phase Design ExampleThe circuit shown in Figure 1 is a 2-phase, voltage mode–control, synchro-nous buck regulator designed for a5V input and output voltages below3.3V. It is intended to power largememory arrays, ASICs, FPGAs andthe like in server and workstationapplications. The output is capable ofmore than 30 amps continuous atoutputs of 2.5V and below, with peakcurrent capability of greater than 40amps. The design is entirely surfacemount and the maximum height abovethe board is 5.5mm. Overall boardarea is only 4.24 in2. Efficiency isexcellent, as can be seen in the curvein Figure 2. Output ripple voltage isshown in Figure 3. The circuit’sdynamic response to a 10 amp loadstep is shown in Figure 4. The

CURRENT (A)0

EFFI

CIEN

CY (%

)100

95

90

85

80

75

705 10 15 20

DC201 F01b

25 30

VIN = 5V

VOUT = 2V

VOUT = 3.3V

VOUT = 2.5V

2µs/DIV

20mV/DIV

VO = 2.5VVIN = 5V

10µs/DIV

100mV/DIV

Efficiency of Figure 1’s circuit, VIN = 5V

Figure 3. Output ripple with 30A load Figure 4. Transient response with 10A load step (100ns rise time)

∆V = 160mV


DESIGN IDEAS

response is dominated by the outputcapacitor’s ESR and shows the out-put voltage recovered to the originallevel in under 10µs. Figures 5 and 6show how the input and output ripplecurrents cancel.

Circuit OperationThe basic design consists of twoLTC1430CS8-based synchronousbuck regulators connected in paralleland operated 180° out of phase. U4,the CD4047 oscillator, is used to gen-erate the required clock signals andsynchronize the two LTC1430s.Unfortunately, simply connecting tworegulators in parallel is a recipe forinstant disaster. The output voltagesof the two regulators will be slightlydifferent due to normal componenttolerances. Therefore, the higher out-put voltage channel will attempt tosupply the full load current, while thelower voltage output will sink currentfrom the output in a desperate attemptto reduce the output voltage to whereit thinks it should be. The result islike a dog chasing its tail, with largecurrents running around in a circleand going nowhere.

2µs/DIV

A + B

CHANNEL ACHANNEL B

5A/D

IV

IO = 25A2µs/DIV

CHANNEL A5A/DIV

CHANNEL A + B =TOTAL INPUT

RIPPLE CURRENT,UNFILTERED

CHANNEL B5A/DIV

IO = 15Af = 306kHz

Op amp U1 solves this problem.Because the two channels are identi-cal, if the output currents are thesame, the input currents will be also.Low value sense resistors are includedin the input power path to allow thecircuit to measure input current. U1then forces the input current of chan-nel two to match the input current ofchannel one by making small adjust-ments in channel two’s output voltage.It does this by adding or subtractinga small amount of current from chan-nel two’s feedback divider. The twosense resistors are short lengths ofPCB trace and only need to be ratio-metrically accurate. Absolute valueof these resistors is not important(see Linear Technology ApplicationNote 69, Appendix A, for a discussionon how to design trace resistors).

The only remaining trick in thecircuit is the role of Q1 and its asso-ciated circuitry. At start-up, theLTC1430’s clock frequency is sloweddown to approximately 10kHz untilthe output voltage rises to approxi-mately 50% of the desired level. If,during this start-up phase, an attemptis made to synchronize the controller

to a very high frequency, the oscilla-tor ramp amplitude never rises to alevel sufficiently high to trip the PWMcomparator and enable the FET driv-ers. Therefore, the output gets stuckon ground. Q1 fixes this by forcingthe sync signals high during the turn-on transient. Once the output voltagenears its final level, the clock signalsare allowed to synchronize the twoPWM controllers.

ConclusionThe design shown combines the per-formance characteristics that will berequired to power the digital systemsthat will emerge over the next severalyears. Circuits based on these con-cepts will be able to efficiently deliververy high current at low voltage whilerelying on surface mount technologyto maintain low profile and minimumuse of real estate. They will also pro-vide substantially better dynamicperformance than has been availableusing more conventional design meth-odologies and do all of this at areasonable cost.

Figure 5. Ripple cancellation—input Figure 6. Ripple cancellation—output



www.linear-tech.com


DESIGN IDEAS

Level Shift Allows CFA Video Amplifierto Swing to Ground on a Single Supply

A current feedback (CFA) videoamplifier can be made to run off asingle supply and still amplify ground-referenced video with the addition ofa simple and inexpensive level shifter.The circuit in Figure 1 is an amplifierand cable driver for a current outputvideo DAC. The video can be compos-ite or component but it must havesync. The single positive supply is12V but could be as low as 6V for theLT1227.

The output of the LT1227 CFAused here can swing to within 2.5V ofthe negative supply with a 150Ω loadover the commercial temperaturerange of 0°C to 70°C. Five diodes inthe feedback loop are used, in con-junction with C5, to level shift theoutput to ground. The video from theoutput of the LT1227 charges C5 andthe voltage across it allows the outputto swing to ground or even slightlynegative. However, the level of thisnegative swing will depend on the

video signal and so will be unpredict-able. When the scene is black, theremust be sync on the video for C5 toremain charged. A zero-level compo-nent video signal with no sync will notwork with this circuit. The CFA out-put will try to go to zero, or as low asit can, and the diodes will turn off.The load will be disconnected fromthe CFA output and connectedthrough the feedback resistor to thenetwork of R6 and R7. This causesabout 150mVDC to appear at theoutput, instead of the 0V that shouldbe there.

The ground-referenced video sig-nal at the input needs to be levelshifted into the input common moderange of the LT1227 (3V above nega-tive supply). R4 and R5 shift the inputsignal to 3V. In the process, the inputvideo is attenuated by a factor of 2.5.For correct gain, no offset and with azero source impedance, R4 would be1.5k. To compensate for the presence

of R3, R4 is made 1.5k minus R3, or1.46k. The trade off is a gain error ofabout 1.5%. If R4 is left 1.5k, the gainis correct, but there is an offset errorof 75mV. R6, R7 and R8 set the gainand the output offset of the amplifier.A noninverting gain of five is taken tocompensate for the attenuation in theinput level shifter and the cable ter-mination.

The voltage offset on the output ofthis circuit is a rather sensitive func-tion of the value of the input resistors.For instance, an error of 1% in thevalue of R6 will cause an offset of30mV (1% of 3V) on the output. Thisis in addition to the offset error intro-duced by the op amp. Precision resistornetworks are available (BI technolo-gies, 714-447-2345) with matchingspecifications of 0.1% or better. Thesecould be used for the level shiftingresistors, although this would makeadjustments like the one made to R4difficult.

+

+

–

+LT1227

5× 1N4148

R9 75Ω LOAD

R10 75Ω

C3 47µF

C4 0.1µF

C5 4.7µF

R8 1.5kR7 1.5k

R6 499Ω

C2 4.7µF

C1 10µF

FILM

R5 1k

*R4 1.46k

*R3 38.1Ω

*R2 77.37Ω

R1 75Ω

SOURCE

5V12V

75Ω VIDEO SOURCE USED FOR TESTING

*RESISTORS ARE A COMBINATION OF TWO 1% VALUES, R2 IS A SERIES COMBINATION OF 75 Ω AND 2.37Ω R3 IS A PARALLEL COMBINATION OF 75 Ω AND 77.3Ω R4 IS A SERIES COMBINATION OF 1.3k + 160 Ω = 1.46k ALL RESISTORS ARE 1% METAL FILM

B

A

by Frank Cox

Figure 1. Amplifier and cable driver for current-output video DAC



DESIGN INFORMATION

Component and MeasurementAdvances Ensure 16-Bit DACSettling Time (Part Two) by Jim Williams

IntroductionReliable measurement of 16-bit DACsettling time is extremely challeng-ing. Part one of this article (in theAugust 1998 issue of Linear Technol-ogy magazine) described a method formaking this measurement. This sec-ond part discusses detailed circuitryand presents results.

DetailedSettling-Time CircuitryFigure 1 is a detailed schematic of the16-bit DAC settling-time-measure-ment circuitry. The input pulse

switches all DAC bits simultaneouslyand is also routed to the oscilloscopevia a delay-compensation network.The delay network, composed ofCMOS inverters and an adjustableRC network, compensates theoscilloscope’s input step signal forthe 12ns delay through the circuit’smeasurement path. The DACamplifier’s output is compared againstthe LT1236-10V reference via the pre-cision 3k summing resistor ratio set.

The LT1236 also furnishes the DACreference, making the measurementratiometric. The clamped settle nodeis unloaded by A1, which drives thesampling bridge. Note the additionalclamp diodes at A1’s output. Thesediodes prevent any possibility ofabnormal A1 outputs (due to lostsupply or supply sequencing anoma-lies) from damaging the diode array.A3 and associated components tem-

+

7

11 D5

AC BALANCE

2.5kRESIDUE

AMPLIFIER

OUTPUT TO OSCILLOSCOPE 0.01V/DIV = 500µV/DIV AT DAC AMPLIFIER OUTPUT

SAMPLING BRIDGESAMPLING BRIDGE

TEMPERATURE CONTROL

108

4

14

1.1k

Q1

Q4

11

1013

8

7

9 6Q3

5pF

3pF

0.1µF 10µF

510Ω

D633Ω*

1.3k*

Q2

D7

CA3039 ARRAY121 13

–5V

–5V

–5V

SKEW COMP 2.5k

3

2 5

2.2k1.1k

5V

15V15V

–15V

–5V

1k

0.01µF

2.2k 10µF 0.1µF

470Ω

560Ω

51Ω820Ω 51Ω680Ω

500Ω BASELINE

ZERO

62Ω

HEAT

SENSE

: 74HC04

: 1N4148

SAMPLING BRIDGE AND TEMPERATURE CONTROL DIODES: HARRIS CA3039M (800) 442-7747 *1% FILM RESISTOR **VISHAY VHD-200, RATIO SET: 10ppm MATCHING D7 TO D9: 1N5711 Q1, Q2: MRF-501 Q3, Q4: LM3045 ARRAY USE IN-LINE COAXIAL 50Ω TERMINATOR FOR PULSE GENERATOR INPUT. DO NOT MOUNT 50Ω RESISTOR ON BOARD DERIVE 5V AND –5V SUPPLIES FROM ±15V. USE LT317A FOR 5V, LT1175-5 FOR –5V CONSTRUCTION IS CRITICAL—SEE TEXT

Q5 2N2219

1.5k* (SELECT— SEE TEXT)

10k*

10k*

–

+A2

LT1222

–

+A3

LT1012

0.1µF 10µF+

+

VCC RC1

5k

5VWIDTH

SAMPLE DELAY/ WINDOW GENERATOR

5V

5V

74HC123

5V

4.7k

4.7k

20k DELAY

1000pF

5.1k

C1 Q1 Q2 CLR2 B2 A2

A1 B1 CLR1 Q1 Q2 C2 RC2 GND

470pF

AN74 F06

5.1k

REF

5V

15V

LT1236-10

OUTNC IN

47µF TANT0.1µF

510Ω

–10VREF

GNDSAMPLING

BRIDGE DRIVER

SETTLE NODE3k**

–15V

15V

–15V

–15V

DUT LTC1597

CCOMP (SELECT— SEE TEXT)

0V TO 10V TRANSITION

TIME CORRECTED INPUT STEP TO OSCILLOSCOPE

–

+

15pF

1k

5VPULSE

GENERATOR INPUT

50Ω IN-LINE TERMINATION (SEE TEXT AND NOTES)

BRIDGE DRIVER/RESIDUE AMPLIFIER DELAY COMPENSATION ≈12ns AUT

LT1468+

3k**

D8 D9

–

+

A1 LT1220

SAMPLING BRIDGE SWITCHING CONTROL

Figure 1. Detailed schematic of DAC-settling-time measurement circuit; optimum performance requires attention to layout.


DESIGN INFORMATION

perature control the sampling diodebridge by comparing a diodes’s for-ward drop to a stable potential derivedfrom the –5V regulator. Another diode,operated in the reverse direction (VZ ≈7V) serves as a chip heater. The pinconnections shown on the schematichave been selected to provide the besttemperature-control performance.

The input pulse triggers the74HC123 one shot. The one shot isarranged to produce a delayed (con-trollable by the 20k potentiometer)pulse whose width (controllable bythe 5k potentiometer) sets diode bridgeon-time. If the delay is set appropri-ately, the oscilloscope will not see anyinput until settling is nearly complete,eliminating overdrive. The samplewindow width is adjusted so that allremaining settling activity is observ-able. In this way, the oscilloscope’soutput is reliable and meaningful datamay be taken. The one shot’s output

is level shifted by the Q1–Q4 transis-tors, providing complementaryswitching drive to the bridge. Theactual switching transistors, Q1–Q2,are UHF types, permitting true differ-ential bridge switching with less than1ns of time skew.

A2 monitors the bridge output,provides gain and drives the oscillo-scope. Figure 2 shows circuitwaveforms. Trace A is the input pulse,trace B the DAC amplifier output,trace C the sample gate and trace Dthe residue amplifier output. Whenthe sample gate goes low, the bridgeswitches cleanly and the last 1.5mVof slew are easily observed. Ring timeis also clearly visible and the ampli-fier settles nicely to final value. Whenthe sample gate goes high, the bridgeswitches off, with only 600µV of feed-through. The 100µV peak beforebridge switching (at ≈3.5 vertical divi-

sions) is feedthrough from A1’s out-put, but it is similarly well controlled.Note that there is no off-screen activ-ity at any time—the oscilloscope isnever subjected to overdrive.

The circuit requires trimming toachieve this level of performance. Thebridge temperature control point isset by grounding Q5’s base prior toapplying power. Next, apply powerand measure A3’s positive input withrespect to the –5V rail. Select theindicated resistor (1.5k nominal) for avoltage at A3’s negative input (again,with respect to –5V) that is 57mVbelow the positive input’s value.Unground Q5’s base and the circuitwill control the sampling bridge toabout 55°C:

25°C ROOM +

= 30°C RISE = 55°C

57mV 1.9mV/°C DIODE DROP

A = 10V/DIV

B = 10V/DIV

C = 10V/DIV

D = 500µV/DIV

1µs/DIV 1µs/DIV

B = 10V/DIV

A = 10V/DIV

C = 500µV/DIV

Figure 2. Settling time circuit waveforms include time-correctedinput pulse (Trace A), DAC amplifier output (Trace B), sample gate(Trace C) and settling-time output (Trace D). The sample gatewindow’s delay and width are variable.

Figure 3. Settling time circuit’s output (Trace C) with unadjustedsampling bridge AC and DC trims. The DAC is disabled and thesettle node grounded for this test. Excessive switch-drivefeedthrough and baseline offset are present. Traces A and B arethe input pulse and sample window, respectively.

1µs/DIV

B = 10V/DIVA = 10V/DIV

C = 500µV/DIV

B = 500µV/DIV

1µs/DIV

A = 10V/DIV

Figure 5. Oscilloscope display with inadequate sample gatedelay: the sample window (Trace A) occurs too early,resulting in off-screen activity in the settle output (Trace B).The oscilloscope is overdriven, making displayedinformation questionable.

Figure 4. The settling time circuit’s output (Trace C) with thesampling bridge trimmed. As in Figure 3, the DAC is disabled and thesettle node grounded for this test. Switch drive feedthrough andbaseline offset are minimized. Traces A and B are the input pulseand sampling gate, respectively.


DESIGN INFORMATION

The DC and AC bridge trims aremade once the temperature control isfunctional. Making these adjustmentsrequires disabling the DAC andamplifier (disconnect the input pulsefrom the DAC and set all DAC inputslow) and shorting the settle nodedirectly to the ground plane. Figure 3shows typical results before trimming.Trace A is the input pulse, trace B thesample gate and trace C the residueamplifier output. With the DAC-amplifier disabled and the settle nodegrounded, the residue amplifier out-put should (theoretically) always bezero. The photo shows this is not thecase for an untrimmed bridge. AC andDC errors are present. The samplegate’s transitions cause large, off-screen residue amplifier swings (noteresidue amplifier’s response to thesample gate’s turn-off at the ≈8.5 ver-tical division). Additionally, the residueamplifier output shows significant DCoffset error during the sampling inter-val. Adjusting the AC balance and

skew compensation minimizes theswitching induced transients. The DCoffset is adjusted out with the base-line zero trim. Figure 4 shows theresults after making these adjust-ments. All switching-related activityis now well on-screen and offset erroris reduced to unreadable levels. Oncethis level of performance has beenachieved, the circuit is ready for use.Unground the settle node and restorethe input pulse connection to the DAC.

Using the Sampling-BasedSettling Time CircuitFigures 5 through 7 underscore theimportance of positioning the sam-pling window properly in time. InFigure 5 the sample gate delay ini-tiates the sample window (trace A) tooearly and the residue amplifier’soutput (trace B) overdrives the oscil-loscope when sampling commences.Figure 6 is better, with only slight off-screen activity. Figure 7 is optimal.

All amplifier residue is well inside thescreen boundaries.

In general, it is good practice to“walk” the sampling window up to thelast millivolt or so of amplifier slewingso that the onset of ring time isobservable. The sampling basedapproach provides this capability andit is a very powerful measurementtool. Additionally, remember thatslower amplifiers may requireextended delay and/or sampling win-dow times. This may necessitate largercapacitor values in the 74HC123 one-shot timing networks.

CompensationCapacitor EffectsThe DAC amplifier requires frequencycompensation to get the best possiblesettling time. The DAC has appreciableoutput capacitance, complicatingamplifier response and making care-ful compensation capacitor selectioneven more important. Figure 8 showseffects of very light compensation.

1µs/DIV

A = 10V/DIV

B = 500µV/DIV

1µs/DIV

A = 10V/DIV

B = 500µV/DIV

Figure 7. Optimal sample-gate delay positions thesampling window (Trace A) so that all settle output(Trace B) information is well inside screen boundaries.

Figure 6. Increasing the sample-gate delay positionsthe sample window (Trace A) so settle output (TraceB) activity is on-screen.

500ns/DIV

A = 5V/DIV

B = 500µV/DIV

500ns/DIV

A = 5V/DIV

B = 500µV/DIV

Figure 9. Excessive feedback capacitanceoverdamps response (tSETTLE = 3.3µs).

Figure 8. This settling profile with inadequate feedbackcapacitance shows underdamped response. Excessive ringingfeeds through during the sample gate off-period (third through ≈sixth vertical divisions) but is tolerable (tSETTLE = 2.8µs).


DESIGN INFORMATION

Trace A is the time-corrected inputpulse and trace B the residue ampli-fier output. The light compensationpermits very fast slewing but excessiveringing amplitude over a protractedtime results. The ringing is so severethat it feeds through during a portionof the sample gate off-period, althoughno overdrive results. When samplingis initiated (just prior to the sixthvertical division) the ringing is seen tobe in its final stages, although still

offensive. Total settling time is about2.8µs. Figure 9 presents the oppositeextreme. Here, a large value compen-sation capacitor eliminates all ringingbut slows down the amplifier so muchthat settling stretches out to 3.3µs.The best case appears in Figure 10.This photo was taken with the com-pensation capacitor carefully chosenfor the best possible settling time.Damping is tightly controlled and set-tling time goes down to 1.7µs.

Settling Timesof Various AmplifiersThe previous results, using theLT1468 amplifier, provide extremelyfast settling times with high accuracyover temperature. Many applicationscan tolerate reduced speed, reducedtemperature stability or both. Set-tling times for a number of amplifiers,along with commentary, can be foundin LTC Application Note 74, Figure34. “Optimized” settling times wererecorded after individually trimmingthe feedback capacitors. The “con-servative” times represent theworst-case settling times using stan-dard-value compensation capacitorswith no trimming.

ConclusionThe sampling-based settling-time cir-cuit appears to be a very usefulmeasurement solution. Expanded dis-cussion and tutorial appear in thisarticle’s “root” publication: LTCApplication Note 74, Component andMeasurement Advances Ensure 16-Bit DAC Settling Time.

500ns/DIV

B = 500µV/DIV

A = 5V/DIV

Figure 10. Optimal feedback capacitance yields a tightlydamped signature and the best settling time (tSETTLE = 1.7µs).

Net1 and Net2 Serial Interface ChipSet Supports Test Mode by David Soo

Some serial networks use a test modeto exercise all of the circuits in theinterface. The network is divided intolocal and remote data terminalequipment (DTE) and data-circuit-terminating equipment (DCE), asshown in Figure 1. Once the networkis placed in a test mode, the local DTEwill transmit on the driver circuitsand expect to receive the same sig-nals back from either a local or remoteDCE. These tests are called local orremote loopback.

As introduced in the February 1998issue of Linear Technology, theLTC1543/LTC1544/LTC1344A chipset has taken the integrated approach

to multiple protocol. By using thischip set, the Net1 and Net2 designwork is done. The LTC1545 extendsthe family by offering test mode capa-bility. By replacing the 6-circuitLTC1544 with the 9-circuit LTC1545,the optional circuits TM (Test Mode),RL (Remote Loopback) and LL (LocalLoopback) can now be implemented.

Figure 2 shows a typical applica-tion using the LTC1543, LTC1545and LTC1344A. By just mapping thechip pins to the connector, the designof the interface port is complete. Thechip set supports the V.28, V.35, V.36,RS449, EIA-530, EIA-530A or X.21protocols in either DTE or DCE mode.

Shown here is a DCE mode connec-tion to a DB-25 connector. Themode-select pins, M0, M1 and M2,are used to select the interface proto-col, as summarized in Table 1.

LOCAL DTE

LOCAL DCE LL REMOTE

DCERL REMOTE

DTE

5451CTL/3451CTLemaNedoM 2M 1M 0M

desUtoN 0 0 0

A035-AIE 0 0 1

035-AIE 0 1 0

12.X 0 1 1

53.V 1 0 0

63.V/944SR 1 0 1

82.V/232SR 1 1 0

elbaCoN 1 1 1

Table 1. Mode pin functions

Figure 1. Serial network


DESIGN INFORMATION

10

17

18

D2

D1

LTC1545

D3

R2

R1

R3

VCC

VDD

VEE

GND

D4

1,192,20

3

4

5

6

7

8

9

R4EN

D4ENB15

16

24

23

22

25

26

27

28

29

30

31

32

33

34

35

36

M0

M1

M2

DCE/DTE

11

12

13

14

D521

R4

R5

D2

LTC1543

RXD

RXC

TXC

SCTE

TXD

CTS

DSR

DCD

DTR

RI

LL

RTS

RL

TM

M0

M1

M2

DCE/DTE

VCC

NCNC

3

16

17

9

15

12

24

11

2

1

5

13

6

8

22

10

20

23

4

19

7

14

1544 F24

D3

R2

R1

R3

D1

C2 1µF

C1 1µF

C5 1µF

C3 1µF

C4 3.3µF

16109764

3 8 11 12 13

5

2

15 18 17 19 20 22

LTC1344A

C6 100pF

C7 100pF

C8 100pF

VCC

VCC

VCC 5V

23 24

14

1

DCE/

DTE

M2

M1

M0

CHARGE PUMP

+

283

1

2

4

5

6

7

8

9

10

NC

11

1213

14

2726

25

24

23

22

21

20

19

18

17

16

15

VEE

M0 M1 M2

21LATCH

C12 1µF

C13 1µF

C11 1µF

C10 1µF

C9 1µF

RXD A (104)

RXD B

RXC A (115)

RXC B

SCTE A (113)

SCTE B

TXD A (103)

TXD B

TXC A (114)

TXC B

SGND (102)

SHIELD (101)

DB-25 FEMALE CONNECTOR

CTS A (106)

CTS B

DSR A (107)

DSR B

RTS A (105)

RTS B

DCD A (109)

DCD B

DTR A (108)

DTR B

18

21

25

LL (141)

RL (140)

TM (142)

RI (125)*

VDD

VCC

VEE

C1–

C1+

C2–

VEE

C2+

*OPTIONAL: FOR USE WITH DB-26 CONNECTOR

Figure 2. Typical application: Controller-selectable DCE port with DB-25 connector


Fortunately, there is always syn-chronization information associatedwith video. A simple circuit can beused to DC restore voltage offsetsproduced by resistor mismatch, opamp offset or DC errors in the inputvideo. Figure 2 shows the additional

–

+

5V

0V

VIDEO

HOLD

SAMPLE

CLAMP PULSE

B

A

5V12V

1/2 LTC201A

13

2, 15

4, 51, 16

3, 14

R1 10k

R2 10k

R3 10k

5V

R4 1.40k

R5 50k

R6 20k

C4 0.1µF

1/2 LT1632

C2 6800pF FILM

C3 0.1µF

12V

R7 10k

C1 10µF FILM

TO FIGURE 1, POINT

TO FIGURE 1, POINT

DC RESTORE LEVEL (ADJUST FOR DESIRED BLANKING LEVEL)

circuitry needed to perform this func-tion. The LTC201A analog switch andC1 store the offset error during blank-ing. The clamp pulse should be 3µs orwider and should occur during blank-ing. It can conveniently be made bydelaying the sync pulse with one shots.

If the sync tip is clamped, the clamppulse must start after and end beforethe sync pulse or offset errors will beintroduced. The integrator made withthe LT1632 adjusts the voltage atpoint B (see Figure 1) to correct theoffset.

Figure 2. DC restore subcircuit

configuration, the part performs oneconversion, then automatically entersthe power-down mode. The durationof the power-down mode is propor-tional to the capacitor value.

While CS is held high, the serialdata out pin is high impedance. OnceCS is pulled low, the part beginsoutputting data under the control ofthe SCLK pin.

This device can operate with eitheran internal or external serial clock. Ifthe SCLK pin is left floating, theLTC2400 automatically detects thisstate and switches to internal clockmode. If the user drives the SCLK pinwith his own clock, the part is auto-matically switched to external clockmode.

Many delta-sigma ADC’s on themarket include a PGA. These PGAsrequire that the designer deal withmore device pins, status registers andtiming sequences. Additionally, theylimit the circuit’s input range. Forexample, if the PGA’s gain is 256 andthe reference is 2.5V the resultinginput range is 0mV to 10mV.

VCC

VREF

VIN

GND

fO

SCLK

DOUT

CS

LTC2400

2.5V

–300mV TO 2.8V 3-WIRE SPI INTERFACE

60Hz REJECTION

2.7V–5.5V

1µF

The LTC2400 provides better noiseand TUE (total unadjusted error) per-formance than previous delta-sigmaADCs; moreover, the user is no longerconfined to a 10mV input range. Theinput can still range between –12.5%× VREF and 112.5% × VREF. The eightMSBs determine the coarse inputrange. For example, if the eight MSBs= 00h, the input (VIN) is in the range:0 < VIN < 10mV, whereas 01h corre-sponds to 10mV < VIN < 20mV, and soon. This enables the LTC2400 todirectly digitize a variety of low levelsensors with large offsets.

The LTC2400 package is the small-est on the market (SO-8). This tinychip combined with no external com-ponents enables the user to greatly

reduce the board area required byexisting designs.

ConclusionThe LTC2400 is the first of a family ofdelta-sigma converters from LTC. Itoffers a combination of the best char-acteristics of delta-sigma convertersand conventional converters. Itsattributes include latency-freeoperation and high precision INL, DNLand offset. It frees the user from addingexternal components and is easy touse. The on-chip sinc4 filter reducesline frequency noise and its harmon-ics by 120dB, making it ideal for usein noisy environments. With only eightpins, an on-chip oscillator, 24-bit DNL,4ppm INL and 10ppm TUE, theLTC2400 is the new state of the art inanalog-to-digital conversion.Notes:

1.Candy, J.C and G.C. Temes. “Oversampling Meth-ods for A/D and D/A Conversion,” in OversamplingDelta-Sigma Data Converters. IEEE Press, 1992.

2. Hauser, Max W. “Principles of Oversampling andA/D Conversion.” Journal of the Audio EngineeringSociety, Vol. 39, No. 1/2 (January/February 1991)pp. 3–26.

Figure 8. LTC2400 typical application

LTC2400, continued from page 4

Level Shift, continued from page 30

CONTINUATIONS


NEW DEVICE CAMEOS

New Device CameosLTC1436A/LTC1436A-PLL/LTC1437A: High Efficiency,PLL-Lockable SwitchingRegulatorsThe LTC1436A/LTC1436A-PLL/LTC1437A are high efficiency, lownoise, synchronous switching regu-lators that drive external N-channelpower MOSFETs in a phase-lockable,fixed frequency architecture and areideal for notebook computers andbattery-powered equipment requir-ing high frequency, low duty cycleoperation.

The LTC1436A/LTC1436A-PLL/LTC1437A have all of the outstandingfeatures of the LTC1436/LTC1436-PLL/LTC1437 with a reducedminimum on-time of 300ns or lessand improved noise immunity at lowoutput voltages. With these improve-ments, high performance can beachieved at output voltages down to1.3V with operating frequencies inexcess of 250kHz and input supplyvoltages above 22V.

As with the originals, the improvedparts feature the optional AdaptivePower™ output stage to provide goodlow current efficiency while main-taining constant frequency operationby selectively driving two topsideN-channel MOSFETs sized for theappropriate load range. An auxiliarylow dropout linear regulator is avail-able to generate an additional supplythat can be used as a CPU I/O supplyor low noise audio supply. A second-ary-winding-feedback/burst-disableinput guarantees regulation regard-less of the primary supply load byforcing continuous operation whenneeded.

Other features include a power-onreset timer that generates a logic-lowoutput signal persisting for 65,536clock cycles after the output is within7.5% of the regulated output voltage,low dropout operation (99% dutycycle), a low-battery comparator withopen-drain output and a wide supplyrange for operation from 3.5V to 36V.

The parts are available in 24-leadnarrow SSOP for the LTC1436A andLTC1436A-PLL and 28-lead SSOP forthe LTC1437A.

LTC1625 No RSENSEController Now Available inIndustrial Temperature GradeAn industrial temperature grade ver-sion of the LTC1625 No RSENSE™controller is now available for appli-cations that require the enhancedtemperature range (–40°C to 85°C).The LTC1625 provides true currentmode control in step-down DC/DCconverters without using a senseresistor. A current sense signal isobtained by monitoring the voltagedrop across the MOSFET switches,making them perform double duty ascurrent sense elements. Eliminatingthe sense resistor reduces board area,lowers costs and increases efficiency.Popular features fr om LinearTechnology’s other controllers havebeen incorporated, such as fixedfrequency operation, N-channel MOS-FET drive, Burst Mode™ operation,soft-start and output voltage program-ming. These features make theLTC1625 an excellent choice for DC/DC converter designs in a variety ofapplications that require the highestperformance.

LTC1694:SMBus AcceleratorThe LTC1694 is a dual active SMBuspull-up designed to enhance data-transmission speed and reliabilityunder all specified SMBus loadingconditions. It consists of two bilevel,hysteretic current source pull-upsthat replace the pull-up resistors in atypical SMBus implementation. Withthe LTC1694, the user can connectmultiple SMBus devices or use longer,more capacitive interconnects with-out compromising slew rates orpenalizing bus performance.

Resistive pull-ups are used in manycommunications protocols that em-ploy open-collector or open-drain

drivers. Their simplicity is offset bythe relatively slow rise times theyafford when bus capacitance is high.Rise times can be improved by usinglower pull-up resistance values, butthe additional current through thelow value resistors increases the lowstate bus voltage, decreasing noisemargins. Slow rise times can seri-ously affect data reliability, enforcinga maximum practical bus speed wellbelow the theoretical SMBus maxi-mum transmission rate.

The LTC1694 overcomes these limi-tations by using bilevel, hystereticcurrent sources as pull-ups. Duringpositive bus transitions, the currentsources provide 2.2mA to quickly slewany parasitic bus capacitance. Dur-ing negative transitions or steady DClevels, the current sources switch to275µA to improve negative slew rateand improve low state noise margins.The fast rise times coupled withimproved low state logic swings allowmaximum transmission speed for anygiven bus loading conditions.

The LTC1694 is available in the5-lead SOT-23 plastic surface mountpackage, requiring virtually the sameboard area as two surface mountresistors. The LTC1694 is specifiedfor operation over the 0°C to 70°Ctemperature range.

LTC1530: High PowerSynchronous SwitchingRegulator Controller withCurrent Limit in SO-8The LTC1530 is a high power, highefficiency switching regulatorcontroller optimized for 5V buck con-verter applications. A typical LTC1530circuit can provide output currents ofup to 20A. Packaged in an SO-8, theLTC1530 operates on a single supplyof up to 14V. It includes a precisioninternal reference and an internalfeedback system that can provideoutput voltage regulation of ±2% overtemperature, load-current and line-voltage shifts.

The LTC1530 employs a synchro-nous switching architecture thatdrives two external N-channel outputdevices. It also senses current throughthe drain-source resistance (or on-


NEW DEVICE CAMEOS

For further information on anyof the devices mentioned in thisissue of Linear Technology, usethe reader service card or callthe LTC literature servicenumber:

1-800-4-LINEAR

Ask for the pertinent data sheetsand Application Notes.

resistance) of the upper N-channelMOSFET, eliminating the need for anexternal, low value sense resistor.The current-limit trip point is set witha single external resistor; a tempera-ture compensation circuit keeps thecurrent-limit level constant as theexternal MOSFET RDS(ON) increaseswith temperature. The part alsoincludes an on-chip soft-start capaci-tor; the soft-start slew rate is 0.4V/ms. It also has a thermal protectioncircuit that disables both internalgate drivers and reduces the supplycurrent to 1mA when excessive dietemperatures occur. In shutdownmode, the LTC1530 supply currentdrops to 45µA.

LTC1753: ProgrammableSynchronous SwitchingRegulator ControllerThe LTC1753 is a high power, highefficiency, synchronous switchingregulator controller that generates adigitally programmable output volt-age between 1.3V and 3.5V. Step-downconversion is optimized for a 5V input.The internal 5-bit DAC accepts a par-allel word and programs the outputvoltage from 1.3V to 2.05V in 50mVincrements and from 2.1V to 3.5V in100mV increments. The precisioninternal reference and feedback sys-tem provide an output voltageaccuracy of ±1.5% at room tem-perature and ±2% (typical) overtemperature, load current and linevoltage shifts.

The LTC1753 uses a synchronousswitching architecture with twoexternal N-channel MOSFETs. It pro-vides more than 14A of load currentat efficiencies exceeding 90%. TheLTC1753 senses output currentthrough the on-resistance of the upper

N-channel FET and provides adjust-able current limit without the use ofan external sense resistor. ExternalMOSFET power dissipation is con-siderably reduced under outputshort-circuit conditions by an over-current protection scheme built intothe LTC1753.

The free-running 300kHz oscilla-tor frequency can be synchronized toa faster clock if desired. Soft-starteases inrush current and recoveryfrom overload conditions. Protectionfeatures include overvoltage faultdetection, overtemperature detectionand a power-good signal when theoutput voltage is within ± 5%regulation.

The LTC1753 is ideal for highpower, tight tolerance microproces-sors applications. It is available in20-pin SO and SSOP packages.

The LTC1597/LTC1591:Ultra-accurate, Low Power16- and 14-Bit MultiplyingCurrent Output DACsInclude On-Chip ResistorsExpanding LTC’s family of currentoutput, multiplying DACs are the pin-compatible 16-bit LTC1597 and 14-bitLTC1591. The LTC1597 features true16-bit performance (DNL and INL,1LSB maximum), low glitch impulse(2nV-s typical) and low supply powerdissipation (10µ W typical). TheLTC1591 offers the same level ofperformance at 14-bit resolution. TheLTC1597/LTC1591 can be configuredfor unipolar, 2-quadrant multiplyingor for bipolar, 4-quadrant multiply-ing applications with no externalresistors. For a fixed 10V referenceinput, the DAC unipolar output rangeis 0V to –10V and the DAC bipolaroutput range is ±10V. The LTC1597,coupled with LT1468 op amp, settlesto within 0.0015% of full scale in 2µs.The LTC1597/LTC1591 have an asyn-chronous clear input that resets theoutput to zero scale. A second pair ofparts, the LTC1597-1/LTC1591-1,resets to a midscale output. Thesedevices also have a power-on reset.The LTC1597 and LTC1591 feature16- and 14-bit parallel input databusses, respectively.

The LTC1597 and LTC1591 aredesigned for applications such asprocess control and industrial auto-mation, direct digital waveformgeneration, software-controlled gainadjustment and automatic test equip-ment. Available in 28-pin SSOP orDIP packages, the LTC1597/LTC1591operate on single 5V supplies.

LTC1258-2.5 MicropowerLow Dropout ReferenceThe LTC1258-2.5 is a micropowerbandgap reference that combines highaccuracy and low drift with very lowsupply current and small packagesize. The combination of only 4µAquiescent current and low, 200mVMax dropout makes it ideal for bat-tery-powered equipment.

This reference uses curvaturecompensation to obtain a lowtemperature coefficient and trimmedthin-film resistors to achieve highoutput accuracy. The reference cansupply up to 10mA and sink up to2mA, making it ideal for precisionregulator applications. The LTC1258-2.5 is stable without an output bypasscapacitor, but is also stable withcapacitance up to 1µF. This feature isimportant in critical applicationswhere PC board space is at a premiumand fast settling is demanded.

This series reference provides sup-ply current and power dissipationadvantages over shunt references thatmust idle the entire load current tooperate.

The LTC1258-2.5 is available in 8-pin SO and MSOP packages.



www.linear-tech.com


DESIGN TOOLS

Applications on DiskFilterCAD™ 2.0 CD-ROM — This CD is a powerful filterdesign tool that supports all of Linear Technology’s highperformance switched capacitor filters. Included is Fil-terView™, a document navigator that allows you toquickly find Linear Technology monolithic filter datasheets, the FilterCAD manual, application notes, designnotes and Linear Technology magazine articles. It doesnot have to be installed to run FilterCAD. It is notnecessary to use FilterView to view the documents, asthey are standard .PDF files, readable with any versionof Adobe Acrobat™. FilterCAD runs on Windows® 3.1 orWindows 95. FilterView requires Windows 95. TheFilterCAD program itself is also available on the web andwill be included on the new LinearView™ CD.

Available at no charge.

Noise Disk — This IBM-PC (or compatible) programallows the user to calculate circuit noise using LTC opamps, determine the best LTC op amp for a low noiseapplication, display the noise data for LTC op amps,calculate resistor noise and calculate noise using specsfor any op amp. Available at no charge

SPICE Macromodel Disk — This IBM-PC (or compat-ible) high density diskette contains the library of LTC opamp SPICE macromodels. The models can be used withany version of SPICE for general analog circuit simula-tions. The diskette also contains working circuit examplesusing the models and a demonstration copy of PSPICE™by MicroSim. Available at no charge

SwitcherCAD™ — The SwitcherCAD program is a pow-erful PC software tool that aids in the design andoptimization of switching regulators. The program cancut days off the design cycle by selecting topologies,calculating operating points and specifying componentvalues and manufacturer’s part numbers. 144 pagemanual included. $20.00

SwitcherCAD supports the following parts: LT1070 se-ries: LT1070, LT1071, LT1072, LT1074 and LT1076.LT1082. LT1170 series: LT1170, LT1171, LT1172 andLT1176. It also supports: LT1268, LT1269 and LT1507.LT1270 series: LT1270 and LT1271. LT1371 series:LT1371, LT1372, LT1373, LT1375, LT1376 and LT1377.

Micropower SwitcherCAD™ — The MicropowerSCADprogram is a powerful tool for designing DC/DC convert-ers based on Linear Technology’s micropower switchingregulator ICs. Given basic design parameters,MicropowerSCAD selects a circuit topology and offersyou a selection of appropriate Linear Technology switch-ing regulator ICs. MicropowerSCAD also performs circuitsimulations to select the other components which sur-round the DC/DC converter. In the case of a batterysupply, MicropowerSCAD can perform a battery lifesimulation. 44 page manual included. $20.00

MicropowerSCAD supports the following LTC micro-power DC/DC converters: LT1073, LT1107, LT1108,LT1109, LT1109A, LT1110, LT1111, LT1173, LTC1174,LT1300, LT1301 and LT1303.

Technical Books1990 Linear Databook, Vol I —This 1440 page collec-tion of data sheets covers op amps, voltage regulators,references, comparators, filters, PWMs, data conver-sion and interface products (bipolar and CMOS), in bothcommercial and military grades. The catalog featureswell over 300 devices. $10.00

1992 Linear Databook, Vol II — This 1248 page supple-ment to the 1990 Linear Databook is a collection of allproducts introduced in 1991 and 1992. The catalogcontains full data sheets for over 140 devices. The 1992Linear Databook, Vol II is a companion to the 1990Linear Databook, which should not be discarded.

$10.00

1994 Linear Databook, Vol III —This 1826 page supple-ment to the 1990 and 1992 Linear Databooks is acollection of all products introduced since 1992. A totalof 152 product data sheets are included with updatedselection guides. The 1994 Linear Databook Vol III is acompanion to the 1990 and 1992 Linear Databooks,which should not be discarded. $10.00

1995 Linear Databook, Vol IV —This 1152 page supple-ment to the 1990, 1992 and 1994 Linear Databooks is acollection of all products introduced since 1994. A totalof 80 product data sheets are included with updatedselection guides. The 1995 Linear Databook Vol IV is acompanion to the 1990, 1992 and 1994 Linear Databooks,which should not be discarded. $10.00

1996 Linear Databook, Vol V —This 1152 page supple-ment to the 1990, 1992, 1994 and 1995 Linear Databooksis a collection of all products introduced since 1995. Atotal of 65 product data sheets are included with updatedselection guides. The 1996 Linear Databook Vol V is acompanion to the 1990, 1992, 1994 and 1995 LinearDatabooks, which should not be discarded. $10.00

1997 Linear Databook, Vol VI —This 1360 page supple-ment to the 1990, 1992, 1994, 1995 and 1996 LinearDatabooks is a collection of all products introducedsince 1996. A total of 79 product data sheets are in-cluded with updated selection guides. The 1997 LinearDatabook Vol VI is a companion to the 1990, 1992, 1994,1995 and 1996 Linear Databooks, which should not bediscarded. $10.00

1990 Linear Applications Handbook, Volume I —928 pages full of application ideas covered in depth by40 Application Notes and 33 Design Notes. This catalogcovers a broad range of “real world” linear circuitry. Inaddition to detailed, systems-oriented circuits, this hand-book contains broad tutorial content together with liberaluse of schematics and scope photography. A specialfeature in this edition includes a 22-page section onSPICE macromodels. $20.00

1993 Linear Applications Handbook, Volume II —Continues the stream of “real world” linear circuitryinitiated by the 1990 Handbook. Similar in scope to the1990 edition, the new book covers Application Notes 40through 54 and Design Notes 33 through 69. Referencesand articles from non-LTC publications that we havefound useful are also included. $20.00

1997 Linear Applications Handbook, Volume III —This 976 page handbook maintains the practical outlookand tutorial nature of previous efforts, while broadeningtopic selection. This new book includes Application

Notes 55 through 69 and Design Notes 70 through 144.Subjects include switching regulators, measurementand control circuits, filters, video designs, interface,data converters, power products, battery chargers andCCFL inverters. An extensive subject index referencescircuits in LTC data sheets, design notes, applicationnotes and Linear Technology magazines. $20.00

1998 Data Converter Handbook — This impressive1360 page handbook includes all of the data sheets,application notes and design notes for LinearTechnology’s family of high performance data converterproducts. Products include A/D converters (ADCs), D/Aconverters (DACs) and multiplexers—including the fast-est monolithic 16-bit ADC, the 3Msps, 12-bit ADC withthe best dynamic performance and the first dual 12-bitDAC in an SO-8 package. Also included are selectionguides for references, op amps and filters and a glossaryof data converter terms. $10.00

Interface Product Handbook — This 424 page hand-book features LTC’s complete line of line driver andreceiver products for RS232, RS485, RS423, RS422,V.35 and AppleTalk® applications. Linear’s particularexpertise in this area involves low power consumption,high numbers of drivers and receivers in one package,mixed RS232 and RS485 devices, 10kV ESD protectionof RS232 devices and surface mount packages.

Available at no charge

Power Solutions Brochure — This collection of cir-cuits contains real-life solutions for common powersupply design problems. There are over 88 circuits,including descriptions, graphs and performancespecifications. Topics covered include battery chargers,PCMCIA power management, microprocessor powersupplies, portable equipment power supplies, micro-power DC/DC, step-up and step-down switchingregulators, off-line switching regulators, linear regula-tors and switched capacitor conversion.


Data Conversion Solutions Brochure — This 64 pagecollection of data conversion circuits, products andselection guides serves as excellent reference for thedata acquisition system designer. Over 60 products areshowcased, solving problems in low power, small sizeand high performance data conversion applications—with performance graphs and specifications. Topicscovered include ADCs, DACs, voltage references andanalog multiplexers. A complete glossary defines dataconversion specifications; a list of selected applicationand design notes is also included.


Telecommunications Solutions Brochure — This col-lection of circuits, new products and selection guidescovers a wide variety of products targeted for thetelecommunications industry. Circuits solving real lifeproblems are shown for central office switching, cellularphone, base station and other telecom applications.New products introduced include high speed amplifiers,A/D converters, power products, interface transceiversand filters. Reference material includes a telecommuni-cations glossary, serial interface standards, protocolinformation and a complete list of key application notesand design notes. Available at no charge

DESIGN TOOLS

Information furnished by Linear Technology Corporationis believed to be accurate and reliable. However, LinearTechnology makes no representation that the circuitsdescribed herein will not infringe on existing patent rights. continued on page 40

Linear Technology Magazine • November 1998© 1998 Linear Technology Corporation/Printed in U.S.A./

LINEAR TECHNOLOGY CORPORATION1630 McCarthy BoulevardMilpitas, CA 95035-7417(408) 432-1900 FAX (408) 434-0507www.linear-tech.comFor Literature Only: 1-800-4-LINEAR

Acrobat is a trademark of Adobe Systems, Inc.; Windowsis a registered trademark of Microsoft Corp.; Macintoshand AppleTalk are registered trademarks of Apple Com-puter, Inc. PSPICE is a trademark of MicroSim Corp.

CD-ROM CatalogLinearView — LinearView™ CD-ROM version 3.0 isLinear Technology’s latest interactive CD-ROM. It al-lows you to instantly access thousands of pages ofproduct and applications information, covering LinearTechnology’s complete line of high performance analogproducts, with easy-to-use search tools.

The LinearView CD-ROM includes the complete productspecifications from Linear Technology’s Databook li-brary (Volumes I–VI) and the complete ApplicationsHandbook collection (Volumes I–III). Our extensivecollection of Design Notes and the complete collectionof Linear Technology magazine are also included.

A powerful search engine built into the LinearView CD-ROM enables you to select parts by various criteria,such as device parameters, keywords or part numbers.All product categories are represented: data conversion,references, amplifiers, power products, filters and inter-face circuits. Up-to-date versions of Linear Technology’s

DESIGN TOOLS, continued from page 39 software design tools, SwitcherCAD, Micropower Switch-erCAD, FilterCAD, Noise Disk and Spice Macromodellibrary, are also included. Everything you need to knowabout Linear Technology’s products and applications isreadily accessible via LinearView. LinearView runs un-der Windows 3.1, Windows 95 and Macintosh® System8.0 or later. Available at no charge.

World Wide Web SiteLinear Technology Corporation’s customers can nowquickly and conveniently find and retrieve the latesttechnical information covering the Company’s productson LTC’s internet web site. Located at www.linear-tech.com, this site allows anyone with internet accessand a web browser to search through all of LTC’stechnical publications, including data sheets, applica-tion notes, design notes, Linear Technology magazineissues and other LTC publications, to find informationon LTC parts and applications circuits. Other areaswithin the site include help, news and information aboutLinear Technology and its sales offices.

Other web sites usually require the visitor to downloadlarge document files to see if they contain the desiredinformation. This is cumbersome and inconvenient. Tosave you time and ensure that you receive the correctinformation the first time, the first page of each datasheet, application note and Linear Technology maga-zine is recreated in a fast, download-friendly format.This allows you to determine whether the document iswhat you need, before downloading the entire file.

The site is searchable by criteria such as part numbers,functions, topics and applications. The search is per-formed on a user-defined combination of data sheets,application notes, design notes and Linear Technologymagazine articles. Any data sheet, application note,design note or magazine article can be downloaded orfaxed back. (files are downloaded in Adobe Acrobat PDFformat; you will need a copy of Acrobat Reader to viewor print them. The site includes a link from which youcan download this program.)

InternationalSales OfficesFRANCELinear Technology S.A.R.L.Immeuble “Le Quartz”58 Chemin de la Justice92290 Chatenay MalabryFrancePhone: 33-1-41079555FAX: 33-1-46314613

GERMANYLinear Technology GmbHOskar-Messter-Str. 24D-85737 IsmaningGermanyPhone: 49-89-962455-0FAX: 49-89-963147

JAPANLinear Technology KK5F NAO Bldg.1-14 Shin-Ogawa-cho Shinjuku-kuTokyo, 162JapanPhone: 81-3-3267-7891FAX: 81-3-3267-8510

KOREALinear Technology Korea Co., LtdNamsong Building, #403Itaewon-Dong 260-199Yongsan-Ku, Seoul 140-200KoreaPhone: 82-2-792-1617FAX: 82-2-792-1619

SINGAPORELinear Technology Pte. Ltd.507 Yishun Industrial Park ASingapore 768734Phone: 65-753-2692FAX: 65-754-4113

SWEDENLinear Technology ABSollentunavägen 63S-191 40 SollentunaSwedenPhone: (08)-623-1600FAX: (08)-623-1650

TAIWANLinear Technology CorporationRm. 602, No. 46, Sec. 2Chung Shan N. Rd.Taipei, Taiwan, R.O.C.Phone: 886-2-521-7575FAX: 886-2-562-2285

UNITED KINGDOMLinear Technology (UK) Ltd.The Coliseum, Riverside WayCamberley, Surrey GU15 3YLUnited KingdomPhone: 44-1276-677676FAX: 44-1276-64851

World HeadquartersLinear Technology Corporation1630 McCarthy BoulevardMilpitas, CA 95035-7417Phone: (408) 432-1900FAX: (408) 434-0507

U.S. AreaSales OfficesNORTHEAST REGIONLinear Technology Corporation3220 Tillman Drive, Suite 120Bensalem, PA 19020Phone: (215) 638-9667FAX: (215) 638-9764

Linear Technology Corporation266 Lowell St., Suite B-8Wilmington, MA 01887Phone: (978) 658-3881FAX: (978) 658-2701

NORTHWEST REGIONLinear Technology Corporation720 Sycamore DriveMilpitas, CA 95035Phone: (408) 428-2050FAX: (408) 432-6331

SOUTHEAST REGIONLinear Technology Corporation17000 Dallas Parkway, Suite 219Dallas, TX 75248Phone: (972) 733-3071FAX: (972) 380-5138

Linear Technology Corporation9430 Research Blvd.Echelon IV Suite 400Austin, TX 78759Phone: (512) 343-3679FAX: (512) 343-3680

Linear Technology Corporation1080 W. Sam Houston Pkwy., Suite 225Houston, TX 77043Phone: (713) 463-5001FAX: (713) 463-5009

Linear Technology Corporation5510 Six Forks Road, Suite 102Raleigh, NC 27609Phone: (919) 870-5106FAX: (919) 870-8831

CENTRAL REGIONLinear Technology Corporation2010 E. Algonquin Road, Suite 209Schaumburg, IL 60173Phone: (847) 925-0860FAX: (847) 925-0878

Linear Technology CorporationKenosha, WI 53144Phone: (414) 859-1900FAX: (414) 859-1974

SOUTHWEST REGIONLinear Technology Corporation21243 Ventura Blvd., Suite 208Woodland Hills, CA 91364Phone: (818) 703-0835FAX: (818) 703-0517

Linear Technology Corporation15375 Barranca Parkway, Suite A-213Irvine, CA 92618Phone: (949) 453-4650FAX: (949) 453-4765

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