List of Publications

Vishwani D. Agrawal

December 25, 2019

[1] V. K. Jain and V. D. Agrawal, “Directional loudspeaker system for a bighall,” J.I.T.E. (India), vol. 12, pp. 29–35, Jan. 1966.

[2] S. K. Chatterjee, V. D. Agrawal, and R. Chatterjee, “Reactance modu-lated dielectric rod waveguide,” J.I.E. (India), vol. 43, Part ET2, pp. 103–114, 1968.

[3] Y. T. Lo and V. D. Agrawal, “Removal of blindness in phased arrays,”Proc. IEEE, vol. 56, pp. 1586–1588, Sept. 1968.

[4] V. D. Agrawal and Y. T. Lo, “Distribution of sidelobe level in randomarrays,” Proc. IEEE, vol. 57, pp. 1764–1765, Oct. 1969.

[5] Y. T. Lo, V. D. Agrawal, and A. R. Panicali, “A review of the theoryof random arrays with some recent results,” in Proc. 4th Colloquium onMicrowave Communication, (Budapest, Hungary), Apr. 1970.

[6] V. D. Agrawal and D. R. Barkhurst, “Vertically polarized dipole evalua-tion – Final report,” Tech. Rep. AL-685, EG&G, Inc., Albuquerque, NewMexico, March 1, 1972.

[7] V. D. Agrawal and Y. T. Lo, “Mutual coupling in phased arrays ofrandomly spaced antennas,” IEEE Trans. Antennas and Propagation,vol. AP-20, pp. 288–295, May 1972. Also Antenna Lab. Report No. 71-1,University of Illinois, Urbana, Illinois.

[8] V. D. Agrawal and Y. T. Lo, “Anomalies of dielectric coated gratings,”Applied Optics, vol. 11, pp. 1946–1951, Sept. 1972.

[9] V. D. Agrawal and P. Agrawal, “An automatic test generation system forIlliac IV logic boards,” IEEE Trans. Comput., vol. C-21, pp. 1015–1017,Sept. 1972.

[10] V. D. Agrawal, “A novel technique of electronic scanning,” in Proc. Sym-posium on Sonar Systems and Ultrasonics, Indian Institute of Technology,New Delhi, May 3-5, 1973.

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[11] V. D. Agrawal and R. K. Arora, “Scanning transients in phased arrayantennas,” Proc. IEEE, vol. 62, pp. 850–851, June 1974.

[12] R. K. Arora and V. D. Agrawal, “Frequency-spread associated with fastelectronic scanning,” Proc. IEEE, vol. 62, pp. 1175–1176, Aug. 1974.

[13] V. D. Agrawal, “Comments on beamwidth of phased arrays,” IEEE Trans.Ant. Prop., vol. AP-22, pp. 841–842, Nov. 1974.

[14] D. T. Shahani and V. D. Agrawal, “An experimental phased array an-tenna,” Tech. Rep. SRS-75-1, School of Radar Studies, Indian Institute ofTechnology, New Delhi, Jan. 1975.

[15] P. Agrawal and V. D. Agrawal, “On improving the efficiency of montecarlo test generation,” in Digest of Fifth Int. Fault Tolerant ComputingSymposium, (Paris, France), pp. 205–209, June 18-20, 1975.

[16] P. Agrawal and V. D. Agrawal, “Probabilistic analysis of random testgeneration method for irredundant combinational networks,” IEEE Trans.Comput., vol. C-24, pp. 691–695, July 1975.

[17] P. Agrawal and V. D. Agrawal, “On monte carlo testing of logic treenetworks,” IEEE Trans. Comput., vol. C-25, pp. 664–667, June 1976.

[18] V. D. Agrawal and W. A. Imbriale, “Dichroic subreflector,” Tech. Rep.76-7323.A4-72, TRW Defense and Space Systems Group, Redondo Beach,California, Sept. 1976.

[19] V. D. Agrawal and W. A. Imbriale, “Experimental and theoretical designof dichroic surface for a spacecraft antenna,” in Proc. IEEE Int. AP-SSymp., (Amherst, MA), pp. 105–108, Oct. 1976.

[20] V. D. Agrawal and W. A. Imbriale, “Analysis of frequency selective sur-faces printed on dielectric sheet,” in Proc. IEEE Int. AP-S Symp., (PaloAlto, CA), June 1977.

[21] V. D. Agrawal and G. G. Wong, “Helix antenna for multiple access arrayof TDRSS spacecraft,” Tech. Rep. TDRSS-77-331-107, TRW Defense andSpace Systems Group, Redondo Beach, California, Dec. 1977.

[22] V. D. Agrawal, “Grating lobe suppression in phased arrays by subarrayrotation,” Proc. IEEE, vol. 66, pp. 347–349, Mar. 1978.

[23] V. D. Agrawal and T. C. Tong, “Grating lobe suppression in multipleaccess array of TDRSS spacecraft,” in IEEE Int. AP-S Symp. Digest,(Washington, D.C.), pp. 178–181, May 1978.

[24] V. D. Agrawal, “Selection of element for a scanned array antenna,” Archivfur Elektronik und Ubertragungstechnik (AEU), vol. 32, pp. 493–495, Nov.1978.

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[25] V. D. Agrawal, “When to use random testing,” IEEE Trans. Comput.,vol. C-27, pp. 1054–1055, Nov. 1978.

[26] V. D. Agrawal, “Electrostatic analog for finding nonintersecting paths,”IETE Student’s Journal (India), vol. 20, pp. 3–7, Jan. 1979.

[27] V. D. Agrawal and G. G. Wong, “A high performance helical element formultiple access array on TDRSS spacecraft,” in IEEE Int. AP-S Symp.Digest, (Seattle, Washington), pp. 481–484, June 1979.

[28] V. D. Agrawal and W. A. Imbriale, “Design of a dichroic cassegrain sub-reflector,” IEEE Trans. Ant. Prop., vol. AP-27, pp. 466–473, July 1979.

[29] V. D. Agrawal, “Authors reply to comments on when to use random test-ing,” IEEE Trans. Comput., vol. C-28, p. 581, Aug. 1979.

[30] V. D. Agrawal, “Comments on an approach to highly integrated, computermaintained cellular arrays,” IEEE Trans. Comput., vol. C-28, pp. 691–693,Sept. 1979.

[31] V. D. Agrawal, A. K. Bose, P. Kozak, H. N. Nham, and E. Pacas-Skewes,“A mixed-mode simulator,” in Proc. 17th Des. Auto. Conf., (Minneapolis,Minnesota), pp. 618–625, June 23-25, 1980.

[32] V. D. Agrawal, “Information theory in digital testing – A new approachto functional test pattern generation,” in Proc. Int. Conf. Cir. Comput.,(Port Chester, N.Y.), pp. 928–931, October 1-3, 1980.

[33] V. D. Agrawal, “Random test generation – A tutorial,” in Proc. Bell Syst.Conf. on Electronic Testing, (Princeton, N.J.), pp. 9–11, October 14-16,1980.

[34] V. D. Agrawal and Y. T. Lo, “Comments on characterization of the ran-dom array peak sidelobes,” IEEE Trans. Ant. Prop., vol. AP-28, pp. 946–948, Nov. 1980.

[35] V. D. Agrawal, S. C. Seth, and P. Agrawal, “LSI product quality and faultcoverage,” in Proc. 18th Des. Auto. Conf., (Nashville, TN), pp. 196–203,June 29-July 1, 1981.

[36] V. D. Agrawal, “An information theoretic approach to digital testing,”IEEE Trans. Comput., vol. C-30, pp. 582–587, Aug. 1981.

[37] M. R. Mercer, V. D. Agrawal, and C. M. Roman, “An LSI chip designedfor testability,” in Proc. Bell System Conference on Electronic Testing,(Princeton, N.J.), Sept. 1981.

[38] V. D. Agrawal, “Sampling techniques for determining fault coverage inLSI circuits,” J. Digital Syst., vol. V, pp. 189–202, Fall 1981.

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[39] V. D. Agrawal, “Emerging roles of VLSI testing,” in Proc. SEMI-CON/Southwest, (Dallas, Texas), October 13-14, 1981.

[40] M. R. Mercer, V. D. Agrawal, and C. M. Roman, “Test generation forhighly sequential scan-testable circuits through logic transformation,,” inProc. International Test Conference, (Philadelphia, PA), pp. 561–565, Oc-tober 27-29, 1981.

[41] S. C. Seth and V. D. Agrawal, “Forecasting reject rate of tested LSI chips,”IEEE Electron Device Letters, vol. EDL-2, pp. 286–287, Nov. 1981.

[42] V. D. Agrawal, A. K. Bose, P. Kozak, H. N. Nham, and E. Pacas-Skewes,“Mixed-mode simulation in the MOTIS system,” J. Digital Syst., vol. V,pp. 383–400, Winter 1981.

[43] V. D. Agrawal, S. C. Seth, and P. Agrawal, “Fault coverage requirementsin production testing of LSI circuits,” IEEE J. Sol. St. Circ., vol. SC-17,pp. 57–61, Feb. 1982.

[44] M. R. Mercer and V. D. Agrawal, “Testability strategies for custom poly-cell designs,” in Computer Elements Workshop, (New York, N.Y.), May21-22 1982.

[45] V. D. Agrawal, “Synchronous path analysis in MOS circuit simulator,”in Proc. 19th Des. Auto. Conf., (Las Vegas, Nevada), pp. 629–635, June14-16, 1982.

[46] S. C. Seth and V. D. Agrawal, “Statistical design verification,” 12th Int.Fault Tolerant Computing Symp., June 22-24, 1982. Digest of Papers pp.393-399.

[47] M. R. Mercer and V. D. Agrawal, “Applications of testability measuresin VLSI design,” in Proc. Bell System Conference on Electronic Testing,(Princeton, N.J.), pp. 52–58, October 5-7 1982.

[48] V. D. Agrawal and M. R. Mercer, “Testability measures – What do theytell us?,” Proc. Int. Test Conf., pp. 391–396, November 16-18, 1982.

[49] S. K. Jain and V. D. Agrawal, “Statistical fault analysis – A techniquefor estimating fault coverage through good circuit simulation,” in IEEEDesign for Testability Workshop, (Vail, CO), April 12-14 1983.

[50] S. K. Jain and V. D. Agrawal, “Test generation for MOS circuits usingD-algorithm,” in Proc. 20th Des. Auto. Conf., (Miami Beach, Florida),pp. 64–70, June 1983.

[51] V. D. Agrawal, S. K. Jain, and D. M. Singer, “Design for testability –Tutorial,” in Proc. Bell Syst. Conf. on Electronic Testing, (Princeton,N.J.), Oct. 1983.

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[52] S. C. Seth and V. D. Agrawal, “Characterizing the LSI yield equationfrom chip test data,” in Proc. Int. Conf. Circ. Comp., (New York, N.Y.),pp. 556–559, Sept. 28-Oct. 1, 1982. Also IEEE Trans. CAD Vol. CAD-3,pp. 123-126, April 1984.

[53] M. R. Mercer and V. D. Agrawal, “A novel clocking technique for VLSIcircuit testability,” IEEE J. Sol. St. Circ., vol. SC-19, pp. 207–212, Apr.1984.

[54] S. K. Jain, M. Weisel, and V. D. Agrawal, “Scan overhead optimizationin standard cell design,” in IEEE Design for Testability Workshop, (Vail,CO), April 24-26 1984.

[55] V. D. Agrawal, S. K. Jain, and D. M. Singer, “Automation in designfor testability,” in Custom Integrated Circuits Conf., (Rochester, N.Y.),pp. 159–163, May 21-23, 1984.

[56] S. M. Reddy, M. K. Reddy, and V. D. Agrawal, “Robust tests for stuck-open faults in CMOS combinational logic circuits,” in Proc. 14th Int. FaultTolerant Comp. Symp., (Kissimmee, Florida), pp. 44–49, June 20-22, 1984.

[57] S. K. Jain and V. D. Agrawal, “STAFAN: An alternative to fault simula-tion,” in Proc. ACM IEEE 21st Des. Auto. Conf., (Albuquerque, N.M.),pp. 18–23, June 25-27, 1984.

[58] A. E. Dunlop, V. D. Agrawal, D. N. Deutsch, M. F. Jukl, P. Kozak, andM. Wiesel, “Chip layout optimization using critical path weighting,” inProc. ACM IEEE 21st Des. Auto. Conf., (Albuquerque, N.M.), pp. 133–136, June 25-27, 1984.

[59] S. M. Reddy, V. D. Agrawal, and S. K. Jain, “A gate level model for CMOScombinational logic circuits with application to fault detection,” in Proc.ACM IEEE 21st Des. Auto. Conf., (Albuquerque, N.M.), pp. 504–509,June 25-27, 1984.

[60] V. D. Agrawal, S. K. Jain, and D. M. Singer, “A CAD system for designfor testability,” VLSI Design, vol. V, pp. 46–54, Oct. 1984.

[61] V. D. Agrawal, “Will testability analysis replace fault simulation - A paneldiscussion,” in Proc. Int. Test Conf., (Philadelphia, PA), Oct. 1984.

[62] V. D. Agrawal, “Computer-aids in VLSI design,” in Proc. IEEE Int. Conf.on Computers, Systems and Signal Processing, (Bangalore, India), Decem-ber 10-12, 1984.

[63] S. K. Jain and V. D. Agrawal, “Statistical fault analysis,” IEEE Design& Test of Computers, vol. 2, pp. 38–44, Feb. 1985.

[64] V. D. Agrawal and S. H. C. Poon, “VLSI design process,” in Proc.ACM Computer Science Conference, (New Orleans, Louisiana), pp. 74–78,March 12-14, 1985.

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[65] S. C. Seth and V. D. Agrawal, “Cutting chip testing costs,” IEEE Spec-trum, vol. 22, pp. 38–45, Apr. 1985.

[66] S. K. Jain and V. D. Agrawal, “Modeling and test generation algorithmsfor MOS circuits,” IEEE Trans. Comput., vol. C-34, pp. 426–433, May1985.

[67] V. D. Agrawal, S. C. Seth, and C. C. Chuang, “Probabilistically guidedtest generation,” in Proc. Int. Symp. on Circuits and Systems, (Kyoto,Japan), pp. 687–690, June 1985.

[68] S. C. Seth, L. Pan, and V. D. Agrawal, “PREDICT - probabilistic esti-mation of digital circuit testability,” in Proc. Fault Tolerant ComputingSymposium, (Ann Arbor, Michigan), pp. 220–225, June 19-21, 1985.

[69] P. Agrawal, V. D. Agrawal, and N. N. Biswas, “Multiple output minimiza-tion,” in Proc. 22nd Design Automation Conference, (Las Vegas, Nevada),pp. 674–680, June 24-26, 1985.

[70] S. K. Jain and V. D. Agrawal, “Clarifying statistical fault analysis – Au-thors’ reply,” IEEE Design & Test of Computers, vol. 2, pp. 7–8, Aug.1985.

[71] V. D. Agrawal and S. C. Seth, “Probabilistic testability,” in Proc. Int.Conf. on Computer Design, (Port Chester, NY), pp. 562–565, Oct. 1985.

[72] V. D. Agrawal, “Stafan takes a middle course (position statement),” inProc. International Test Conference, (Philadelphia, PA), Nov. 1985.

[73] S. C. Seth and V. D. Agrawal, “A review of testing of VLSI devices,”IETE Tech. Review, vol. 1, pp. 363–374, Nov. 1985.

[74] V. D. Agrawal, “VLSI testing,” in Proc. First International Workshop onVLSI Design, (Madras, India), December 18-26 1985.

[75] S. C. Seth, B. B. Bhattacharya, and V. D. Agrawal, “An exact analysis forefficient computation of random-pattern testability in combinational cir-cuits,” in Proc. Fault Tolerant Computing Symposium, (Vienna, Austria),pp. 318–323, July 1-3, 1986.

[76] T. Lin and V. D. Agrawal, “A test generator for scan-design VLSI cir-cuits,” in Proc. AT&T Conference on Electronic Testing, (Jamesburg,NJ), pp. 23.1–23.7, Sept. 1986.

[77] V. D. Agrawal and D. D. Johnson, “Logic modeling of PLA faults,” inProc. Int. Conf. on Computer Design, (Port Chester, NY), pp. 86–88, Oct.1986.

[78] N. C. E. Srinivas and V. D. Agrawal, “PROVE: Prolog based verifier,” inProc. Int. Conf. on Computer-Aided Design, (Santa Clara, CA), pp. 306–309, Nov. 1986.

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[79] V. D. Agrawal, K. T. Cheng, D. D. Johnson, and T. Lin, “A complete so-lution to the partial scan problem,” in Proc. Int. Test Conference, (Wash-ington, D.C.), pp. 44–51, Sept. 1987.

[80] V. D. Agrawal and K. T. Cheng, “A simulation-based directed searchmethod for test generation,” in Proc. Int. Conf. on Computer Design(ICCD), (Port Chester, NY), pp. 48–51, Oct. 1987.

[81] V. D. Agrawal, K. T. Cheng, and P. Agrawal, “Use of a concurrent faultsimulator for test vector generation,” in Proc. AT&T Conf. on ElectronicTesting, (Princeton, NJ), pp. 23–28, Oct. 1987.

[82] N. C. E. Srinivas and V. D. Agrawal, “Formal verification of digital circuitsusing hybrid simulation,” Circuits and Devices, vol. 4, pp. 19–27, Jan.1988.

[83] V. D. Agrawal, K. T. Cheng, D. D. Johnson, and T. Lin, “Designingcircuits with partial scan,” IEEE Design & Test of Computers, vol. 5,pp. 8–15, Apr. 1988.

[84] V. D. Agrawal, “Statistical testing,” in Testing and Diagnosis of VLSIand ULSI (F. Lombardi and M. Sami, eds.), pp. 33–47, Dordrecht, TheNetherlands: Kluwer Academic Publishers, 1988.

[85] V. D. Agrawal and K. T. Cheng, “Threshold-value simulation and testgeneration,” in Testing and Diagnosis of VLSI and ULSI (F. Lombardiand M. Sami, eds.), pp. 311–323, Dordrecht, The Netherlands: KluwerAcademic Publishers, 1988.

[86] V. D. Agrawal, K. T. Cheng, and P. Agrawal, “CONTEST: A concurrenttest generator for sequential circuits,” in Proc. Des. Auto. Conf., (Ana-heim, CA), pp. 84–89, June 1988.

[87] K. T. Cheng, V. D. Agrawal, and E. S. Kuh, “A sequential circuit testgenerator using threshold-value simulation,” in Digest of Papers, Fault-Tolerant Computing Symposium (FTCS-18), (Tokyo, Japan), pp. 24–29,June 1988.

[88] V. D. Agrawal and S. C. Seth, Test Generation for VLSI Chips. LosAlamitos, CA: IEEE Computer Society Press, 1988.

[89] V. D. Agrawal, H. Farhat, and S. C. Seth, “Test generation by fault sam-pling,” in Proc. Int. Conf. on Computer Design (ICCD-88), (Rye Brook,NY), pp. 58–61, Oct. 1988.

[90] V. D. Agrawal, “Testability and productivity - the merging of the twogoals,” in Proc. TECHCON’88 (An SRC Conference), (Dallas, TX),pp. 137–140, Oct. 1988.

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[91] V. D. Agrawal and S. C. Seth, “On a relationship between fault coverageand circuit testability,” in Proc. AT&T Conf. Electronic Testing, (Prince-ton, NJ), pp. 16.1–16.6, Oct. 1988.

[92] P. Agrawal, V. D. Agrawal, and K. T. Cheng, “Fault simulation inMARS,” in Proc. AT&T Conf. Electronic Testing, (Princeton, NJ),pp. 40.1–40.9, Oct. 1988.

[93] S. T. Chakradhar, M. L. Bushnell, and V. D. Agrawal, “Automatic testgeneration using neural networks,” in Proc. Int. Conf. on Computer-AidedDesign (ICCAD-88), (Santa Clara, CA), pp. 416–419, Nov. 1988.

[94] S. C. Seth and V. D. Agrawal, “On the probability of fault occurrence,”in Defect and Fault Tolerance in VLSI Systems (I. Koren, ed.), pp. 47–52,Plenum Publishing Corp., 1989.

[95] V. D. Agrawal and S. M. Reddy, “Fault modeling and test generation,” inVLSI Handbook (J. DiGiacomo, ed.), p. Chapter 8, New York: McGraw-Hill, 1989.

[96] V. D. Agrawal, “Design automation, expert opinion,” IEEE Spectrum,vol. 26, pp. 36–37, Jan. 1989.

[97] V. D. Agrawal, K. T. Cheng, and P. Agrawal, “A directed searchmethod for test generation using a concurrent simulator,” IEEE Trans.on Computer-Aided Design, vol. 8, pp. 131–138, Feb. 1989.

[98] S. C. Seth, V. D. Agrawal, and H. Farhat, “A theory of testability withapplication to fault coverage analysis,” in Proc. European Test Conference,(Paris, France), pp. 139–143, Apr. 1989.

[99] S. C. Seth and V. D. Agrawal, “A new model for computation of proba-bilistic testability in combinational circuits,” INTEGRATION, The VLSIJournal, vol. 7, pp. 49–75, 1989.

[100] K. T. Cheng and V. D. Agrawal, “Concurrent test generation and de-sign for testability,” in Proc. Int. Symp. Circ. Syst. (ISCAS), (Portland,Oregon), pp. 1935–1938, May 1989.

[101] K. T. Cheng and V. D. Agrawal, Unified Methods for VLSI Simulationand Test Generation. Boston: Kluwer Academic Publishers, 1989.

[102] K. T. Cheng and V. D. Agrawal, “An economical scan design for sequentiallogic test generation,” in Proc. 19th Fault-Tolerant Computing Symposium(FTCS-19), pp. 28–35, June 1989.

[103] P. Agrawal, V. D. Agrawal, K. T. Cheng, and R. Tutundjian, “Faultsimulation in a pipelined multiprocessor system,” in Proc. Int. Test Conf,(Washington, DC), pp. 727–734, Aug. 1989.

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[104] K. T. Cheng and V. D. Agrawal, “State assignment for initializable syn-thesis,” in Proc. Int. Conf. Computer-Aided Design (ICCAD-89), (SantaClara, CA), pp. 212–215, Nov. 1989.

[105] K. T. Cheng and V. D. Agrawal, “Design of sequential machines forefficient test generation,” in Proc. Int. Conf. Computer-Aided Design(ICCAD-89), (Santa Clara, CA), pp. 358–361, Nov. 1989.

[106] V. D. Agrawal and K. T. Cheng, “An architecture for synthesis of testablefinite state machines,” in Proc. First European Design Automation Con-ference, (Glasgow, UK), pp. 612–616, Mar. 1990.

[107] K. T. Cheng and V. D. Agrawal, “A partial scan method for sequentialcircuits with feedback,” IEEE Trans. Comput., vol. 39, pp. 544–548, Apr.1990.

[108] S. C. Seth, V. D. Agrawal, and H. Farhat, “A statistical theory of digitalcircuit testability,” IEEE Trans. Comput., vol. 39, pp. 582–586, Apr. 1990.

[109] P. Agrawal and V. D. Agrawal, “Can logic simulators handle bidirection-ality and charge sharing?,” in Proc. Int. Symp. Circ. Syst. (ISCAS), (NewOrleans), pp. 411–414, May 1990.

[110] K. T. Cheng and V. D. Agrawal, “Synthesis of testable finite statemachines,” in Proc. Int. Symp. Circ. Syst. (ISCAS), (New Orleans),pp. 3114–3117, May 1990.

[111] S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, “Automatic testgeneration using quadratic 0-1 programming,” in Proc. 27th ACM/IEEEDes. Autom. Conf., (Orlando, FL), pp. 654–659, June 1990.

[112] V. D. Agrawal and K. T. Cheng, “Test function specification in synthesis,”in Proc. 27th ACM/IEEE Des. Autom. Conf., (Orlando, FL), pp. 235–240,June 1990.

[113] K. T. Cheng and V. D. Agrawal, “An entropy measure for the complex-ity of multi-output Boolean functions,” in Proc. 27th ACM/IEEE Des.Autom. Conf., (Orlando, FL), pp. 302–305, June 1990.

[114] S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, “Polynomial timesolvable fault detection problems,” in Proc. 20th Fault-Tolerant Comput-ing Symposium (FTCS-20), (Newcastle-upon-Tyne, UK), pp. 56–63, June1990.

[115] V. D. Agrawal and H. Kato, “Fault sampling revisited,” IEEE Design &Test of Computers, vol. 7, pp. 32–35, Aug. 1990.

[116] S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, “Toward massivelyparallel automatic test generation,” IEEE Trans. CAD, vol. 9, pp. 981–994, Sept. 1990.

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[117] D. V. Das, S. C. Seth, P. T. Wagner, J. C. Anderson, and V. D. Agrawal,“An experimental study on reject ratio prediction for VLSI circuits:Kokomo revisited,” in Proc. Int. Test Conf., pp. 712–720, Sept. 1990.

[118] S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, “Neural net andBoolean satisfiability models of logic circuits,” IEEE Design & Test ofComputers, vol. 7, pp. 54–57, Oct. 1990.

[119] V. D. Agrawal and K. T. Cheng, “Finite state machine synthesis withembedded test function,” J. Electronic Testing: Theory and Applications(JETTA), vol. 1, no. 3, pp. 221–228, 1990.

[120] V. D. Agrawal and S. T. Chakradhar, “Statistical performance of a parallelprocessing system,” in Proc. ISMM Int. Conf. on Parallel and DistributedComputing and Systems, pp. 212–216, Oct. 1990.

[121] V. D. Agrawal and S. T. Chakradhar, “Logic simulation and parallel pro-cessing,” in Proc. Int. Conf. on CAD (ICCAD), pp. 496–499, Nov. 1990.

[122] V. D. Agrawal and S. T. Chakradhar, “Performance estimation in a mas-sively parallel system,” in Proc. Supercomputing ’90, pp. 306–313, Nov.1990.

[123] K. T. Cheng, V. D. Agrawal, and E. S. Kuh, “A simulation-based methodfor generating tests for sequential circuits,” IEEE Trans. on Computers,vol. 39, pp. 1456–1463, Dec. 1990.

[124] V. D. Agrawal, S. C. Seth, and J. S. Deogun, “Design for testability andtest generation with two clocks,” in Proc. 4th CSI/IEEE InternationalSymp. on VLSI Design, pp. 112–117, Jan. 1991.

[125] S. T. Chakradhar and V. D. Agrawal, “A novel VLSI solution to a difficultgraph problem,” in Proc. 4th CSI/IEEE International Symp. on VLSIDesign, pp. 124–129, Jan. 1991.

[126] S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, Neural Models andAlgorithms for Digital Testing. Boston: Kluwer Academic Publishers,1991.

[127] K. T. Cheng and V. D. Agrawal, “Methods for synthesizing testable se-quential circuits,” AT&T Technical Journal, vol. 70, pp. 64–86, Jan. 1991.

[128] S. T. Chakradhar, V. D. Agrawal, and M. L. Bushnell, “On test generationusing neural computers,” Intl. J. Computer Aided VLSI Design, vol. 3,pp. 241–257, 1991.

[129] K. T. Cheng and V. D. Agrawal, “State assignment for testable design,”Int. J. Computer Aided VLSI Design, vol. 3, pp. 291–307, 1991.

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[130] S. Bhawmik, C. J. Lin, K. T. Cheng, and V. D. Agrawal, “PASCANT:A partial scan and test generation system,” in Proc. Custom IntegratedCirc. Conf., May 1991.

[131] S. T. Chakradhar and V. D. Agrawal, “A transitive closure based algo-rithm for test generation,” in Proc. 28th Design Automation Conf., June1991.

[132] P. C. Sardeshmukh and V. D. Agrawal, “Filtering of SEM voltage contrastimages,” 3rd European Conf. Electron and Optical Beam Testing, Sept.1991.

[133] J. Villoldo, P. Agrawal, and V. D. Agrawal, “Stafan algorithms for MOScircuits,” in Proc. Intl. Conf. Computer Design, pp. 56–59, Oct. 1991.

[134] V. D. Agrawal, “Design and test — the two sides of a coin,” in Proc. Intl.Conf. Computer Design, p. 12, Oct. 1991.

[135] D. V. Das, S. C. Seth, and V. D. Agrawal, “Estimating the quality of man-ufactured digital sequential circuits,” in Proc. Intl. Test Conf., pp. 210–217, Oct. 1991.

[136] P. Agrawal, V. D. Agrawal, and S. C. Seth, “A new method for generatingtests for delay faults in non-scan circuits,” in Proc. 5th Intl. Conf. VLSIDesign, pp. 4–11, Jan. 1992.

[137] J. Jacob and V. D. Agrawal, “Functional test generation for sequentialcircuits,” in Proc. 5th Intl. Conf. VLSI Design, pp. 17–24, Jan. 1992.

[138] V. D. Agrawal, “Technology forecast and weather prediction (keynote ad-dress),” in Proc. 2nd Great Lakes Symp. on VLSI, pp. 1–2, Feb. 1992.

[139] K. T. Cheng and V. D. Agrawal, “Initializability considerations in sequen-tial machine synthesis,” IEEE Trans. Comput., vol. 41, pp. 374–379, Mar.1992.

[140] S. T. Chakradhar, M. A. Iyer, and V. D. Agrawal, “Energy minimizationbased delay testing,” in Proc. European Design Autom. Conf., pp. 280–284, Mar. 1992.

[141] S. T. Chakradhar, S. Kanjilal, and V. D. Agrawal, “A synthesis for testa-bility technique for PLA-based finite state machines,” in Proc. EuropeanDesign Autom. Conf., pp. 361–365, Mar. 1992.

[142] E. Ulrich, K. P. Lentz, J. Arabian, M. Gustin, V. D. Agrawal, and P. L.Montessoro, “The comparative and concurrent simulation of discrete-event experiments,” J. Electronic Testing: Theory and Applic. (JETTA),vol. 3, pp. 107–118, May 1992.

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[143] J. Jacob and V. D. Agrawal, “Multiple fault detection in two-level multi-output circuits,” J. Electronic Testing: Theory and Applic. (JETTA),vol. 3, pp. 171–173, May 1992.

[144] T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell, “Delay fault mod-els and test generation for random logic sequential circuits,” in Proc. De-sign Autom. Conf., pp. 165–172, June 1992.

[145] D. Bhattacharya, P. Agrawal, and V. D. Agrawal, “Delay fault test gen-eration for scan/hold circuits using Boolean expressions,” in Proc. DesignAutom. Conf., pp. 159–164, June 1992.

[146] S. T. Chakradhar, S. Kanjilal, and V. D. Agrawal, “Finite state machinesynthesis with fault tolerant test function,” in Proc. Design Autom. Conf.,pp. 562–567, June 1992. also J. Electronic Testing: Theory and Applic.(JETTA), vol. 4, pp. 57-69, February 1993.

[147] M. K. Srinivas, J. Jacob, and V. D. Agrawal, “Finite state machine testingbased on growth and disappearance faults,” in Proc. 22nd Fault-TolerantComput. Symp., pp. 238–245, July 1992.

[148] P. Agrawal, V. D. Agrawal, and S. C. Seth, “DynaTAPP: Dynamic tim-ing analysis with partial path activation in sequential circuits,” in Proc.EURO-DAC, pp. 138–141, Sept. 1992.

[149] V. D. Agrawal and S. T. Chakradhar, “Performance analysis of synchro-nized iterative algorithms on multiprocessor systems,” IEEE Trans. Par-allel and Distr. Syst., vol. 3, pp. 739–746, Nov. 1992.

[150] T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell, “Path delay simu-lation algorithms for sequential circuits,” in Proc. First Asian Test Symp.,pp. 52–56, Nov. 1992.

[151] S. Bose, P. Agrawal, and V. D. Agrawal, “A path delay fault simulatorfor sequential circuits,” in Proc. 6th International Conf. VLSI Design,pp. 269–274, Jan. 1993.

[152] P. Agrawal, V. D. Agrawal, and S. C. Seth, “Generating tests for delayfaults in nonscan circuits,” IEEE Design & Test of Computers, vol. 10,pp. 20–28, Mar. 1993.

[153] V. D. Agrawal, C. R. Kime, and K. K. Saluja, “A tutorial on built-inself-test, part 1: Principles,” IEEE Design & Test of Computers, vol. 10,pp. 73–82, Mar. 1993.

[154] K. L. Einspahr, S. C. Seth, and V. D. Agrawal, “Clock partitioning fortestability,” in Proc. 3rd Great Lakes Symp. VLSI, pp. 42–46, Mar. 1993.

[155] S. Bose, P. Agrawal, and V. D. Agrawal, “Delay fault testability evaluationthrough timing simulation,” in Proc. 3rd Great Lakes Symp. VLSI, pp. 18–21, Mar. 1993.

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[156] V. D. Agrawal and T. J. Chakraborty, “Partial scan testing with singleclock control,” in Proc. IEEE VLSI Test Symp., pp. 313–315, Apr. 1993.

[157] V. D. Agrawal and S. T. Chakradhar, “Combinational ATPG theoremsfor identifying untestable faults in sequential circuits,” in Proc. EuropeanTest Conf., pp. 249–253, Apr. 1993.

[158] V. D. Agrawal, “A tale of two designs: the cheapest and the most economic(keynote talk),” in Second International Workshop on the Economics ofDesign, Test and Manufacturing, May 1993. Also Proc. 12th AT&T Con-ference on Electronic Testing, September 1993, pp. 241-244.

[159] S. T. Chakradhar, V. D. Agrawal, and S. G. Rothweiler, “A transitive clo-sure algorithm for test generation,” IEEE Trans. CAD, vol. 12, pp. 1015–1028, July 1993.

[160] V. D. Agrawal, C. R. Kime, and K. K. Saluja, “A tutorial on built-in self-test, part 2: Applications,” IEEE Design & Test of Computers, vol. 10,pp. 69–77, June 1993.

[161] P. Agrawal, V. D. Agrawal, and J. Villoldo, “Sequential circuit test gen-eration on a distributed system,” in Proc. 29th Design Autom. Conf.,pp. 107–111, June 1993.

[162] T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell, “Design for testa-bility for path delay faults in sequential circuits,” in Proc. 29th DesignAutom. Conf., pp. 453–457, June 1993.

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[164] S. Bose, P. Agrawal, and V. D. Agrawal, “The optimistic update theoremfor path delay testing of sequential circuits,” J. Electronic Testing: Theoryand Applic., vol. 4, pp. 285–290, Aug. 1993.

[165] S. Kanjilal, S. T. Chakradhar, and V. D. Agrawal, “Test function embed-ding algorithms with application to interconnected finite state machines,”in Proc. EURO-DAC, pp. 219–224, Sept. 1993.

[166] S. Bose, P. Agrawal, and V. D. Agrawal, “Logic systems for path delaytest generation,” in Proc. EURO-DAC, pp. 200–205, Sept. 1993.

[167] S. Bose, P. Agrawal, and V. D. Agrawal, “Generation of compact de-lay tests by multiple path activation,” in Proc. International Test Conf.,pp. 714–723, Oct. 1993.

[168] S. Kanjilal, S. T. Chakradhar, and V. D. Agrawal, “A synthesis approachto design for testability,” in Proc. International Test Conf., pp. 754–763,Oct. 1993.

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[169] P. R. Sureshkumar, J. Jacob, M. K. Srinivas, and V. D. Agrawal, “FAS-SAD: Fault simulation with sensitivities and depth-first propagation,” inProc. 2nd Asian Test Symp., pp. 66–71, Nov. 1993.

[170] S. Bose, P. Agrawal, and V. D. Agrawal, “Path delay fault simulation ofsequential circuits,” IEEE Trans. VLSI Systems, vol. 1, pp. 453–461, Dec.1993.

[171] D. Das, S. C. Seth, and V. D. Agrawal, “Accurate computation of fieldreject ratio based on fault latency,” IEEE Trans. VLSI Systems, vol. 1,pp. 537–545, Dec. 1993.

[172] S. Kanjilal, S. T. Chakradhar, and V. D. Agrawal, “A test function ar-chitecture for interconnected finite state machines,” in Proc. 7th Interna-tional Conference VLSI Design, pp. 113–116, Jan. 1994.

[173] R. M. Chou, K. K. Saluja, and V. D. Agrawal, “Power constraint schedul-ing of tests,” in Proc. 7th International Conference VLSI Design, pp. 271–274, Jan. 1994.

[174] P. R. Sureshkumar, J. Jacob, M. K. Srinivas, and V. D. Agrawal, “An im-proved deductive fault simulator,” in Proc. 7th International ConferenceVLSI Design, pp. 307–310, Jan. 1994.

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[178] K. Heragu, V. D. Agrawal, and M. L. Bushnell, “FACTS: Fault coverageestimation by test vector sampling,” in Proc. 12th IEEE VLSI Test Symp.,pp. 266–271, Apr. 1994.

[179] V. D. Agrawal, “A tale of two designs: the cheapest and the most eco-nomic,” J. Electronic Testing: Theory and Applic., vol. 5, pp. 131–135,May 1994.

[180] K. Heragu, M. L. Bushnell, and V. D. Agrawal, “An efficient path de-lay fault coverage estimator,” in Proc. 31st Design Automation Conf.,pp. 516–521, June 1994.

[181] S. T. Chakradhar, A. Balakrishnan, and V. D. Agrawal, “An exact algo-rithm for selecting partial scan flip-flops,” in Proc. 31st Design Automa-tion Conf., pp. 81–86, June 1994.

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[182] V. D. Agrawal, C. J. Lin, P. Rutkowski, S. Wu, and Y. Zorian, “Built-in self-test for digital integrated circuits,” AT&T Tech. Jour., vol. 73,pp. 30–39, Mar. 1994.

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[186] T. J. Chakraborty and V. D. Agrawal, “Robust testing for stuck-at faults,”in Proc. 8th International Conf. VLSI Design, pp. 42–46, Jan. 1995.

[187] M. K. Srinivas, J. Jacob, and V. D. Agrawal, “Functional test generationfor non-scan sequential circuits,” in Proc. 8th International Conf. VLSIDesign, pp. 47–52, Jan. 1995.

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[191] S. T. Chakradhar, S. Rothweiler, and V. D. Agrawal, “Redundancy re-moval and test generation for circuits with non-Boolean primitives,” inProc. 13th IEEE VLSI Test Symp., pp. 12–19, April-May 1995.

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[194] S. T. Chakradhar, M. Iyer, and V. D. Agrawal, “Energy models for delaytesting,” IEEE Trans. CAD, vol. 14, pp. 728–739, June 1995.

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[196] S. Kanjilal, S. T. Chakradhar, and V. D. Agrawal, “Test function embed-ding algorithms with application to interconnected finite state machines,”IEEE Trans. CAD, vol. 14, pp. 1115–1127, Sept. 1995.

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[203] S. Bose and V. D. Agrawal, “Sequential logic path delay test generationby symbolic analysis,” in Proc. Fourth Asian Test Symp., pp. 353–359,Nov. 1995.

[204] V. D. Agrawal, “Science, technology and the indian society, A keynotetalk,” in Proc. 9th International Conf. VLSI Design, pp. 6–8, Jan. 1996.

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[207] V. D. Agrawal and D. Lee, “Characteristic polynomial method for ver-ification and test of combinational circuits,” in Proc. 9th InternationalConf. VLSI Design, pp. 341–342, Jan. 1996.

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[220] V. D. Agrawal, “Low-power design by hazard filtering,” in Proc. 10thInternational Conf. on VLSI Design, pp. 193–197, Jan. 1997.

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[228] S. Bose, V. D. Agrawal, and T. G. Szymanski, “Algorithms for switch leveldelay fault simulation,” in Proc. International Test Conf., pp. 982–991,1997.

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[230] K. Heragu, J. H. Patel, and V. D. Agrawal, “Fast identification ofuntestable delay faults using implications,” in Proc. International Conf.CAD, pp. 642–647, 1997.

[231] P. Chavda, J. Jacob, and V. D. Agrawal, “Optimizing logic using Booleantransforms,” in Proc. 11th International Conf. VLSI Design, pp. 218–221,1998.

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[233] A. K. Majhi and V. D. Agrawal, “Tutorial: Delay fault models and cover-age,” in Proc. 11th International Conf. VLSI Design, pp. 364–369, 1998.

[234] S. Majumder, V. D. Agrawal, and M. L. Bushnell, “Path delay testing:Variable-clock versus rated-clock,” in Proc. 11th International Conf. VLSIDesign, pp. 470–475, 1998.

[235] V. D. Agrawal and S. C. Seth, “Mutually disjoint signals and probabil-ity calculation in digital circuits,” in Proc. 8th Great Lakes Symp. VLSI,pp. 307–312, 1998.

[236] M. A. Gharaybeh, M. L. Bushnell, and V. D. Agrawal, “The path-statusgraph with application to delay fault simulation,” IEEE Trans. CAD,vol. 17, pp. 324–332, Apr. 1998.

[237] V. D. Agrawal, “Test education for vlsi systems design engineers,” in Proc.Computer Soc. Workshop on VLSI, pp. 62–64, 1998.

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[239] S. Bose, P. Agrawal, and V. D. Agrawal, “A rated-clock test method forpath delay faults,” IEEE Trans. VLSI Systems, vol. 6, pp. 323–331, June1998.

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[242] S. Bose, P. Agrawal, and V. D. Agrawal, “Deriving logic systems for pathdelay test generation,” IEEE Trans. Computers, vol. 47, pp. 829–846,Aug. 1998.

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[245] M. A. Gharaybeh, V. D. Agrawal, and M. L. Bushnell, “False path removalusing delay fault simulation,” in Proc. 7th IEEE Asian Test Symp., pp. 82–87, 1998.

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[246] V. D. Agrawal, “Design of mixed-signal systems for testability,” INTE-GRATION, The VLSI Journal, vol. 26, pp. 141–150, 1998.

[247] V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, “Dig-ital circuit design for minimum transient energy and a linear programmingmethod,” in Proc. 12th International Conf. VLSI Design, pp. 434–439,1999.

[248] K. Heragu, J. H. Patel, and V. D. Agrawal, “A test generator for segmentdelay faults,” in Proc. 12th International Conf. VLSI Design, pp. 484–491,1999.

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[252] Q. Peng, V. D. Agrawal, and J. Savir, “On the guaranteed failing andworking frequencies in path delay fault analysis,” in Proc. 16th IEEE In-strumentation and Measurement Technology Conf., pp. 1794–1799, 1999.

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[254] H.-C. Tsai, K.-T. Cheng, and V. D. Agrawal, “A testability metric forpath delay faults and its application,” in Proc. Asia and South PacificDesign Automation Conf. (ASP-DAC), pp. 593–598, Jan. 2000.

[255] J. T. deSousa and V. D. Agrawal, “Reducing the complexity of defectlevel modeling using the clustering effect,” in Proc. Design, Automationand Test in Europe (DATE) Conf., pp. 640–644, Mar. 2000.

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[259] P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, “Register-transfer levelfault modeling and test evaluation techniques for vlsi circuits,” in Proc.International Test Conf., pp. 940–949, Oct. 2000.

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[264] A. Giani, S. Sheng, M. Hsiao, and V. D. Agrawal, “Efficient spectraltechniques for sequential ATPG,” in Proc. Design, Automation and Testin Europe (DATE) Conf., pp. 204–208, Mar. 2001. Reprinted in Design,Automation, and Test in Europe, The Most Influential Papers of 10 YearsDATE, R. Lauwereins and J. Madsen (Eds.), Springer, 2008, pp. 455-464.

[265] A. Giani, S. Sheng, M. Hsiao, and V. D. Agrawal, “Novel spectral methodsfor built-in self-test in a system-on-a-chip environment,” in Proc. 19thIEEE VLSI Test Symp., pp. 163–168, Apr. 2001.

[266] Y. C. Kim, V. D. Agrawal, and K. K. Saluja, “Combinational test gener-ation for various classes of acyclic sequential circuits,” in Proc. Interna-tional Test Conf., pp. 1078–1087, Oct. 2001.

[267] Y. C. Kim, V. D. Agrawal, and K. K. Saluja, “Multiple faults: Model-ing, simulation and test,” in Proc. 7th ASPDAC/15th International Conf.VLSI Design, pp. 592–597, Jan. 2002.

[268] V. Gaur, V. D. Agrawal, and M. L. Bushnell, “A new transitive clo-sure algorithm with application to redundancy identification,” in Proc.1st International Workshop on Electronic, Design and Test Applications(DELTA’02), pp. 496–500, Jan. 2002.

[269] A. Giani, S. Sheng, M. Hsiao, and V. D. Agrawal, “Compaction-basedtest generation using state and fault information,” J. Electronic Testing:Theory and Applic., vol. 18, pp. 63–72, Feb. 2002.

[270] A. D. Sathe, M. L. Bushnell, and V. D. Agrawal, “Analog macromodel-ing of capacitive coupling faults in digital circuit interconnects,” in Proc.International Test Conf., pp. 375–383, Oct. 2002.

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[271] A. V. S. S. Prasad, V. D. Agrawal, and M. V. Atre, “A new algorithmfor global fault collapsing into equivalence and dominance sets,” in Proc.International Test Conf., pp. 391–397, Oct. 2002.

[272] V. D. Agrawal, D. H. Baik, Y. C. Kim, and K. K. Saluja, “Exclusive testand its applications in fault diagnosis,” in Proc. 16th International Conf.VLSI Design, pp. 143–148, Jan. 2003.

[273] V. Mehta, K. Dave, V. D. Agrawal, and M. L. Bushnell, “A fault-independent transitive closure algorithm for redundancy identification,”in Proc. 16th International Conf. VLSI Design, pp. 149–154, Jan. 2003.

[274] L. Rao, M. L. Bushnell, and V. D. Agrawal, “Graphical IDDQ signaturesreduce defect level and yield loss,” in Proc. 16th International Conf. VLSIDesign, pp. 353–360, Jan. 2003.

[275] T. Raja, V. D. Agrawal, and M. L. Bushnell, “Minimum dynamic powerCMOS circuit design by a reduced constraint set linear program,” in Proc.16th International Conf. VLSI Design, pp. 527–532, Jan. 2003.

[276] P. A. Thaker, V. D. Agrawal, and M. E. Zaghloul, “A test evaluationtechnique for VLSI circuits using register-transfer level fault modeling,”IEEE Trans. CAD, vol. 22, pp. 1104–1113, Aug. 2003.

[277] V. D. Agrawal, A. V. S. S. Prasad, and M. V. Atre, “Fault collapsing viafunctional dominance,” in Proc. International Test Conf., pp. 274–280,Sept. 2003.

[278] T. Raja, V. D. Agrawal, and M. L. Bushnell, “CMOS circuit design forminimum dynamic power and highest speed,” in Proc. 17th InternationalConf. VLSI Design, pp. 1035–1040, Jan. 2004.

[279] T. Raja, V. D. Agrawal, and M. L. Bushnell, “A tutorial on the emergingnanotechnology devices,” in Proc. 17th International Conf. VLSI Design,pp. 343–360, Jan. 2004.

[280] S. Majumder, B. B. Bhattacharya, V. D. Agrawal, and M. L. Bushnell,“New classification of path-delay fault testability in terms of stuck-atfaults,” Journal of Computer Science and Technology (Academia Sinica),vol. 19, pp. 955–964, Nov. 2004.

[281] J. Zhang, M. L. Bushnell, and V. D. Agrawal, “On random pattern gener-ation with the selfish gene algorithm for testing digital sequential circuits,”in Proc. International Test Conf., pp. 617–626, Oct. 2004.

[282] T. Raja, V. D. Agrawal, and M. L. Bushnell, “Variable input delay cmoslogic for low power design,” in Proc. 18th International Conf. VLSI De-sign, pp. 598–605, Jan. 2005.

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[283] K. Dave, V. D. Agrawal, and M. L. Bushnell, “Using contrapositive lawin an implication graph to identify logic redundancies,” in Proc. 18thInternational Conf. VLSI Design, pp. 723–729, Jan. 2005.

[284] R. K. K. R. Sandireddy and V. D. Agrawal, “Diagnostic and detectionfault collapsing for multiple output circuits,” in Proc. Design, Automationand Test in Europe (DATE’05), pp. 1014–1019, Mar. 2005.

[285] F. Hu and V. D. Agrawal, “Dual-transition glitch filtering in probabilisticwaveform power estimation,” in Proc. 15th IEEE Great Lakes Symp. onVLSI, pp. 357–360, Apr. 2005.

[286] Y. C. Kim, V. D. Agrawal, and K. K. Saluja, “Combinational automatictest pattern generation for acyclic sequential circuits,” IEEE Trans. CAD,vol. 24, pp. 948–956, June 2005.

[287] S. Uppalapati, M. L. Bushnell, and V. D. Agrawal, “Glitch-free design oflow power asics using customized resistive feedthrough cells,” in Proc. 9thVLSI Design & Test Symp. (VDAT’05), pp. 41–49, Aug. 2005.

[288] A. S. Mudlapur, V. D. Agrawal, and A. D. Singh, “A novel random accessscan flip-flop design,” in Proc. 9th VLSI Design & Test Symp. (VDAT’05),pp. 226–236, Aug. 2005.

[289] A. S. Doshi and V. D. Agrawal, “Independence fault collapsing,” in Proc.9th VLSI Design & Test Symp. (VDAT’05), pp. 357–366, Aug. 2005.

[290] T. Raja, V. D. Agrawal, and M. L. Bushnell, “Variable input delaycmos logic design for low dynamic power circuits,” in Proc. Power andTiming Modeling, Optimization and Simulation Workshop (PATMOS’05),pp. 436–445, Sept. 2005.

[291] Y. Lu and V. D. Agrawal, “Leakage and dynamic glitch power minimiza-tion using integer linear programming for Vth assignment and path balanc-ing,” in Proc. Power and Timing Modeling, Optimization and SimulationWorkshop (PATMOS’05), pp. 217–226, Sept. 2005.

[292] F. Hu and V. D. Agrawal, “Enhanced dual-transition probabilistic powerestimation with selective supergate analysis,” in Proc. IEEE InternationalConf. on Computer Design, pp. 366–369, Oct. 2005.

[293] A. S. Mudlapur, V. D. Agrawal, and A. D. Singh, “A random access scanarchitecture to reduce hardware overhead,” in Proc. International TestConf., Nov. 2005. Paper 15.1.

[294] V. D. Agrawal and A. S. Doshi, “Concurrent test generation,” in Proc.14th IEEE Asian Test Symp., pp. 294–297, Dec. 2005.

[295] K. R. Kantipudi and V. D. Agrawal, “On the size and generation of min-imal N-detection tests,” in Proc. 19th International Conf. VLSI Design,pp. 425–430, Jan. 2006.

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[296] T. Raja, V. D. Agrawal, and M. L. Bushnell, “Transistor sizing of logicgates to maximize input delay variability,” Journal of Low Power Elec-tronics, vol. 2, pp. 121–128, Apr. 2006.

[297] V. D. Agrawal, S. Bose, and V. Gangaram, “Upper bounding fault cov-erage by structural analysis and signal monitoring,” in Proc. 24th IEEEVLSI Test Symp., pp. 88–93, May 2006.

[298] N. Yogi and V. D. Agrawal, “Spectral characterization of functional vec-tors for gate-level fault coverage tests,” in Proc. 10th VLSI Design & TestSymp. (VDAT’06), pp. 407–417, Aug. 2006.

[299] F. Hu and V. D. Agrawal, “Input-specific dynamic power optimization forvlsi circuits,” in Proc. Int. Symp. on Low Power Electronics and Design(ISLPED’06), pp. 232–237, Oct. 2006.

[300] S. Bose and V. D. Agrawal, “Fault coverage estimation for non-randomfunctional input sequences,” in Proc. Int. Test Conf., pp. 19.3.1–19.3.10,Oct. 2006.

[301] N. Yogi and V. D. Agrawal, “Spectral RTL test generation for gate-levelstuck-at faults,” in Proc. 15th IEEE Asian Test Symp. (ATS06), pp. 83–88, Nov. 2006.

[302] Y. Lu and V. D. Agrawal, “CMOS leakage and glitch minimization forpower-performance tradeoff,” Journal of Low Power Electronics, vol. 2,pp. 378–387, Dec. 2006.

[303] Y. Lu and V. D. Agrawal, “Statictical leakage and timing optimizationfor submicron process variation,” in Proc. 20th International Conf. VLSIDesign, pp. 439–444, Jan. 2007.

[304] N. Yogi and V. D. Agrawal, “Spectral RTL test generation for micro-processors,” in Proc. 20th International Conf. VLSI Design, pp. 473–478,Jan. 2007.

[305] K. R. Kantipudi and V. D. Agrawal, “A reduced complexity algorithmfor minimizing N -detect tests,” in Proc. 20th International Conf. VLSIDesign, pp. 492–497, Jan. 2007.

[306] N. Yogi and V. D. Agrawal, “Transition delay fault testing of micropro-cessors by spectral method,” in Proc. 39th Southeastern Symp. on SystemTheory, pp. 283–287, Mar. 2007.

[307] S. Bose and V. D. Agrawal, “Delay test quality evaluation using boundedgate delays,” in Proc. 25th IEEE VLSI Test Symp., pp. 23–28, May 2007.

[308] R. K. K. R. Sandireddy and V. D. Agrawal, “Using hierarchy in designautomation: The fault collapsing problem,” in Proc. 11th VLSI Design &Test Symp. (VDAT’07), pp. 174–184, Aug. 2007.

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[309] S. Bose and V. D. Agrawal, “Estimating stuck fault coverage in sequentialcircuits using state traversal and entropy analysis,” in Proc. Int. TestConf., pp. 26.1.1–26.1.10, Oct. 2007.

[310] S. Bose, H. Grimes, and V. D. Agrawal, “Delay fault simulation withbounded gate delay model,” in Proc. Int. Test Conf., pp. 26.3.1–26.3.10,Oct. 2007.

[311] O. I. Khan, M. L. Bushnell, S. K. Devanathan, and V. D. Agrawal, “SPAR-TAN: a spectral and information theoretic approach to partial scan,” inProc. Int. Test Conf., Oct. 2007. Paper 21.1.

[312] L. Rao, M. L. Bushnell, and V. D. Agrawal, “Graphical IDDQ signaturesreduce defect level and yield loss,” IEEE Trans. VLSI Systems, vol. 15,pp. 1245–1255, Nov. 2007.

[313] F. Wang and V. D. Agrawal, “Single event upset: An embedded tutorial,”in Proc. 21st International Conf. VLSI Design, pp. 429–434, Jan. 2008.

[314] Y. Lu and V. D. Agrawal, “Total power minimization in glitch-free CMOScircuits considering process variation,” in Proc. 21st International Conf.VLSI Design, pp. 531–536, Jan. 2008.

[315] N. Yogi and V. D. Agrawal, “N -model tests for VLSI circuits,” inProc. 40th Southeastern Symp. System Theory, pp. 242–246, Mar. 2008.

[316] F. Wang and V. D. Agrawal, “Soft Error Rate Determination for Nanome-ter CMOS VLSI Logic,” in Proc. 40th Southeastern Symp. System Theory,pp. 324–328, Mar. 2008.

[317] R. Sethuram, M. L. Bushnell, and V. D. Agrawal, “Fault Nodes in Im-plication Graph for Equivalence/Dominance Collapsing, and Identify-ing Untestable and Independent Faults,” in Proc. 26th IEEE VLSI TestSymp., pp. 329–335, Apr. 2008.

[318] M. A. Shukoor and V. D. Agrawal, “A Primal-Dual Solution to Mini-mal Test Generation Problem,” in Proc. 12th IEEE VLSI Design & TestSymp., pp. 269–279, July 2008.

[319] W. Jiang and V. D. Agrawal, “Built-in Self-Calibration of On-Chip DACand ADC,” in Proc. International Test Conf., Oct. 2008. Paper 32.2.

[320] N. Yogi and V. D. Agrawal, “Sequential Circuit BIST Synthesis usingSpectrum and Noise from ATPG Patterns,” in Proc. 17th IEEE AsianTest Symp. (ATS08), pp. 69–74, Nov. 2008.

[321] F. Wang and V. D. Agrawal, “Soft Error Rates with Inertial and LogicalMasking,” in Proc. 22nd International Conf. VLSI Design, pp. 459–464,Jan. 2009.

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[322] J. D. Alexander and V. D. Agrawal, “Computing Bounds on DynamicPower Using Fast Logic Simulation,” in Proc. 41st Southeastern Symp.System Theory, pp. 107–112, Mar. 2009.

[323] S. Menon, A. D. Singh, and V. D. Agrawal, “Output Hazard-Free Transi-tion Delay Fault Test Generation,” in Proc. 27th IEEE VLSI Test Symp.,pp. 97–102, May 2009.

[324] S. Sindia, V. Singh, and V. D. Agrawal, “Polynomial Coefficient BasedDC Testing of Non-Linear Analog Circuits,” in Proc. 19th IEEE GreatLakes Symp. on VLSI, pp. 69–74, May 2009.

[325] J. D. Alexander and V. D. Agrawal, “Algorithms for Estimating Numberof Glitches and Dynamic Power in CMOS Circuits with Delay Variations,”in Proc. IEEE Computer Society Annual Symp. on VLSI, pp. 127–132,May 2009.

[326] J. T. Tudu, E. Larsson, V. Singh, and V. D. Agrawal, “On Minimizationof Peak Power for Scan Circuit during Test,” in Proc. 14th IEEE EuropeanTest Symp., pp. 25–30, May 2009.

[327] M. A. Shukoor and V. D. Agrawal, “A Two Phase Approach for Mini-mal Diagnostic Test Set Generation,” in Proc. 14th IEEE European TestSymp., pp. 115–120, May 2009.

[328] W. Jiang and V. D. Agrawal, “Designing Variation-Tolerance in Mixed-Signal Components of a System-on-Chip,” in Proc. International Symp.Circuits and Systems, pp. 126–129, May 2009.

[329] S. Sindia, V. Singh, and V. D. Agrawal, “Bounds on Defect Level andFault Coverage in Linear Analog Circuit Testing,” in Proc. 13th IEEEVLSI Design & Test Symp., pp. 410–421, July 2009.

[330] N. Yogi and V. D. Agrawal, “BIST/Test-Decompressor Design using Com-binational Test Spectrum,” in Proc. 13th IEEE VLSI Design & TestSymp., pp. 443–454, July 2009.

[331] S. Sindia, V. Singh, and V. D. Agrawal, “V-Transform: An EnhancedPolynomial Coefficient Based DC Test for Non-Linear Analog Circuits,”in Proc. 7th IEEE East-West Design & Test Symp., (Moscow, Russia),pp. 283–286, Sept. 2009.

[332] T. Raja, V. D. Agrawal, and M. L. Bushnell, “Variable input delay cmoslogic for low power design,” IEEE Trans. on VLSI Systems, vol. 17,pp. 1534–1545, Oct. 2009.

[333] S. Sindia, V. Singh, and V. D. Agrawal, “Multi-Tone Testing of Linear andNonlinear Analog Circuits using Polynomial Coefficients,” in Proc. 18thIEEE Asian Test Symp., (Taichung, Taiwan), pp. 63–68, Nov. 2009.

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[334] S. Sindia, V. Singh, and V. D. Agrawal, “Parametric Fault Diagnosis ofNonlinear Analog Circuits using Polynomial Coefficients,” in Proc. 23rdInternational Conf. on VLSI Design, (Bangalore), pp. 288–293, Jan. 2010.

[335] F. Wang and V. D. Agrawal, “Enhancing Random Access Scan for SoftError Tolerance,” in Proc. 42nd Southeastern Symp. on System Theory,pp. 263–268, Mar. 2010.

[336] F. Wang and V. D. Agrawal, “Soft Error Considerations for ComputerWeb Servers,” in Proc. 42nd Southeastern Symp. on System Theory,pp. 269–274, Mar. 2010.

[337] F. Wang and V. D. Agrawal, “Soft Error Rate Determination forNanoscale Sequential Logic,” in Proc. 11th International Symp. on QualityElectronic Design, pp. 225–230, Mar. 2010.

[338] Y. Zhang and V. D. Agrawal, “An Algorithm for Diagnostic Fault Simu-lation,” in Proc. 11th IEEE Latin-American Test Workshop, Mar. 2010.

[339] N. Yogi and V. D. Agrawal, “Application of Signal and Noise Theory toDigital VLSI Testing,” in Proc. 28th IEEE VLSI Test Symp., pp. 215–220,Apr. 2010.

[340] M. Kulkarni and V. D. Agrawal, “Matching Power Source to ElectronicSystem: A Tutorial on Battery Simulation,” in Proc. 14th VLSI Design& Test Symp., July 2010.

[341] Y. Zhang and V. D. Agrawal, “A Diagnostic Test Generation System,” inProc. International Test Conf., Nov. 2010. Paper 12.3.

[342] K. Kim and V. D. Agrawal, “True Minimum Energy Design Using DualBelow-Threshold Supply Voltages,” in Proc. 24th International Conf. onVLSI Design, (Chennai), pp. 292–297, Jan. 2011.

[343] K. Kim and V. D. Agrawal, “Minimum Energy CMOS Design with DualSubthreshold Supply and Multiple Logic-Level Gates,” in Proc. 12th In-ternational Symp. on Quality Electronic Design, pp. 689–694, Mar. 2011.

[344] M. Kulkarni, K. Sheth, and V. D. Agrawal, “Architectural Power Manage-ment for High Leakage Technologies,” in Proc. 43rd IEEE SoutheasternSymp. System Theory, pp. 67–72, Mar. 2011.

[345] M. Kulkarni and V. D. Agrawal, “Energy Source Lifetime Optimizationfor a Digital System through Power Management,” in Proc. 43rd IEEESoutheastern Symp. System Theory, pp. 73–78, Mar. 2011.

[346] M. Venkatasubramanian and V. D. Agrawal, “Subthreshold Voltage High-k CMOS Devices Have Lowest Energy and High Process Tolerance,” inProc. 43rd IEEE Southeastern Symp. System Theory, pp. 98–103, Mar.2011.

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[347] W. Jiang and V. D. Agrawal, “A DSP-Based Ramp Test for On-ChipHigh-Resolution ADC,” in Proc. 43rd IEEE Southeastern Symp. SystemTheory, pp. 203–207, Mar. 2011.

[348] S. Sindia, V. D. Agrawal, and V. Singh, “Distinguishing Process VariationInduced Faults from Manufacturing Defects in Analog Circuits using V-Transform Coefficients,” in Proc. 43rd IEEE Southeastern Symp. SystemTheory, pp. 231–236, Mar. 2011.

[349] P. Shanmugasundaram and V. D. Agrawal, “Dynamic Scan Clock Controlin BIST Circuits,” in Proc. 43rd IEEE Southeastern Symp. System Theory,pp. 237–242, Mar. 2011.

[350] K. Kim and V. D. Agrawal, “Dual Voltage Design for Minimum EnergyUsing Gate Slack,” in Proc. IEEE International Conf. Industrial Technol-ogy, pp. 419–424, Mar. 2011.

[351] S. Sindia and V. D. Agrawal, “Testing Linear and Non-Linear AnalogCircuits using Moment Generating Functions,” in Proc. 12th IEEE Latin-American Test Workshop, Mar. 2011.

[352] S. Sindia, V. D. Agrawal, and V. Singh, “Non-Linear Analog Circuit Testand Diagnosis under Process Variation using V-Transform Coefficients,”in Proc. 29th IEEE VLSI Test Symp., pp. 64–69, May 2011.

[353] P. Shanmugasundaram and V. D. Agrawal, “Dynamic Scan Clock for TestTime Reduction Maintaining Peak Power Limit,” in Proc. 29th IEEEVLSI Test Symp., pp. 248–253, May 2011.

[354] S. Alampally, T. V. Rakshith, P. Shanmugasundaram, R. A. Parekhji, andV. D. Agrawal, “An Efficient Test Data Reduction Technique throughDynamic Pattern Mixing across Multiple Fault Models,” in Proc. 29thIEEE VLSI Test Symp., pp. 285–290, May 2011.

[355] M. Kulkarni and V. D. Agrawal, “Architectural Power Management forBattery Lifetime Optimization in Portable Systems,” in Proc. 15th VLSIDesign & Test Symp., July 2011.

[356] K. Kim and V. D. Agrawal, “Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply,” Jour. Low Power Electronics, vol. 7,pp. 460–470, Dec. 2011.

[357] Y. Zhang and V. D. Agrawal, “Reduced Complexity Test Generation Al-gorithms for Transition Fault Diagnosis,” in Proc. 29th IEEE Int. Conf.on Computer Design, pp. 96–101, Oct. 2011.

[358] S. Sindia, V. D. Agrawal, and V. Singh, “Test and Diagnosis of AnalogCircuits using Moment Generating Functions,” in Proc. 20th IEEE AsianTest Symp., pp. 371–376, Nov. 2011.

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[359] P. Shanmugasundaram and V. D. Agrawal, “Externally Tested Scan Cir-cuit with Built-In Activity Monitor and Adaptive Test Clock,” in Proc.25th International Conf. on VLSI Design, pp. 448–453, Jan. 2012.

[360] M. A. Shukoor and V. D. Agrawal, “Diagnostic Test Set Minimizationand Full-Response Fault Dictionary,” Jour. Electronic Testing: Theoryand Applications, vol. 28, pp. 177–187, Apr. 2012.

[361] M. Allani and V. D. Agrawal, “An Efficient Algorithm for Dual-VoltageDesign Without Need for Level Conversion,” in Proc. 44th IEEE South-eastern Symp. System Theory, pp. 51–56, Mar. 2012.

[362] S. Sindia, F. F. Dai, and V. D. Agrawal, “All-Digital Replica Techniquesfor Managing Random Mismatch in Time-to-Digital Converters,” in Proc.44th IEEE Southeastern Symp. System Theory, pp. 130–134, Mar. 2012.

[363] O. Sinanoglu and V. D. Agrawal, “Retiming Scan Circuit to EliminateTiming Penalty,” in Proc. 13th IEEE Latin-American Test Workshop,pp. 137–142, Apr. 2012.

[364] S. Sindia and V. D. Agrawal, “Towards Sptial Fault Resilience in ArrayProcessors,” in Proc. 30th IEEE VLSI Test Symp., pp. 288–293, May2012.

[365] L. Zhao and V. D. Agrawal, “Net Diagnosis Using Stuck-at and TransitionFault Models,” in Proc. 30th IEEE VLSI Test Symp., pp. 221–226, May2012.

[366] S. Sindia, F. F. Dai, V. D. Agrawal, and V. Singh, “Impact of ProcessVariations on Computers Used for Image Processing,” in Proc. Interna-tional Symp. Circuits and Systems, pp. 1444–1447, May 2012.

[367] F. Rashid and V. D. Agrawal, “Power Problems in VLSI Circuit Testing,”in Progress in VLSI Design and Test, Lecture Notes in Computer Science,Volume LNCS 7373 (H. Rahaman et al., eds.), pp. 393–405, Springer, July2012. Proc. 16th VLSI Design & Test Symp., Shibpur, India.

[368] S. Sindia, V. D. Agrawal, and V. Singh, “Defect Level and Fault Coveragein Coefficient Based Analog Circuit Testing,” Jour. Electronic Testing:Theory and Applications, vol. 28, pp. 541–549, Aug. 2012.

[369] V. Sheshadri, V. D. Agrawal, and P. Agrawal, “Optimal Power-Constrained SoC Test Schedules With Customizable Clock Rates,” inProc. 25th IEEE International System-on-Chip Conf., pp. 271–276, Sept.2012.

[370] S. Sindia, V. D. Agrawal, and V. Singh, “Parametric Fault Testing ofNon-Linear Analog Circuits Based on Polynomial and V-Transform Co-efficients,” Jour. Electronic Testing: Theory and Applications, vol. 28,pp. 757–771, Oct. 2012.

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[371] S. Sindia and V. D. Agrawal, “Tailoring Tests for Functional Binning ofIntegrated Circuits,” in Proc. 21st Asian Test Symp., pp. 95–100, Nov.2012.

[372] K. Chakraborty and V. D. Agrawal, “Data-Driven DPPM Estimation andAdaptive Fault Coverage Calibration Using MATLAB,” Jour. ElectronicTesting: Theory and Applications, vol. 28, pp. 869–875, Dec. 2012.

[373] V. Sheshadri, V. D. Agrawal, and P. Agrawal, “Optimum Test Schedulefor SoC with Specified Clock Frequencies and Supply Voltages,” in Proc.26th International Conf. VLSI Design, (Pune), pp. 267–272, Jan. 2013.

[374] P. Venkataramani and V. D. Agrawal, “Reducing Test Time of PowerConstrained Test by Optimal Selection of Supply Voltage,” in Proc. 26thInternational Conf. VLSI Design, (Pune), pp. 273–278, Jan. 2013.

[375] O. Sinanoglu and V. D. Agrawal, “Eliminating the Timing Penaltyof Scan,” Jour. Electronic Testing: Theory and Applications, vol. 29,pp. 103–114, Feb. 2013.

[376] A. Shinde and V. D. Agrawal, “Managing Performance and Efficiency of aProcessor,” in Proc. 45th IEEE Southeastern Symp. System Theory, Mar.2013.

[377] S. Sindia, S. Gao, B. Black, A. S. Lim, V. D. Agrawal, and P. Agrawal,“MobSched: Customizable Scheduler for Mobile Cloud Computing,” inProc. 45th IEEE Southeastern Symp. System Theory, Mar. 2013.

[378] P. Venkataramani, S. Sindia, and V. D. Agrawal, “A Test Time Theoremand Its Applications,” in Proc. 14th IEEE Latin-American Test Workshop,Apr. 2013.

[379] P. Venkataramani, S. Sindia, and V. D. Agrawal, “Finding Best Voltageand Frequency to Shorten Power-Constrained Test Time,” in Proc. 31stIEEE VLSI Test Symp., pp. 19–24, Apr. 2013.

[380] C. Alagappan and V. D. Agrawal, “Defect Diagnosis of Digital CircuitsUsing Surrogate Faults,” in Communications in Computer and Informa-tion Science, Volume CCIS 382 (M. S. Gaur et al., eds.), pp. 376–386,Springer, July 2013. Proc. 17th VLSI Design & Test Symp., Jaipur, In-dia.

[381] S. Sindia and V. D. Agrawal, “Neural Network Guided Spatial Fault Re-silience in Array Processors,” Jour. Electronic Testing: Theory and Ap-plications, vol. 29, pp. 473–483, Aug. 2013.

[382] P. Venkataramani and V. D. Agrawal, “ATE Test Time Reduction UsingAsynchronous Clocking,” in Proc. International Test Conf., Sept. 2013.Paper 15.3.

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[383] S. Sindia and V. D. Agrawal, “High Sensitivity Test Signatures for Un-conventional Analog Circuit Test Paradigms,” in Proc. International TestConf., Sept. 2013. Paper PTF-1, TTTC E. J. McCluskey Best PhD ThesisFinalist.

[384] M. Allani and V. D. Agrawal, “Energy-Efficient Dual-Voltage DesignUsing Topological Constraints,” Jour. Low Power Electronics, vol. 9,pp. 275–287, Oct. 2013.

[385] V. Sheshadri, V. D. Agrawal, and P. Agrawal, “Power-Aware SoCTest Optimization through Dynamic Voltage and Frequency Scaling,” inProc. 21st IFIP/IEEE International Conf. VLSI (VLSI-SoC), (Istanbul,Turkey), pp. 105–110, Oct. 2013.

[386] B. Zhang, B. Li, and V. D. Agrawal, “Yield Analysis of a Novel WaferManipulation Method in 3D Stacking,” in Proc. IEEE International 3DSystems Integration Conference (3DIC), pp. 1–8, Oct. 2013.

[387] J. Yao and V. D. Agrawal, “Dual-Threshold Design of Sub-threshold Cir-cuits,” in Proc. IEEE Subthreshold Microelectronics Conference (S3S),pp. 77–78, Oct. 2013.

[388] B. Zhang and V. D. Agrawal, “A Novel Wafer Manipulation Method forYield Improvement and Cost Reduction of 3D Wafer-on-Wafer StackedICs,” Journal of Electronic Testing: Theory and Applications, vol. 30,pp. 57–75, Feb. 2014.

[389] S. Sindia and V. D. Agrawal, “Specification Test Minimization for GivenDefect Level,” in Proc. 15th IEEE Latin-American Test Workshop, (For-taleza, Brazil), pp. 1–6, Mar. 2014.

[390] P. Venkataramani, S. Sindia, and V. D. Agrawal, “A Test Time Theoremand its Applications,” Journal of Electronic Testing: Theory and Appli-cations, vol. 30, pp. 229–236, Apr. 2014.

[391] P. Venkataramani and V. D. Agrawal, “ATE Test Time Reduction byScaling Supply Voltage and Frequency,” in Proc. 31st IEEE VLSI TestSymp., pp. 1–3, Apr. 2014. TTTC E. J. McCluskey Best PhD ThesisContest.

[392] S. Gunasekar and V. D. Agrawal, “Optimal Selection of ATE Frequenciesfor Test Time Reduction Using Aperiodic Clock,” in Proc. 23rd IEEENorth Atlantic Test Workshop, (Johnson City, NY), pp. 52–56, May 2014.

[393] M. Venkatasubramanian and V. D. Agrawal, “A New Test Vector SearchAlgorithm for a Single Stuck-at Fault using Probabilistic Correlation,”in Proc. 23rd IEEE North Atlantic Test Workshop, (Johnson City, NY),pp. 57–60, May 2014.

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[394] B. Zhang and V. D. Agrawal, “An Optimal Probing Method of Pre-BondTSV Fault Identification in 3D Stacked ICs,” in Proc. IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), (SanFrancisco, CA), pp. 1–3, Oct. 2014.

[395] B. Zhang and V. D. Agrawal, “An Optimized Diagnostic Procedure forPre-Bond TSV Defects,” in Proc. 32nd IEEE International Conference onComputer Design, (Seoul, Korea), pp. 189–194, Oct. 2014.

[396] Y. Zhang, B. Zhang, and V. D. Agrawal, “Diagnostic Test Generation forTransition Delay Faults Using Stuck-At Fault Detection Tools,” Journalof Electronic Testing: Theory and Applications, vol. 30, pp. 763–780, Dec.2014.

[397] K. N. Jayaraman and V. D. Agrawal, “A Four-Transistor Level Con-verter for Dual-Voltage Low-Power Design,” Jour. Low Power Electronics,vol. 10, pp. 617–628, Dec. 2014.

[398] B. Zhang and V. D. Agrawal, “Diagnostic Tests for Pre-Bond TSVDefects,” in Proc. 28th International Conf. VLSI Design, (Bangalore),pp. 387–392, Jan. 2015.

[399] S. Gunasekar and V. D. Agrawal, “Few Good Frequencies for Power-Constrained Test,” in Proc. 28th International Conf. VLSI Design, (Ban-galore), pp. 393–398, Jan. 2015.

[400] B. Li, B. Zhang, and V. D. Agrawal, “Adopting Multi-Valued Logic forReduced Pin-Count Testing,” in Proc. 16th IEEE Latin American TestSymp., (Puerto Vallarta, Mexico), pp. 1–6, Mar. 2015.

[401] B. Li and V. D. Agrawal, “Multivalued Logic for Reduced Pin Countand Multi-Site SoC Testing,” in Proc. 24th IEEE North Atlantic TestWorkshop, (Johnson City, NY), pp. 49–54, May 2015.

[402] H. Zhang and V. D. Agrawal, “SoC TAM Design to Minimize Test Appli-cation Time,” in Proc. 24th IEEE North Atlantic Test Workshop, (John-son City, NY), pp. 55–60, May 2015.

[403] S. Gunasekar and V. D. Agrawal, “A Maximum Power Algorithm to FindFrequencies for Aperiodic Clock Testing,” Journal of Electronic Testing:Theory and Applications, vol. 31, pp. 403–410, Aug. 2015.

[404] S. Sindia and V. D. Agrawal, “Defect Level Constrained Optimization ofAnalog and Radio Frequency Specification Test,” Journal of ElectronicTesting: Theory and Applications, vol. 31, pp. 479–489, Oct. 2015.

[405] M. Venkatasubramanian and V. D. Agrawal, “Quest for a Quantum SearchAlgorithm for Testing Stuck-at Faults in Digital Circuit,” in Proc. IEEEInternational Symp. Defect and Fault Tolerance in VLSI and Nanotech-nology Systems, (Amherst, MA), pp. 128–133, Oct. 2015.

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[406] H. Liu and V. D. Agrawal, “Securing IEEE 1687-2014 Standard Instru-mentation Access by LFSR Key,” in Proc. IEEE 24th Asian Test Symp.,(Mumbai, India), pp. 91–96, Nov. 2015.

[407] H. Goyal and V. D. Agrawal, “Characterizing Processors for Energy andPerformance Management,” in Proc. 16th International Workshop on Mi-croprocessor/SoC Test and Verification (MTV), (Austin, TX), Dec. 2015.

[408] M. Venkatasubramanian and V. D. Agrawal, “Database Search and ATPG- Interdisciplinary Domains and Algorithms (Embedded Tutorial),” inProc. 29th International Conf. VLSI Design, (Kolkata, India), pp. 38–43, Jan. 2016.

[409] B. Li and V. D. Agrawal, “Applications of Mixed-Signal Technology inDigital Testing,” Journal of Electronic Testing: Theory and Applications,vol. 32, pp. 209–225, Apr. 2016.

[410] S. Kim and V. D. Agrawal, “Analytical Delay and Variations Modeling inthe Subthreshold Region,” in Proc. National Conference on UndergraduateResearch (NCUR), (Asheville, NC), Apr. 2016.

[411] M. Venkatasubramanian and V. D. Agrawal, “Failures Guide ProbabilisticSearch for a Hard-to-Find Test,” in Proc. 25th IEEE North Atlantic TestWorkshop, (Providence, RI), pp. 18–23, May 2016.

[412] V. Sheshadri and V. D. Agrawal, “Power-Aware Optimization of SoC TestSchedules Using Voltage and Frequency Scaling,” Journal of ElectronicTesting: Theory and Applications, vol. 33, pp. 171–187, Apr. 2017.

[413] Z. Zhou, U. Guin, and V. D. Agrawal, “Modeling and Test Generation forCombinational Hardware Trojans,” in Proc. 36th IEEE VLSI Test Symp.,(San Francisco, CA), pp. 1–6, Apr. 2018.

[414] B. Zhang and V. D. Agrawal, “Three-Stage Optimization of Pre-BondDiagnosis of TSV Defects,” Journal of Electronic Testing: Theory andApplications, vol. 33, pp. 573–589, Oct. 2017.

[415] M. M. Shihab and V. D. Agrawal, “Energy EfficientPower Distributionon Many-Core SoC,” in Proc. 32nd International Conference on VLSIDesign, pp. 488–493, 2019.

[416] P. Chowdhury, U. Guin, A. D. Singh, and V. D. Agrawal, “Two-Pattern∆IDDQ Test for Recycled IC Detection,” in Proc. 32nd International Con-ference on VLSI Design, pp. 82–87, 2019.

[417] J. Mahmod, S. Millican, U. Guin, and V. D. Agrawal, “Special Session:Delay Fault Testing - Present and Future,” in Proc. 37th IEEE VLSI TestSymp., (Monterey, CA), pp. 1–10, 2019.

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[418] S. Roy, B. Stiene, S. Millican, and V. D. Agrawal, “Improved RandomPattern Delay Fault Coverage Using Inversion Test Points,” in Proc. 28thIEEE North Atlantic Test Workshop, (Essex, VT).

[419] H. Goyal and V. D. Agrawal, “Technology Characterization Model andScaling for Energy Management,” in Proc. 23rd International Sympo-sium on VLSI Design and Test, (Indore, India), pp. 679–693, July 2019.Springer CCIS 1066.

[420] S. K. Millican, Y. Sun, S. Roy, and V. D. Agrawal, “Applying NeuralNetworks to Delay Fault Testing: Test Point Insertion and Random Cir-cuit Training,” in Proc. 28th IEEE Asian Test Symp., (Kolkata, India),pp. 1–6, 2019.

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