10

CHAPTER 2

LITERATURE SURVEY

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1. LITERATURE SURVEY

The digital down converters (DDC) / digital up converters (DUC)

are a significant part of 3G or 4G baseband transceivers and it

changes the intermediate frequency to baseband or baseband to

intermediate frequency. The decimation/interpolation filter is one

among the fundamental blocks in DDC / DUC. Their construction,

functioning can influence the performance of the entire system.

Digital down converter also does decimation and matched

filtering functions to eliminate the nearby channels and improves the

signal-to-noise ratio of the received information. Down sampler is a

fundamental sampling rate changing device employed to decrement

the rate of sampling of signal by an integer factor. Generally low pass

filters are employed to decrease the signal bandwidth before

decreasing the sampling rate.

The method of reducing the sampling rate of a signal in a signal

processing system is named as decimation. The device that changes

the sampling rate of the signal is known as decimator or down-

sampler. Decimation has to be performed in such a way to avoid the

aliasing effects. In general the decimator performs two functions:

filtering and down-sampling. The overlapping of the original spectrum

with continued replica occurs if the signal is not correctly band

limited. This effect can damage the appropriate information of the

decimated signal and it is called as aliasing. Hence the original signal

has to be band limited before down-sampling.

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The requirement of efficient decimation filter is increasing

rapidly for different reasons in the past few decades. This high

demand has created interest among researchers and design engineers

to develop efficient decimation filter structure with enhanced

magnitude response. The literature available on the present research

topic has been reviewed and presented in this section.

An optimum FIR linear phase digital filter was developed using a

computer program by McClellan et al. [1]. The program written in

FORTRAN is used to design different standard filters available. Such

programs are used to modify the filters with arbitrary frequency

specifications furnished by the users.

Bellanger et al. [2] have established a poly-phase network

structure and it allows for efficient sample-rate alterations for

recursive structures. The decrease in rate of computation can be

attained when there is an increase in modification factor.

Crochiere and Rabiner [3] have given an outline of multi-rate

digital signal processing especially to systems for interpolation and

decimation. In this overview, basic concepts of sampling rate

conversion, direct-form, poly-phase and time-varying structures for

realizing single-stage decimators or interpolators are discussed. The

characteristics of ideal filters and different filter design approaches for

realizing realistic filters are also discussed for sampling rate

conversion systems.

A linear phase performance of FIR digital filters for interpolation

and decimation was discussed by Saramaki [4]. The parameters of the

13

novel filters such as zero locations, sensitivity coefficient and variance

of noise in output due to errors occurred in rounding process are

contrasted with traditional FIR designs. It was emphasized that

combining multiple stages of decimators and interpolators will give

narrow-band filters that includes effectively few number of

computations per output with corresponding design.

Ramstad and Saramaki [5] have discussed a filter structure,

capable of realizing any low-pass and high-pass filters in practical and

it needs 50 to 60 computations per output. This structure is

dependent on multi-rate methods and balancing filters. The effects of

finite-word length and aliasing were also analyzed in their work.

Dempster and Macleod [6] have analyzed the usage of efficient

structures of shift and add multipliers, to decrease calculations in

filter banks and the simplified structure applied in interpolator design.

Gustafsson and Dempster [7] have examined the multiple constant

multiplications in a well-organized way to decrease the number of

arithmetic operations in the FIR filter realizations.

Gustafsson et al. [8] have realized the decomposed polyphase

filters of FIR using a MCM technique. This technique consumes lesser

number of adders and subtracters. The subfilters in direct form paved

way for few numbers of registers as a shared structure for

interpolation. However the registers of subfilters in transposed direct

form cannot be shared. The opposite applies for subfilters in direct

form and transposed direct form respectively. At last for various

14

implementations, observations for power, area and speed are

evaluated.

Eghbali et al. [9] have presented the FIR filter structures with

multiplierless implementation. It defines the number of adders needed

by the transposed direct structure as well as polyphase system with

decreased complexity.

The design and realization of FIR decimation filter structures

with sharp transitions are very complicated, sometimes impractical

using single-stage structures. The FIR filter length varies inversely to

the width of the pass band and it becomes complicated for sharp

filters. Hence in our research work we realize the decimation filter

structures with multi-stages. In addition the complexity of the

decimation filter structures are significantly reduced by the

introduction of comb structure in the initial stages. The literature

available related to the comb filter on the present research topic has

been reviewed and presented in the remaining section.

Hogenauer [10] intended a class of digital filter with only adders

and memory elements for interpolation and decimation to reduce the

hardware realization complexity. The filter was named as Cascaded-

Integrator-Comb filter since it contains an identical number of

integrators functioning at high sampling rate and comb sections

works at the low sampling rate.

The CIC filter structures having zero multipliers, comprising

only delay elements and adders, which is an important merit while

targeting low power consumption. The number of CIC sets is selected

15

to satisfy the system prerequisites to overcome the effects of imaging

or aliasing error. The magnitude characteristics of CIC filters is

completely controlled by only two integer parameters and results a

restricted range of filter features. The two control parameters are;

decimation/interpolation factor (M) and number of cascaded

integrator-comb sets (K). The aliasing/imaging error in the pass band

can be held within arbitrary bounds by appropriate choice of these

parameters in the framework.

Kaiser and Hamming [11] have portrayed the filter sharpening

method dependent on the concept of amplitude change function and

restricted to symmetric non-recursive filters. When processing data by

filters, it is needed to enhance the magnitude characteristics of the

filter, either by improving the out of-band rejection or by reducing the

error in the passband or both. This sharpening procedure tries to

enhance, magnitude characteristics of a symmetric non-recursive

filter by adopting several copies of the similar filter. This process is

called filter sharpening.

Hong-Kui Yang and Martin Snelgrove [12] have proposed a CIC

decimation filter with polyphase structures. This new structure can

work at a lower rate of sampling and attain similar magnitude

characteristics as proposed by Hogenauer and they have the merits of

low power consumption and high speed in operation.

Kwentus et al. [13] proposed the CIC based programmable

multirate decimation filter structure which enhances the magnitude

responses using filter sharpening approaches. This filter structure

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permits the initial stage of CIC decimation filter followed by second-

stage filter of fixed coefficient instead of a programmable filter thereby

obtaining a considerable hardware savings when compared to

techniques available. It maintains the advantages of the conventional

multiplierless CIC methodology and provides a tangible, PSOCs having

higher data rates using the above structure.

Kei-Yong Khoo et al. [14] have presented an effective structure

for the initial stage of the integrator, for a high-speed CIC decimation

filter. This structure was constructed with the help of carry-save

arithmetic concept and it is dependent on the properties of carry

propagation in a CSA. Area optimization can be achieved by reducing

the number of registers and savings in power can be achieved by

decreasing frequency of number of adders and register which are

enabled. Additionally, the full-adders can be replaced by half-adders

and considerable area is optimized for larger decimation rate and less

integrator stages.

Garcia et al. [15] have implemented a three-stage RNS based

CIC filters with Complex programmable logic devices. Compared to a

two’s complement design, the presented RNS-based design increases

the speed by 54%.

Partial-polyphase architecture for CIC decimation filters have

been proposed by Gao et al. [16]. Depending upon the polyphase

decomposition and the techniques of parallel processing, the proposed

structure can function at a low rate of sampling and obtain the same

performance as that of Hogenauer CIC filters. With this polyphase

17

decomposition, complications are eliminated in respect of decimation

ratio and high filter order. This proposed architecture provides the

merits of high speed function, consumption of low power and less

complexity against VLSI implementation.

An enhanced version of the non-recursive carry-save-adder-

based structures for CIC decimation filters for high speed functions

was proposed by Gao et al. [17]. This can be obtained by parallel

processing methods and hence the sampling rate of the CIC filter is

increased by this proposed structure. Power utilization and area

consumed are considerably reduced by applying the parallel

processing only to the critical stages, which control the sampling rate

of the non-recursive structure and by reduced-complexity realization

of the parallel stages.

Aboushady et al. [18] have presented a multi-rate multi-stage

CIC decimation filter for single-bit and multiple-bit sigma-delta

analog/digital converters. This structure significantly reduces the

sampling frequency of the filter using polyphase decomposition with

higher decimation rate at the initial stage. The appropriate selection of

the initial stage decimation rate can considerably enhances the device

utilization, power consumed and frequency of sampling.

A fifth order CIC decimation filter was proposed for GSM and

DECT application by Gao et al. [19] with programmable decimation

ratio of 8 and 16. The proposed filter structure consumes less power

consumption with the help of non-recursive structure for comb filter

and unwanted calculations were avoided. The polyphase design of

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each stage with data-broadcast structure was used to achieve the low

power.

An efficient multi-stage decimation filter structure for an analog

to digital converter was intended by Presti [20]. This proposed filter

structure composed of two-stages; the initial section of the filter was

attained by appropriately revolving the pole-zero distribution of a CIC

filter properly in the z-plane. The resulting structure provides linear

phase and it may be designed by using a recursive structure with only

two multipliers and hence the filter performance can be improved at

the expense of a moderate increase in difficulty.

Babic et al. [21] have proposed a decimation filter structure for

arbitrary ratio decimation. In this proposed structure two CIC filters

in parallel are used to compute the required sample values for the

purpose of linear interpolation. The performance of this structure

depends on the device in which the interpolation is made at a larger

rate of input being sampled.

Jang and Yang [22] have proposed multi-rate architecture for

non-recursive CIC decimation filters with an arbitrary factor. This

structure is applied when the decimation factors are represented by

the multiplication of prime numbers and this structure provides the

significant reduction of power dissipation compared to the

conventional structure.

Farden et al. [23] have presented a multirate cascade of

discrete-time CIC filters using frequency-weighted least-squares

approach. The errors produced by each stage in cascade are

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compensated. As a result, very simple high rate decimation filters can

be designed for the stages operating at higher sampling rates.

The multiplier-less design and implementation of a new digital

IF structures for SDR receivers are presented by Chan and Yeung [24].

This architecture consists of a compensator for compensating the

passband characteristics of the conventional CIC and eliminates the

need for a programmable FIR filter. The hardware complexities of the

proposed IF are minimized using a random search algorithm subject

to a given specification in the frequency domain and prescribed output

accuracy.

Adel Ghazel et al. [25] have described the architecture, the

synthesis and the hardware implementation of a decimation filter

designed for multistandard wireless receiver. The results show that

the use of carry ripple adders allows to minimizing the complexity for

comb filter implementation.

Dolecek and Mitra [26] have proposed an efficient sharpened

CIC filter of decimation for an even factor of decimation. The structure

comprises of two parts; a combination of moving average filters of first

order and a sharpening filter. The sharpening part is positioned to

work at half of the high rate of input sampling. The poly-phase sub

filters of the initial fragment can work at the 50% of the high input

sampling rate, using poly-phase decomposition.

Stephen and Stewart [27] have discussed the approaches for

sharpening the frequency responses of the CIC filters. Its partially

non-recursive implementation with power of 2 decimation rates

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provides replacement to the sharpened CIC filter techniques, if

considering the operating speed and compensation for the passband

characteristics of a conventional comb structure is a dispute.

Uusikartano and Takala [28] have presented a power-efficient

CIC decimator structure for fs/4 down converting digital receivers. In

this proposed structure power conservation is achieved by running all

the integrators at half of the sampling frequency, despite the

decimation ratio and the disadvantage of this structure is the

increased layout area. This decimator structure is suited for any

decimation ratio, even a prime or fractional number.

Rajic and Babic [29] have proposed an efficient decimation filter

structure consisting of a CIC filter with second order sharpening. This

proposed structure is significantly more power efficient and

appropriate to sharpening ACF due to no variation of factorization

abutting ACF of linearly mixed form. In this structure, every cascaded

stage is designed in non-recursive method with sharpened comb

filters.

Gerosa and Neviani [30] have been proposed a digital sinc filter

formed by the convolution between the samples of input signal and

the coefficients of filter as an alternative approach to the standard

CIC. This provides the eloquent decrease in hardware intricacy

compared to conventional CIC.

A novel architecture for a sharpened CIC filter structure was

presented by Dolecek and Mitra [31]. This structure comprises two

parts: a combination of comb filters with the down-sampling factor M1

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and a sharpened comb filter with a factor M2 and hence M=M1M2. It

permits the sharpening part to operate at a smaller rate which is M1

times lower than the high input rate and to work on a comb filter with

a length M2. The first part can be realized in non-recursive or

recursive form. The stop-band attenuation of this architecture not

depends on M1 for a given M and this structure provides lower pass-

band characteristics with a good stop-band attenuation compared to

the practical CIC filter.

A programmable CIC based decimation filter is designed for

sigma-delta ADC and manufactured in 1.5um n-well CMOS process

was described by Srivastava and Anantha [32]. The ADC scheme is

demonstrated for the over sampling ratios 16 and 64 with a respective

output resolution of 7 and 10 bits respectively. The programmability

characteristics of the sigma-delta ADC can be extended for higher

resolution further by functioning the ADC at corresponding higher

decimation ratios.

Dolecek and Carmona [33] have presented a novel improved

multistage CIC-Cosine decimation filter structure. This structure is

substuited by a multiple stage configuration, in which every stage

comprises a cascade of CIC filter with different amount of stages. The

presented filter structure is a cascade of modified CIC filter as well as

cosine pre-filters. With the help of cosine pre-filters the magnitude

response of this filter can be enhanced.

Dolecek and Mitra [34] have proposed a novel sharpened comb

decimation filter structure comprising of a sharpened and cascade of

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comb-filter based decimator. Applying poly-phase decomposition to

the initial stage, the sub filters can also be functioned at M1 time’s

lower rate. Stop-band attenuation of this arrangement not relies upon

M1 for a given value of M but pass band characteristics are improved

with the increase of M1.

Luis Teepanecatl-Xihuitl et al. [35] have presented a well-

organized architecture for CIC based decimation filter which reduces

the power considerably, by having the integrator with a poly-phase

structure in which every poly-phase part works at a lowered frequency

which is a complex section in multi-standard digital receivers. The

voltage given to the poly-phase structure is sized to decrease the

consumption of power without losing the performance of the whole

structure. Various communication methods like GSM, IS-95, UMTS

Mobitex and Ardis are considered in the filter design.

A novel two-stage decimation filter was presented by Dolecek

[36]. First section is the cascade of K1 in this structure, M1-length

comb filters and the respective cosine filters. The next part is the

cascade of K2, length comb filters and the corresponding cosine filters

is M2. Selecting 21 MM , less power utilization is achieved compared to

the case where 12 MM , because in the first stage the filtering is

shifted to the rate in which input rate is greater than 1M . Hence the

sharpening is applied only at the next stage, selecting 12 MM will yield

an improved magnitude response that in the reverse case. Hence the

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selection of decimation factors M1 and M2 relies on the compensation

between the desired stop-band attenuation and the power utilization.

The design of decimation filters with low power and high

precision through an efficient algorithm for sigma-delta ADC is

presented by Mortazavi Zanjani et al. [37]. This algorithm is applied to

the decimation filters with oversampling ratios of 32 to 256. The use of

multi-stage structure with half-band filters and CIC with enhanced

down-sampling approach has decreased the required amount of

arithmetic calculations considerably.

Zhang and Ofner [38] have proposed a CIC based decimation

filter structure for sigma-delta ADC with low-power for GSM

application with order 4 and its factor mth power of 2 and mth power of

3 poly-phase structures. The power utilization for non recursive

decimation filters with order 4 reduced about 70% contrasted to

recursive structure. The design space for recursive-less decimation

filters go beyond that of recursive decimation factors which have the

value more than 8.

Dolecek and Mitra [39] have intended a novel decimation filter

structure, which offers better stopband attenuation around the first

zero using stepped triangular impulses and cosine filters. This

proposed scheme consists two stages; the first stage comprises of

polyphase decomposition and the second stage comprises the cascade

of cosine filters and the CIC filter with length M2.

A novel decimation filter structure is presented with a

conversion factor by Dolecek et al. [40] in which the interpolation and

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decimation factors are reciprocally prime numbers. This structure

comprises of stepped triangular CIC and the expanded cosine filters.

The expansion factor is characteristically selected to reduce the

stopband characteristics of the filter. Finally it has 3 sections of

integrators and/or combs and provides better performance when

21 MM . This exhibits better magnitude response than the modified

CIC filter for software radio applications.

Wang and Li [41] proposed a decimation filter structure for

reconfigurable integer factor used in SDR receiver. The fundamental

concept behind this structure is that categorizing low-complexity and

large-decimation-factor in initial stages and high-attenuation and low-

decimation-factor components at the final stages. In this proposed

structure, the CIC filters are used in initial stage as anti-aliasing filter

with greater decimation factor, based on the over sampling rates in

various stages as final stages, Nyquist and equiripple half band filters

are used.

A multiplierless technique, based on the add and shift method

and common subexpression elimination for low area, low power and

high speed implementations of FIR filters was presented by Shahnam

Mirzaei et al. [42]. The result shows that a significant area and power

reductions over traditional Distributed Arithmetic based techniques

on Virtex II FPGA is achieved.

Dolecek and Mitra [43] have proposed a new CIC-based efficient

decimation filter for even number of decimation factor, which can be

attractive for software defined radio applications comprises of two

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stages. In this filter structure the pass-band droop has been enhanced

by the introduction sine-based compensator. This sine-based

compensator is influenced by the decimation factor M and a single

integer coefficient. It parameters are; k1 - CIC filter, L and k2 - cosine

filter and k3 - sine compensator. The pass-band performance is

enhanced by increasing k3 and the stopband performance has been

enhanced by increasing k1 and k2.

Torres and Dolecek [44] have proposed multistage decimation

filter based on the CIC-cosine decimation filter with second order

symmetric compensator. The compensator coefficients are represented

in canonical signed digits and it can be realized using only adders and

delay elements. This results multiplier-free structure provides

enhanced magnitude responses in passband and stopband.

Dolecek [45] presents a new decimation filter structure for a

logical conversion factor in which decimation factors and interpolation

are prime numbers. This filter structure is constructed on the stepped

triangular CIC filter, expanded cosine filters and sine-based

compensation filter. This filter is a second order filters which can be

implemented by shift and add functions. The resulting structure is a

multiplier-free structure.

A novel efficient multi-stage comb-RS decimation filter structure

was presented by Dolecek [46] to enhance the overall magnitude

characteristics of the filter. Here the initial stages are implemented in

non-recursive form by utilizing the poly-phase decomposition and the

filters in the initial stage are shifted to operate at a lesser rate.

26

Shahana et al. [47] have presented non-recursive CIC

decimators for sigma-delta converters with efficient polyphase

realization. This decimation filter structure provides high speed and

consumes low power compared to the recursive and non-recursive

realizations. The sampling rate reduction and filtering are done in

various phases to decrease the complexity of hardware and dissipation

of power. To achieve low power consumption and high operating

speed, small word length can be used at the initial stages and for the

subsequent stages, the increasing word length can be used.

Laddomada [48] proposed a novel decimation filter structure,

applicable for sigma-delta A/D converters. This structure offers

efficient passband droop, selectivity and stopband attenuation

compared to conventional comb decimation filters. This proposal is

the extension of modified-comb filters intended by Presti (2000). This

proposal is the combination of sharpening technique, which improves

the passband droop and modified-comb filers with rotated zeros,

which improve the stopband attenuation.

A mathematical framework is addressed to optimize the

decimation filters to improve the sigma-delta quantization noise

rejection at folding bands by Laddomada [49]. In terms of practical

implementation two different structures are presented namely

recursive and non-recursive implementation. It was focused to

enhance the elimination of quantization noise in the folding band and

decreasing the passband droops in the decimation filters.

27

Pramod Kumar Meher et al. [50] have presented the design

optimization of one- and two-dimensional fully-pipelined computing

structures for area-delay-power-efficient implementation of finite

impulse response (FIR) filter by systolic decomposition of distributed

arithmetic (DA)-based inner-product computation. For efficient DA-

based realization of FIR filter of different orders, the flexible linear

systolic design is implemented on a Xilinx Virtex-E FPGA. Various key

performance metrics such as number of slices, dynamic power

consumption, and energy density and energy throughput are

estimated for different filter orders and address-lengths. The analysis

results indicate that the performance metrics of the proposed

implementation is broadly in line with theoretical expectations.

Dolecek et al. [51] presented a multiplierless CIC based

decimation filter with compensator. The coefficient of the

compensation filter are defined by the number of cascaded CIC stages

‘K’ and the parameter ‘b’ which are the design parameters and the

choice of b is based on the chosen value of K.

A novel method is proposed by Yi and Wu [52] to calculate the

coefficients automatically for sinc filters. Filter coefficients could be

approached with state transition and accumulator chain, using

coefficient automatic calculation method, without any coefficient

storage. This method is a replacement to the conventional CIC method

and saves a maximum of 41% power. The performances of the

intended approaches are compared for general cases with various

filter orders and decimation factors. This exhibits that proposed one is

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good with low filter order which results in lower power compared to

CIC as well as acceptable area.

Malki et al. [53] have proposed a digital down converter

structure for triple-mode WCDMA, CDMA2000 and GSM. Using

programmable CIC filter blocks an enhanced hardware is achieved

when realizing the system in FPGA.

FPGA based efficient design of a DDC was presented by

Roddewig et al. [54] using a digital Costas loop as part of a wireless

system. The CIC filter is used in the digital down converter to reduce

the power consumption as a decimation filter with a FIR

compensation filter which operates with a reduced sampling rate.

Singh et al. [55] have presented a CIC based sigma-delta

decimation filter design and implementation. The implementation is

presented by analyzing each block and the multistage implementation

uses the CIC for large rate change and the FIR is used for lower rates

to achieve a very sharp response.

A modern very high speed digital decimation filter is described

by Liu and Willson [56], which is the combination of CIC multi-rate

design with filter sharpening technique to enhance the filters

passband characteristics. The sharpened CIC filter coefficients are

further encoded assigned power of two (SPT) to enable the decimation

filter to run at a faster clock rate considerably.

Shahana et al. [57] have presented a toolbox for the design of

multistage decimation filter for various wireless communication

methods. The toolbox is enhanced by using information processing

29

and filter design toolbox in MATLAB. This toolbox will help the user to

carry out a rapid design and analysis of decimation filters for multiple

standards without any mathematical calculations.

Xiong Liu [58] proposed a parallel CIC pre-filters structure, to

improve the speed of digital decimation filters greatly. By parallel

computations several times of clock rate, hardware saving can be

obtained especially for large decimation factors.

A novel two-stage multiplierless CIC based decimator is

proposed by Dolecek and Mitra [59]. In this structure, the first- stage

is a cascaded CIC filter and the second next stage is composed of

cascaded comb filter with a second-order compensator. The intended

filter structure provides better magnitude characteristics and the

design parameters are the decimation factors M1 and M2, number of

cascaded CIC filters K and L and the parameter b of the compensator.

Dolecek and Laddomada [60] have presented a simple recursive

Comb-Filter using the good pole-zero annulment in the rational z-

transfer function which eases the achievement of stability and an

efficient droop compensator of second order to rescue the passband

initiated by the filter.

Xiong Liu and Willson [61] have proposed the recursive

polyphase CIC prefilters to improve the speed of the digital decimation

for sigma-delta ADCs. The recursive calculations in the proposed filter

prevent the considerable area/complexity increases in conventional

polyphase decomposition realizations.

30

A new IIR filter of second order which effectively enhances the

magnitude characteristics of the CIC filter was presented by Alfonso

Fernandez-Vazquez and Dolecek [62]. By using the multirate identity

the filter can be placed to the smaller rates, which are D times less

than the high input rate. The parameters considered for this design is

the number of cascaded CIC filter K, the decimation factor D, the

passband frequency ωp and the weighted parameter α. In general IIR

filter has a nonlinear phase but the intended filter has a linear-phase

roughly defined by the pass-band frequency.

Dong Pei et al. [63] have proposed a FPGA based novel concept

for realizing Zoom FFT for high performance spectral analysis. To

decrease the computational difficulty of traditional Zoom FFT, multi-

stage decimation Zoom FFT was proposed with the help of the parallel

pipelining concept of FPGA and a well-organized CIC filter. In addition

polyphase filter were applied in to each stage of decimation

architectures. Contrasted with one-stage decimation filters, the

proposed one provides error free magnitude analysis and this concept

decreases the FPGA utilization and obtains higher operating speed.

Dolecek and Carmona [64] have presented a novel multistage

CIC-cosine decimation filter to improve the stopband CIC

characteristics. By adding the simple compensation filter with 2M-

order, the passband characteristics are enhanced. This technique can

be used for any value of M, in special case where M is in the form of 2k

and it provides lower power and high speed designs.

31

A power-efficient narrow-band digital front end for bandpass

sigma-delta ADC is presented by Shahein et al. [65] with a tunable

centre frequency. This presented a new structure that divides the

down converter into two mixers and moving a CIC decimation stages

between the two mixers. The first mixer is a quadrature mixer that

operates at a quarter of the sampling frequency and the other complex

mixer operates with a tunable frequency.

Vishal Awasthi and Trishla Devi Gupta [66] have analyzed the

performance of single and multistage CIC decimation filters to improve

the passband characteristics for decimation factor of 64. For an

overall decimation factor of 64, a decimation process is analyzed by

cascading CIC and FIR filters with different stages. It is found that

CIC filter with large sampling rate enhances the stopband attenuation,

whereas the FIR filters provide the desired passband characteristics.

Nikhil Reddy Karnati et al. [67] have proposed a well-organized

poly-phase sharpened CIC filter for sigma-delta ADCs. The power

requirements may decrease significantly contrasted to conventional

SCIC filter structures by using a combination of SCIC filter and CIC

filter with proper orientation. Further power reduction is achieved by

poly-phase realizations for CIC as well as SCIC filters.

Alfonso Fernandez-Vazquez and Dolecek [68] have introduced a

design of maximally flat CIC passband compensator filters. Here the

filter coefficients are derived by solving a set of linear equations. In

this case, 2nd and 4th order filters for the narrow-band and wideband

compensations are described. The realization difficulty of the intended

32

filters relies on the decimation factor D and the number of cascaded

stages N.

A new non-recursive comb decimation filter is presented by

Dolecek and Salgado [69] in which a decimation factor M is a power of

two. The design goal was to reduce the operating power by

compromising the desired minimum aliasing attenuation in all folding

bands.

Dolecek and Salgado [70] have presented an efficient non-

recursive comb decimation filter structure, in which a decimation

factor M is a power of three. The aim of this presentation is to

enhance the stopband attenuation at first folding band and reduce the

power consumption, while sacrificing the required minimum aliasing

attenuation in all other folding bands.

A new three cascaded decimator structures design with integer

coefficients is introduced by Mondal and Mitra [71] using a polynomial

factorization technique. Every designed decimator shows better stop-

band attenuation for a given order and decimation factor that a CIC

and for performance enhancement may not require any prefilters. A

fourth decimator structure is introduced which is a hybrid between

the CIC and GCF with coefficients approximated by integers.

Vishal Awasthi and Krishna Raj [72] have presented an efficient

CIC decimation filter that perform fast down sampling using singed

digit adder algorithm with compensated frequency droop that arises

due to aliasing effect during the decimation process. This newly

designed structure provides an optimum solution for all signal

33

processing applications which require sampling rate conversion with

higher speed and lesser area such as image and speech processing.

Ashok Agarwal et al. [73] have presented architecture for sample

rate conversion employing multiplexed CIC filters to down convert the

signal sampling rate by large factors using multiple stages for

multistandard radio communication system. From the comparison of

hardware resources, the results show that the compensation and

interpolation filters require more hardware resources in comparison to

mixers and CIC filter.

A mixed-integer linear programming (MILP) formulation to

design first-stage decimation filters for delta-sigma ADCs with a

minimum number of non-zero terms such that they meet the worst

case behavior of CIC-based filters in the stopband was introduced by

Oscar Gustafsson and Hakan Johansson [74]. The results show that

CIC-based FIR filters are highly competitive once the passband

deviation specification is large enough for the CIC-based filters to meet

the specifications.

The literatures reviewed so far, describes different methods to

enhance the magnitude responses of the CIC based decimation filter

structures. In addition, the literatures have shown that the design and

implementation of efficient decimation filter structure with required

magnitude responses, which consumes less device utilization and

power consumption, still on high demand for various wireless

applications.

34

Keeping the above reports and findings, the present research

has focused on design and realization of efficient decimation filter

structure using CIC structure in FPGA to reduce the device utilization

and power consumption, which meets the specifications of WiMAX

with decimation factor of M=8 and WCDMA with decimation factor of

M=16 systems.