llrf4.6 evaluation board - dimtel · llrf4.6 evaluation board dmitry teytelman july 7, 2014...

LLRF4.6 Evaluation BoardDmitry Teytelman

July 7, 2014

Introduction

This document is an update of LLRF4 documentation packet, describing up-to-date in-

formation on 2013 LLRF4.6 revision of the board. The main difference between LLRF4

(last revision 4.2, dated 2009-06-28) and LLRF4.6 is the FPGA. The updated board uses

Spartan-6 FPGA in CS324 package. Normally, the boards are assembled with the largest

and fastest part fitting the footprint — XC6SLX45-3CSG324. While smaller parts can be

used, there is little rationale to do so.

Besides the component changes, several new or improved features have been incorporated:

• Transition from Spartan-3 XC3S1000 to Spartan-6 XC6SLX45;

• New FPGA core supply switcher capable of 2.5 A;

• Power supply jumpers replaced by zero ohm resistors;

• Maximally flat PCB backside for thermal pad mounting on cold plate;

• Reduced parasitics on RF/IF inputs

• High quality stripline LO distribution network, capable of 3 GHz;

• LO 1:8 splitter works to 3.4 GHz;

• LVDS signals routed as 100 Ω differential lines;

• LVDS termination resistors deleted;

• DS1822 thermometer in TO-92 replaced by DS18B20 in SO-8;

• Improved input channel shielding assembly.

The rest of this paper walks through these changes in detail.

FPGA

LLRF4.6 transitions to a more modern Xilinx FPGA. The part is also slightly faster

than the old Spartan-3. A short summary of differences between the two parts is shown

below. Of course, logic cells comparison is imprecise, since Spartan-6 uses new 6-input

LUT architecture. Xilinx uses some fudge factors to convert slice counts to vague “logic

cells”.XC3S1000 XC6SLX45 Notes

Logic cells 17280 43661

Multipliers 24 58 DSP48A1 in S6

BlockRAM 24 116 18kbits

One quirk of LLRF4.6 FPGA setup is that two data bits on high-speed DAC interface are

driven by dual function pins R15 (IO L1P CCLK 2) and V10 (IO L30N GCLK0 USERCCLK 2).

The bitfile must be generated with startup clock set to CCLK (-g StartUpClk:CClk

option of bitgen) for these pins to function as user outputs.

1

RF/LO Subsystem

At the RF input, parallel LC matching network was removed (never used on the original

LLRF4, layout considerations).

LO 1:8 power splitter (4 input mixers, 2 output mixers, power monitor, monitor connector)

is now built from 7 Mini-Circuits QCN-series quadrature splitters. These parts cover the

range from 220 MHz to 3.4 GHz in multiple bands.

The following parts can be used to populate the board according to the desired LO and

RF frequencies:

U13, U21, U22, U23, U24, U25, U26: 2-way LO splitter

220-470 MHz QCN-3+

330-580 MHz QCN-5+

425-675 MHz QCN-7+

450-750 MHz QCN-8+

800-1375 MHz QCN-12+

675-1300 MHz QCN-13D+

1100-1925 MHz QCN-19+

1350-2450 MHz QCN-25+

1700-2700 MHz QCN-27+

2500-3400 MHz QCN-34+

M1, M2, M101, M102, M103, M104: level 13 mixer

40-2500 MHz SYM-25DMHW

5-3000 MHz SYM-30DMHW

RF down- and up-conversion can also be bypassed during production.

2

IF filters

Many different IF filter designs have been developed for the original LLRF4. Most of

these should work well with LLRF4.6. Some have already been updated and tested on the

revised board — see the table below. CF is center frequency, BW is the bandwdith, level

refers to the bandwidth measurement level (drop in dB from the peak). For narrow filters,

3 dB measurement is appropriate, for wider ones, 1 and 0.5 dB bandwidth is specified. In

all cases, full bandwidth from lower to upper magnitude drop points is listed.

CF (MHz) BW (MHz) Level (dB) FS (dBm)

Tested on LLRF4.6

50 MHz (original) 48.5 9 3 11

39 MHz (Dimtel) 39 5.5 3 -4

74 MHz (Dimtel) 74 11 3 -3

81 MHz (Dimtel) 81 12.4 3 -3

Wideband (J-PARC) 34.1 68.1 0.5 6

Tested on LLRF4.2

110 MHz (FERMI) 110 58 3 -7

186 MHz (APEX) 190 28 0.5 -5

DAC outputs are also filtered on the board, with a simple two element filter. Original

configuration is 150 nH series inductor followed by 100 pF parallel capacitor. This setup

has low-pass response with roughly 41MHz 3 dB bandwidth. This two element design can

be reconfigured for wider bandwidth, high-pass response, or bypassed altogether.

3

Power Supplies

FPGA 1.2V core supply has been reconfigured on LLRF4.6. The new switching regulator

is based on the LTC3604 from Linear Technologies. Here is a comparison of the new device

with the MAX1820X used on LLRF4.2:MAX1820X LTC3604 Units

Output current 0.6 2.5 A

Switching frequency 1 2 (up to 4) MHz

External sync Direct PLL

Sync frequency 10–16 (÷13) 0.8–4 MHz

The FPGA user I/O pin labeled ”SYNC” in the UCF provides the optional synchronization

function. Existing designs that used this feature based on the MAX1820X will need to be

adapted to the different characteristics of the new regulator chip.

One major problem with the MAX1820X was that changes in external sync drive cre-

ated large output voltage transients, locking up the FPGA (high power dissipation, no

JTAG/USB response). For those reasons, few designs made use of the synchronization

capability. With a synchronization PLL, LTC3604 can seamlessly go from free running

to synchronized mode and back to free running. Direct synchronization drive (without

divide-by-13 as in the MAX1820X) provides for more a flexible FPGA divide ratio.

Another power supply related change in LLRF4.6 is the deletion of 8 power output jumpers.

These made sense early on, but not at serial numbers above 100. Jumpers have been

replaced by zero ohm 0603 parts, so the regulators can still be disconnected from the

loads, if necessary.

4

LVDS inter-board communication

Since Spartan-6 supports internal differential termination for LVDS, on-board termination

resistors have been deleted. Direction and termination options can be specified in HDL

code now.

Unfortunately, Xilinx does not support bi-directional LVDS I/O with runtime termination

control. So the bit files have to explicitly define inputs and outputs, enabling termination

for the inputs. Since the signals are flipped on the cable, it is feasible to define 4 output

channels and 4 input channels, with identical bitfile on both FPGAs.

Connector Summary

Counterclockwise around the perimeter of the board

J101 SMA RF/IF input




J15 SMA LO input (+26 dBm nominal)

J17 SMA Clock input (+1 dBm nominal)

J7 34-pin header Geek port (see schematic)

J18 SMA RF/IF output

J19 SMA RF/IF output

J20 SMA Analog output (0 to 2.5V, 2.2 kΩ)

J9 24-pin header 12 channels Analog output (0 to 2.5V)

J8 6-pin Weidmuller SNS-compatible interlock I/O

J21 LEMO Trigger

J22 LEMO Trigger

J6 2.1 mm +5V, 1.2A pseudo-regulated power input

J1 Type B USB

J3 20-pin 0.5mm flex LVDS inter-board communication

Interior test points

J23 U.Fl LO monitor (remove R809 to maintain match)

J24 U.Fl ICS83940D output 17

J25 U.Fl ICS83940D output 4

J26 U.Fl AD9512 output 3

J27 2mm IF output channel 2

J28 2mm IF output channel 1

2mm test points are intended for use with a high-impedance single-ended FET scope probe.

5

RF Input

VA

LO

CLK

PD

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

OVR

VD

VREF

RF Input

VA

LO

CLK

PD

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

OVR

VD

VREF

RF Input

VA

LO

CLK

PD

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

OVR

VD

VREF

RF Input

VA

LO

CLK

PD

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

OVR

VD

VREF

USBinterface

SLED

XERR

+3.3VDDSPCLK

regulators

3.0V1

3.0V2

3.3VD

3.3VA

2.5VD

5Vin

3.3VA2

3.3V3

+1.2V

IMON

SYNC

VREF1

VREF2

IN1PD

IN1D0

IN1D1

IN1D2

IN1D3

IN1D4

IN1D5

IN1D6

IN1D7

IN1D8

IN1D9

IN1D10

IN1OVR

IN1D11

IN1D12

IN1D13

IN2PD

IN2D0

IN2D1

IN2D2

IN2D3

IN2D4

IN2D5

IN2D6

IN2D7

IN2D8

IN2D9

IN2D10

IN2OVR

IN2D11

IN2D12

IN2D13

IN3PD

IN3D0

IN3D1

IN3D2

IN3D3

IN3D4

IN3D5

IN3D6

IN3D7

IN3D8

IN3D9

IN3D10

IN3OVR

IN3D11

IN3D12

IN3D13

IN0PD

IN0D0

IN0D1

IN0D2

IN0D3

IN0D4

IN0D5

IN0D6

IN0D7

IN0D8

IN0D9

IN0D10

IN0OVR

IN0D11

IN0D12

IN0D13

fpga_caps

+3.3VD

+2.5VD

+1.2VD

+1.2VD

+2.5VD

+3.3VD

SLEDXERR

SYNC

+5V

12

34

56

78

910

1112

1314

1516

1718

1920

2122

2324

2526

J7

27

29

31

28

30

32

3334

J6

PJ102A

dual_rf_out

VD VA

QD0

QD1

QD2

QD3

QD4

QD5

QD6

QD7

QD8

QD9

QD10

QD11

QD12

QD13

LO1

ID0

ID1

ID2

ID3

ID4

ID5

ID6

ID7

ID8

ID9

ID10

ID11

ID12

ID13

SLEEP CLK

LO2

VREF

QD0

QD1

QD2

QD3

QD4

QD5

QD6

QD7

QD8

QD9

QD10

QD11

QD12

QD13

ID0

ID1

ID2

ID3

ID4

ID5

ID6

ID7

ID8

ID9

ID10

ID11

ID12

ID13

Local schematic pins at this level

an external database.

Clock

Distribution

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

(doubled) Qx2

Q13

Q14

Q15

Q16

Q17

CLKIN

3.3VA

SCLK

SDIO

CSB

housekeeping

ADC_CLK

ADC_SDO

ADC_SDI

ADC_CS

DAC_DIN2

DALLAS

LO

AO1

AO2

AI1

AI2

+3.3VD +3.3VA

+5V

DAC_CS

DAC_CLK

DAC_DIN1

IMON

DAC_DIN3

DALLAS

ADC_CLK

ADC_SDO

ADC_SDI

ADC_CS

J17

DAC_CLK

DAC_CS

DAC_DIN1

GEEK_DIO6

GEEK_PIN

GEEK_LED1

GEEK_LED3

GEEK_LED4

GEEK_LED2

GEEK_DIO1

GEEK_DIO2

GEEK_DIO3

GEEK_DIO4

GEEK_DIO5

GEEK_DIO6

are resolved to FPGA pads by

(5V)

RN7

IF_SLEEP

221

ΩR

1822

1Ω

R17

’1GT04U10

221

ΩR

19

10.0

ΩR

20

0.47µFC5

D4

150

ΩR

25

D5

150

ΩR

26

LOCAL_LED4

LOCAL_LED5

LO DistIn

LO1LO2LO3LO4LO5LO6

LO8

J15

J24

J25

IN OUT

GND

RN820dB

1234567891011121314151617181920

J3

Flex

L0PL0N

L1PL1NL2PL2N

L3PL3NL4PL4N

L5PL5NL6PL6N

L7PL7N

J21

J22

TRIG2

332

ΩR

38

TRIG1

332

ΩR

39

TTL High turns on output

+3.3V+5V

Send_OK Got_OK

External Interlocks

N_SEND_OK N_GOT_OK

LBNL LLRF Digital Board V4.6Larry Doolittle, LBNL

Page 1/102013-08-13

Top Level

Dmitry Teytelman, Dimtel

DAC_DIN2

GEEK_DIO5

DIV_CSB

DAC_DIN3

681

ΩR

107

681

ΩR

106

1000pFC105

1.0µFC111

1.0µFC110

+3.0VA +2.5VD

CLK

2.2µFC112

PD

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

OVR

Use 100Ω resistor pack

RN101

RN102

T101

150ΩR103

ADT16-1T

10.0pFC107

680nHL103

330pFC103

22nHL102

D11

D12

D13

0.1µFC109

2.2µFC113

37.4

ΩR

102

LO

150ΩR101

1244 MHz

78 MHz

1300 MHz+10 dBm F.S. +4 dBm

-2 dBm F.S.

+13 dBm

RF LO

IF

SYM-25DMHW

M101

LTC2249

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

OF

IN+

IN-

OE

SHDN

REFH

REFL

SENSE

VCM

GND

CLK

+VS VDRVMODE

U101

(QFP32)

D12

D13

56 MHz

1.0 V F.S. diff. peak-peak

49.9ΩR104

0.1µFC114

0pFC108

0pFC104

470

pFC

106

NPOJ101

INPUT

∞Ω

R10

9681ΩR

108

VREF0.625 V

10nHL104

1.0µFC117


Page 2/102013-08-13

RF Input Channel


IN OUT

GND

RN1032dB

0.1µFC116

0.1µFC115

2.2µFC118

0ΩR1

0ΩR2

RN1

M0M1

TDOTDI

TCKTMS

U1

INIT_BPROG_B

XC6SLX45-CS324

GCLK1GCLK2

DONE

HSWAP_EN

GCLK0

FIFOADR0CTL2

PA7

PA4PA5

U2

CY7C68013A-LF56

PA3PA2PA1PA0

SDASCL

XTALINXTALOUT

DPLUSDMINUS

IFCLKCLKOUT

RESET#WAKEUP#

GND AGND

AVCCVCC

RESERVED

CTL2

PA6

Y124.0 MHz

12pFC1

12pFC2

SDA

SCL U3

WC

VCC E1

E2

E3

VSS

M24C324.75kΩR4

4.75kΩR5

1

2

3

4

5

6

USB

Type

B

J1T

332

ΩR

6

D1

0ΩR7

XERR

SLED

+3.3VD

+3.3VD +3.3VD0.1µFC81

0.47µFC82

0.1µFC83

+3.3VD

0ΩR11

DSPCLK

’1GT04U11

10.0ΩR

21

0.47µF

C6

+3.3VD

D2

150

ΩR

22

’1GT04U12

10.0ΩR

23

0.47µF

C7

+3.3VD

D3

150

ΩR

24


Page 3/102013-08-13

USB Interface


0.47µFC9

82.5kΩR34

0.47µFC10

2.2µFC622

4.75kΩR59

(48 MHz)TP1

∞Ω

R60

∞Ω

R61

1

2

3

4

5

6

USB

Type

B

J1S

1MΩR63

4700pFC86

+5V

22nHL33

10nFC602

EN VIN GND VOUT BYPASS

TPS79530

U601

tab(NC)

3.0V1

10nFC605


TPS79530

U602

tab(NC)

3.0V2

2.2µFC603

2.2µFC606

10nFC608


TPS79533

U603

tab(NC)

3.3VA

2.2µFC609

3.3VD

2.5VD

214 mA nominalsupplies 2 x ADC

214 mA nominalsupplies 2 x ADC

83 mA nominalsupplies DAC

213 mA nominalsupplies FPGA VCCO

140 mA nominalsupplies FPGA VCCAUX and ADC OVDD

10nFC617


TPS79533

U606

tab(NC)

3.3VA3

2.2µFC618

27 mA nominalsupplies System ADC and DAC

10nFC620


TPS79533

U607

tab(NC)

3.3VA2

2.2µFC621

146 mA nominalsupplies Clock Distribution

10nFC614


TPS79533

U605

tab(NC)

2.2µFC615

10nFC611


TPS79525

U604

tab(NC)

2.2µFC612

2.2µFC601

2.2µFC604

2.2µFC607

2.2µFC610

2.2µFC613

2.2µFC616

2.2µFC619

0Ω

R60

20

ΩR

604

0Ω

R60

60

ΩR

608

0Ω

R61

00

ΩR

612

0Ω

R61

4

Vin

RUN

PGOOD

TRACK/SS

BOOST

SW

Von

PGND

LTC3604EUD

U30

Vin

INTVcc

ITH

RT

SGND

MODE/SYNC

SW

FB0.

68µH

L31

47µFC30

22pFC34

+1.2V

22nH

L32

47nFC33

22µFC35

0.1

uFC

36

SYNC

20kΩR31

20kΩR32

0.47

ΩR

40

VIN+ VIN-

GND

V+ OUT

INA138

U5IMON

2.2µFC31

2.5 A maxsupplies FPGA Core

1.0µFC37

1.0µFC38

VIN

GND

TP

NC

TP

NC

VOUT

TRIM

ADR421U18

4.3kΩR41

4.3kΩR42

4.3kΩR43

4.3kΩR44

0.47µFC39

100µFC41

100µFC40

VREF2

VREF1


Page 4/102013-08-13

Voltage Regulators


2.50 Volts

1.25 Volts

0.625 Volts

2.2µFC29

10.0

ΩR

33

0ΩR37

D6

0Ω

R62

00

ΩR

621

0Ω

R62

20

ΩR

623

0Ω

R62

7

0Ω

R62

40

ΩR

625

0Ω

R62

6

49.9

ΩR

30160kΩR50

2.2µFC32

14kΩR62

150pFC50

TP2

0.47µFC63

+2.5VD

0.47µFC64

0.47µFC65

0.47µFC66

0.47µFC67

0.47µFC68

0.47µFC69

0.47µFC70

0.47µFC51

+1.2VD

0.47µFC52

0.47µFC53

0.47µFC54

0.47µFC71

0.47µFC72

0.47µFC73

0.47µFC74

0.47µFC58

+2.5VD

0.47µFC59

0.47µFC60 VCCO for banks 6, 7, 0, 1 connected to ADCs

0.47µFC55

+3.3VD

0.47µFC56

0.47µFC57

0.47µFC61

0.47µFC62 VCCO for other banks


Page 5/102013-08-13

FPGA Power Capacitors


2.2µFC623

2.2µFC624

QD0

QD1

QD2

QD3

QD4

QD5

QD6

QD7

QD8

QD9

QD10

QD11

QD12

QD13

ID0

ID1

ID2

ID3

ID4

ID5

ID6

ID7

ID8

ID9

ID10

ID11

ID12

ID13

ISL5927 QOUTA

QOUTB

QCOMP

SLEEP

FSADJ

REFIO

REFLO

ICOMP

IOUTA

IOUTB

DVDD

DGND AGND

AVDD

CLK

U4

+3.3VD +3.3VA

0.1µF

C80

0.1

µFC

79

0.1µFC78

0.1µFC76

0.1

µFC

750.

1µF

C77

2.00

kΩR

8

SLEEP

CLK

QD0

QD1

QD2

QD3

QD4

QD5

QD6

QD7

QD8

QD9

QD10

QD11

QD12

QD13

ID0

ID1

ID2

ID3

ID4

ID5

ID6

ID7

ID8

ID9

ID10

ID11

ID12

ID13

T1

T2

49.9

ΩR

9

49.9ΩR

10

J19

J18

Full scale output current

is 32*Vref/R8

Internal Vref is 1.23 V

RFLO

IF

SYM-25DMHW

M2

150nH L3

100pFC85

RFLO

IF

SYM-25DMHW

M1

150nH L2

100pFC84

LO1

LO2

J27

J28

∞ΩR45

0ΩR46

VREF


Page 6/102013-08-13

RF Output Channels


IN OUT

GND

RN102dB

IN OUT

GND

RN92dB

ADT1-1WT

ADT1-1WT

0Ω

R35

2.2µFC625

RN2

RN3

RN4

RN5

RN6

Q0

LVCMOS_CLK

CLK_SEL

PCLK

nPCLK

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q11

Q12

Q13

Q14

Q15

Q16

Q17

Q10

ICS83940D

VDDOVDD

GND

U9

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q10

Q11

Q13

Q14

Q15

Q16

Q17

3.3VA

CLKIN

124ΩR14

84.5ΩR15

J26

4.12 kΩR29

0.1µFC46

0.1µFC47

0.47µFC48

0.47µFC49


Page 7/102013-08-13

Clock Distribution


OUT0OUT0B

OUT1OUT1B

OUT2OUT2B

OUT3OUT3B

OUT4OUT4B

STATUSFUNCTION

DSYNCDSYNCB

CLK1CLK1B

CLK2CLK2B

SCLKSDIOSDOCSB

AD9512

VS

GND RSET

U17

1000

pFC

310

00pF

C4 200Ω

R16

CSB

SDIOSCLK

124ΩR12

84.5ΩR13

T3

Mini-Circuits TCM4-19

DB714 case, gs pinout

1000 pFC8

Qx2

49.9

ΩR

2849

.9Ω

R27

0.47µFC42

0.47µFC43

0.1µFC44

0.47µFC45

39.2

kΩR

36

2.2µFC626

4.75 kΩR58

ADC_CLKADC_SDOADC_SDIADC_CS

DAC_CLK

MCP3208

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

VDD

AGND

CLK

CS

DIN

DOUT

DGND

VREF

(SO-16)U801

DAC_DIN1

DALLAS

DS1822DQ

GND

(SOIC-8)U804

VDD

+3.3VA

+3.3VA+3.3VA

AD8361RFIN

PWDN

VPOSFLTR

VRMS

COMM

U805

(uSOIC-8)SREFIREF

+3.3VA

1000pFC802

49.9ΩR801

2.21

kΩR

802

LOSerial Number

ADC

3 x DAC

2.21

kΩR

803

10nF

C80

3

68.1ΩR804

100

pFC

804

10nF

C80

5

4.75kΩR805

+3.3VD

AO1

AO2

AI1

AI2

4.75kΩR806

4.75kΩR807

10nFC806

221kΩR808

220pFC807

+5V

30-2500 MHz from SMA


Page 8/102013-08-13

Housekeeping


NC

NC

DAC_CS

DAC_DIN2

22nHL801

10nF

C80

8

IMON

J20

0ΩR810

1

2

3

4

5

6

7

8

J9

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

AD56x4R(MSOP-10)

U806

VDD

GND

VOUTA

SCLK

DIN

VOUTB

VOUTC

VOUTD

VREF

SYNC

AD56x4R(MSOP-10)

U807

VDD

GND

VOUTA

SCLK

DIN

VOUTB

VOUTC

VOUTD

VREF

SYNC

AD56x4R(MSOP-10)

U808

VDD

GND

VOUTA

SCLK

DIN

VOUTB

VOUTC

VOUTD

VREF

SYNC

DAC_DIN3

10nF

C81

010

nFC

809

221ΩR811

∞Ω

R81

2∞

ΩR

813

∞Ω

R81

422

1Ω

R81

5 0.47µFC811

+3.3VA

0.47µFC812

0.47µFC813

0.47µFC814

0.47µFC815

+3.3VA

2.2µFC627

MiniCircuits QCNSum

Term 0

90

U21GND GND

LO1

LO2

LO3

LO4

LO5

LO6

LO8

LO

J23

49.9ΩR809


Page 9/102013-08-13

LO Distribution


MiniCircuits QCNSum

Term 0

90

U22GND GND

MiniCircuits QCNSum

Term 0

90

U23GND GND

MiniCircuits QCNSum

Term 0

90

U24GND GND

MiniCircuits QCNSum

Term 0

90

U26GND GND

MiniCircuits QCNSum

Term 0

90

U13GND GND

49.9ΩR816

49.9ΩR822

49.9ΩR818

49.9ΩR819

49.9ΩR820

49.9ΩR821

MiniCircuits QCNSum

Term 0

90

U25GND GND

49.9ΩR817

D701

RF_PERMIT

RF_PERMIT Return

IN+

IN-

CathodeVO

VE

VCC

Gnd

HCPL-060L

(SOIC-8)U701

+3.3V

Low output meansInterlock OK

Send_OK

+5V

MPS_PERMIT

MPS_PERMIT Return

D702

J8

MMBD914

BZ

X38

4-C

5V6

BCW60DCT

Got_OK

to FPGA

Q701

Weidmuller P/N 172863

(WIED6)

(SOT23)

(SOT23)

(SO

T23

)

RearPanelMount

NPO

2.21kΩR705

221ΩR704

82.5kΩR702

681

ΩR

701

2.21

kΩR

703

47pFC701

470

pFC

702


Page 10/102013-08-13

Interlock Input/Output


681

ΩR

706

llrf4.pcbLLRF4, top, scale = 1:1.000

llrf4.pcbLLRF4, bottom (mirrored), scale = 1:1.000

llrf4.pcbLLRF4, topassembly, scale = 1:1.000

llrf4.pcbLLRF4, bottomassembly (mirrored), scale = 1:1.000

llrf4.pcbLLRF4, fab, scale = 1:1.000

llrf4.6 evaluation board - dimtel · llrf4.6 evaluation board dmitry teytelman july 7, 2014...

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