ln-1.3.1-introduction to electronic circuit analysis

8/12/2019 LN-1.3.1-Introduction to Electronic Circuit Analysis

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ELECTRONIC CIRCUIT ANALYSIS

David J. Sager

Copyright 1972 and 1999, David J. Sager. Permission is hereby given for anyone to copy,reproduce, and distribute this work in its entirety or in part, for any purpose, provided that

proper attribution to the author is included, and a reference to where the entire work may beobtained is included. If the entire work, including this copyright notice, is kept intact andunaltered, then this in itself constitutes such reference. Otherwise, the requirement for a

reference may be satisfied by including a World Wide Web location or Internet Address fromwhich the entire work may be downloaded.If the work is altered, this must be clearly noted in the attribution.

The author is available by email [email protected]

Table of Contents

. Foreword..................................................................................................................... 2

. Introduction.................................................................................................................. 6

1.1 Circuit Analysis....................................................................................................... 6

1.2 Describing Circuits.................................................................................................. 6

. Network Topology....................................................................................................... 8

2.1 Terminals................................................................................................................. 8

2.2 Links and Currents................................................................................................... 8

2.3 Nodes and Voltages................................................................................................. 9

2.4 Devices.................................................................................................................... 9

2.5 A Network Topology............................................................................................... 9

2.6 Semidevices and Ports............................................................................................. 9

. Descriptive Remarks................................................................................................. 11


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. Some Important Devices and Some Examples........................................................... 15

4.1 One Terminal Devices........................................................................................... 15

4.2 Two Terminal Devices.......................................................................................... 15

4.2.1 The Current Source........................................................................................ 15

4.2.2 The Voltage Source........................................................................................ 17

4.2.3 The Resistor................................................................................................... 19

4.2.4 The Diode...................................................................................................... 21

4.2.5 The Inductor and the Capacitor...................................................................... 24

4.3 Three Terminal Devices........................................................................................ 26

4.3.1 The Silicon Bipolar Transistor...................................................................... 26

4.3.2 The MOSFET................................................................................................ 34

. Composite Devices.................................................................................................... 37

. Numbers of Equations and Independence of Equations.............................................. 41

6.1 The Essentials........................................................................................................ 41

6.2 Topology................................................................................................................ 42

6.2.1 Summary........................................................................................................ 42

6.2.2 Independence of the Current Balance Equations............................................ 42

6.2.3 Equation Counting.......................................................................................... 45

6.3 Devices.................................................................................................................. 47

6.3.1 Summary........................................................................................................ 56

. A Circuit Analysis Program....................................................................................... 57

7.1 Description............................................................................................................ 57

7.2 Example................................................................................................................. 60

. Estimating.................................................................................................................. 66


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0. ForewordI wrote this presentation of circuit analysis at the University of California, Riverside in 1972. I scanned it, reedited it, and filled it out m

998 and 1999.

This presentation was written and used to teach circuit analysis very quickly in a course on processor design for computer science stud

he students began with no background in electronics or circuits at all. They did have significant programming ability, and were rela

ophisticated in mathematics. The circuits unit was to bring these students to a level of sophistication in circuits so that they would be capable of d

DC analysis of a TTL or ECL gate circuit, with a number of transistors and diodes and any applied input voltage, by hand. Therefore they wou

ble to produce the Z shaped transfer function of such a gate by hand. They would also be able to analyze a 2 transistor flip flop by hand and to

hat it can be in 3 different states.

Perhaps more importantly, the students wrote a circuit analysis program that could do DC analysis on quite complex circuits containing vo

ources, current sources, resistors, diodes, and transistors. This program could analyze significant circuits with many states including many

ustaining states. Writing this program was an exercise in writing a complex application program. It was also proof that the students understood c

nalysis. If you can write a program to do it, you know how to do it.

Besides circuits, it was a goal that the students leave with a keen understanding of where circuit states come from at the lowest level of cir

ow these states become logic levels and how they become self sustaining states in latches and flip flops memory devices.

This circuits unit was just a part of the course. This course went on to examine how important logic families worked at the circuit level, a

ombinational logic design, design of registers, muxes, adders and other important structures, sequential logic design, and design of entire proce

with emphasis on the control logic.

The actual instruction in circuits took place in about 3 to 4 weeks. The project, writing a circuit analysis program, took quite a few more w

utside of class. Meanwhile the class moved on.

The challenge was how to bring a class from 0 to considerable sophistication with circuit analysis, including a solid understanding of

omplex circuit devices, in 3 or 4 weeks, about 10 classroom hours. The advantage that I had was that the students started out fairly sophisticat

mathematics and programming.

In the 3 or 4 weeks of instruction we did not cover all of the material in this paper. We were very brief on composite devices in section 5

id not touch section 6 at all. Indeed I make the point in section 6 that although this material may be interesting to some people, it is not actu

equired for almost anything you might want to do.

I learned circuit analysis at the University of Wisconsin in 1964 to 1965. I was taught several different complex and arcane methods for w

he equations for a circuit (e.g., loop equations, cut-set equations). These involved extracting the graph of the circuit, constructing the tree, etc.

aught from notes, Elementary Topology and Network Equilibrium Equations written at the University of Wisconsin. I have provided a co

hese notes together with this paper in my postings of this paper. It should be very interesting indeed to compare the approach in Eleme

opology and Network Equilibrium Equations with the approach in this paper. Elementary Topology and Network Equilibrium Equations

onventional way to write circuit equations. The only other known choice at the time was to write random loop equations. With random

quations, there is no effective procedure for getting a complete set of equations. That is why there was this arcane thing with trees and so forth.

The conventional way to write circuit equations was entirely too complex. I was also convinced that it was needlessly complex. If I h

each it this way, I would never be able to teach what I wanted in circuits in 3 to 4 weeks. It was also much, much too complex to write a ci

nalysis program with this conventional approach. Students would have little chance of success with their projects of writing a quite sophisti

ircuit analysis program if they were taught the conventional approach to writing circuit equations and told to go with it. I also believed tha

onventional approach was conceptually opaque. Students would not get what is really going on in circuits in a few weeks if they had to see ci

om the conventional vantage point.

I therefore developed the approach of this paper. To my knowledge, no one else has presented circuit analysis this way. There is no

cience in this presentation. Everything here is well known. But as far as I know, it is a completely new presentation and method of writing the c

quations.

I believe this paper is a superior presentation of circuit analysis compared to the conventional approach, which is exemplified in Eleme

opology and Network Equilibrium Equations. This is not picking on these notes in particular. These notes are very representative oonventional approach to writing circuit equations. They did a good job of presenting this conventional approach. You will see exactly the same

n an endless string of textbooks on circuit analysis.

In the conventional approach you never quite know if a resistor is some special thing that is intrinsic to circuit analysis itself, or if i

evice. Is Ohms law fundamental to circuit analysis, or is it a device characteristic? The approach of this paper makes it very, very clear w

evice is. No devices are special. You can use any devices you want. A resistor is a device just like any other device. Ohms law is a de

haracteristic. It is neither more nor less fundamental than any other device characteristic.

The conventional approach is entirely built around 2 terminal devices. There really is no provision in the circuit analysis itself for anythin

terminal devices. This follows directly from the conventional approach of having currents flowing through devices. If a current flows throu

evice, it is very hard to have that device be anything but 2 terminals. 3 terminal devices, like transistors, must be modeled in terms of 2 term

evices. Then there must be some extra equations thrown in in the form of dependent sources. You cannot model a 3 terminal device wit


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omething like dependent sources. I believe that the inability of the conventional approach to deal with atomic devices with anything other th

erminals is a significant disappointment. Further, I believe it is conceptually limiting.

In the presentation of this paper it is very natural to have atomic devices with any number of terminals. This paper presents and uses de

with 1, 2, 3 and 4 terminals. In this paper, quite unlike the conventional approach, currents flow in links which are ideal wires. (Note that the

link in this paper is used differently from the way the word link is used in the conventional approach.) Having currents in links frees devices

whatever they want to be. Links, of course, have to be two ended. But it is not limiting to have ideal wires be restricted to be two ended. I

resentation, 2 terminal devices are in no way any more legitimate or natural than devices with any other number of terminals.

The whole point of Elementary Topology and Network Equilibrium Equations is a complex way to get a complete set of indepen

quations. With the conventional approach, getting the right equations is a very big issue. If you do not get the right equations, it can lead to the w

onclusions. It is easy enough to not get the right equations, so there is this complex topology thing with trees, etc. just to have an effective methet the right equations.

By contrast, in the presentation of this paper, getting the right equations is essentially trivial. There is no issue about getting the right equa

here is no complex procedure required. There is one obvious current balance equation for each device, and then the device characteristics. Peri

that simple. These are always, even under extremely bizarre and pathological conditions, exactly the right equations from which you get the

onclusions.

There are cases in which the circuit equations should not be complete and independent. Such cases occur pretty frequently. Sinc

onventional approach is centered on a complex procedure to get complete and independent equations, it does not deal with these cases well. But

re real cases that are accurate models of circuits you can and do actually build. The presentation of this paper deals with cases in which there a

olutions or multiple solutions as being just as natural as when there is a unique solution. When there is no solution, there should not be a solutio

is exactly the correct description of what the circuit behavior is. If there are multiple solutions, there should be multiple solutions and this agai

orrect description of what the circuit behavior is. It is not generally appreciated how common these cases are because conventional circuit ana

oes not deal with them very well so they tend to be swept under the rug.

Although we did not get into it much in the limited time for circuit analysis in the course, and this paper is quite brief on it too, this app

eally provides a natural way to make composite devices; to determine their characteristics, and then to use them in circuits as devices tha

ompletely on a par with atomic devices.

From the method of writing circuit equations presented in this paper it is totally obvious how to write a program to form those equation

olve them. Section 7 describes the writing of a program in detail. This emphasizes how easy it is, but it should not be necessary. It is obvious.

The conventional approach to writing circuit equations is not pointless. The conventional approach results in a very small number of unkn

nd a comparably small number of equations. It was designed to do just that. These methods were developed at a time when the equations would

o be solved by hand, perhaps with a slide rule, or with a mechanical calculator at best. It was thought that it was important to get a small numb

quations with a small number of unknowns for such a hand solution. This is not unreasonable. If equations are written for the same circuit acco

o this paper there will be many more unknowns and many more equations. The few classical equations will be quite dense. The many more equ

ccording to this paper will be very sparse.

On the other hand, to really do hand analysis of typical circuits encountered everyday in design, one rarely writes out all the equations

olves them classically. The common circuits can be solved rapidly by hand without the formality of writing the equations out. The method by w

ne does this is illustrated in section 8. In fact, the way one can rapidly analyze complex circuits as illustrated in section 8 inspired the approach o

aper. As it turns out, really fast hand solution demands a large number of very sparse equations not a smaller number of dense equations. Kno

he method of this paper makes it easy to go to fast hand solution. By contrast, there is much less connection between the conventional approach

ense equations and fast hand solutions. For the few cases where fast methods dont help and there is no alternative to writing out the equation

olving them classically, it could be argued that dense equations with fewer unknowns is better. But today, one would not do such problems by

nyway; you would use a circuit analysis program.


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. Introduction

.1 Circuit AnalysisThis is a very modern approach to network analysis. It is strongly influenced by two factors. The first is the explosive growth in the comp

f systems in the last 15 years, which is certain to go on for the foreseeable future. The second is the increasing importance of computers in ne

nalysis.

In the beginning there was classical circuit analysis. There were the classic (mathematical) devices: the resistor, capacitor, and the indu

hese were THE passive linear components. There were a few other (mathematical) elements: the voltage source and the current source and for

who were really with it, the switch. These were the tube days. There were rather few real devices too: the physical realizations of the resistor, capa

nd inductor, and a few kinds of vacuum tubes and just a few others. For the purpose of analysis, vacuum tubes were represented by combinatioasic devices that have about the same properties (tube equivalent circuit).

Today systems often enough have thousands of components. There are also, a great many real devices. There are switching diodes, vo

eference diodes, current regulator diodes, tunnel diodes, variable capacitance diodes, thyrector diodes, and more, and these are just the diodes.

re also many kinds of transistors. New devices are appearing almost literally every day. If you consider integrated circuits, the possible varie

lmost limitless. It would seem that a more open-minded idea of what a device is in the mathematics of network analysis is indicated. The mo

end is to define a device in circuit analysis so that almost anything can be one. There are those (for example in the field called optimal con

ssentially doing network analysis wherein a typical component device is an entire computer.

The second big factor influencing the form of this presentation of circuit analysis is the computer. Now much of the network analysis t

ctually done is done by computer. A number of systems have been developed so that a circuit can be more or less drawn with a light pen on a gr

isplay device and the computer immediately analyzes it. The form that network analysis takes in this presentation is intended to be suitabl

mplementation on a computer.

.2 Describing CircuitsThe complete description of a network is broken into 2 parts. The first part is called network topology. The network is viewed as a bun

lack boxes (we don't ask what is in the boxes). Each black box has a number of terminals, and wires connect various of the terminals. In the ne

opology then, we are interested in how many black boxes (devices) there are, how many terminals each one has, and exactly which termina

onnected to which other terminals. In the second phase of network analysis we ask what the nature of each device is. We expect the answer to com

he form of the characteristics of the device. We still view the device as a black box and we still don't want to know what's inside but rather we

description of what it does. These characteristics come to us from other fields such as device physics with which we are not concerned in net

nalysis.

In network analysis we are doing mathematics and strictly speaking, everything we talk about is a mathematical object. I will define de

ke resistors purely in mathematical terms with no reference to any physical object at all. For most of the mathematical objects we define, phy

bjects with the same name exist. The mathematical object is frequently idealized to some degree, but its behavior models a real device well enou

e useful. Better and better models of a real device can be made but making such models is a discipline of study in itself. We associate the

omponents of a real circuit with mathematical devices that model them, usually of the same name, to get a model of the circuit.

One final remark before we begin is that the presentation will consist essentially of just definitions. The definitions will be presented i

yle of formal definition, theorem, proof mathematics with little text around them. There are some theorems that are unique to circuit analys

his presentation is mostly not about theorems. The mathematical objects used here are well known in mathematics. Once we have defined what w

oing, in a real sense, the theorems come from mathematics.


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2. Network Topology

2.1 TerminalsLet T be a set with a finite, nonzero number of members. If t is a member of T, then t is called a terminal. T is the set of terminals. Or, in

nglish: suppose I have a bunch of things I want to call terminals.

2.2 Links and CurrentsLet L be a collection of ordered pairs from T. L may be empty or have any possible ordered pairs in it. L is the set of Links. If l is a memb

, call l a link. Assume that for each link there is a real number. Precisely stated, let C be a function from L into the real numbers. The real nu

orresponding to any link is the current in that link.

A link is the mathematical object that represents a wire. This says suppose some terminals are connected by wires. A wire is describ

elling which two terminals it connects (thus the mathematical object, a link, can just be the pair of terminals). Now wires don't have any sp

irections - one way along a wire is the same as the other, but currents do go in directions. We arbitrarily assign a direction to the wire just so w

e able to talk about which way the current is going. We do this by saying a link is anorderedpair of terminals. That way we can say the curr

ositive if it goes from the first terminal to the second and negative if it happens to be going the opposite way.

Let la,b be a link from terminal a to terminal b. If Ia,b is the current in la,b then we say:

la,b contributes a current Ia,b into b.

la,b contributes a current Ia,b out of a.

For any terminal t, the current entering t is defined to be the sum of all the contributed currents into t minus the sum of all contributed cu

ut of t.

{To be absolutely correct, a link is anamedordered pair from T. Ifaandbare two real terminals in a real world circuit, it would be possi

onnect any number of wires between them. Since this is true in the real world, we would like to be able to represent this in the mathematical m

with any number of links between the mathematical terminals a and b. Strictly speaking, there can be no more than 2 ordered pairs of the termin

nd b and they would have to be (a, b) and (b, a). Every ordered pair containing a and b must be indistinguishable from one of these. But if we

ame, then there can be any number ofnamedordered pairs containing a and b, distinguishable by different names. This is an extremely minor

f very little practical value. It will be completely ignored in this paper except for section 6, which examines the effect of having more than 1

onnecting the same terminals.}

2.3 Nodes and VoltagesA set of all terminals connected by links is called a node. If there are any terminals not elements of links they are also nodes. Thus we se

he terminals are broken up into groups, each group called a node and each terminal is in one and only one node. Let N be the set of nodes.

Assume that there is a real number for each node. Precisely stated, let V be a function from N into the real numbers. The real nu

orresponding to any node is the voltage at that node.

We want to have voltages at each terminal but we want to make sure that if any two terminals are connected by wires, then they must hav

ame voltages. We do this by lumping together all the terminals that are joined by wires - they must all have the same voltage - and we call the b

f terminals a node. We then make voltages properties of the nodes.

We define the voltage at a terminal to be just the voltage of the node to which it belongs.

2.4 DevicesAssume now that D is a collection of disjoint, ordered subsets of T and that if t is a member of T, then t is a member of d for some d in D

lements, d, of D are called devices, and we observe that each terminal belongs to exactly one device.

The current entering a device is defined to be the sum of all currents entering all terminals of the device.

Each device is anorderedset of terminals. In general, different terminals of the device play different roles in the device characteristics thwith the device. This just means that we can tell which terminal on a device is which.

2.5 A Network TopologyIf we have sets T, L, D and functions C and V as described, and if the total current entering each device in D is zero, then (T, L, D, C,

alled a network topology.

2.6 Semidevices and PortsThere are just a couple more words that will be handy to have around:

If d is a device in a network topology and if S is a subset of d (that is S is some of the terminals in d) such that the sum of the currents en

ll the terminals in S = 0 then S is a semidevice. In particular, a semidevice consisting of exactly two terminals is called a port.

Devices that consist of exactly 2 ports are nice for many things. Not surprisingly, such a device is called a 2-port.


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3. Descriptive Remarks.The plan is to describe a real circuit by associating a network topology with it. The theory consists of saying that for any circuit there

uitable topology for describing it. Mostly, the network topology is just a way to talk about the terminals and which terminals are connected tog

ut there is one more very significant thing. There is this condition that in a network topology, the total current entering each device must be 0

may be viewed as expressing a physical law, conservation of charge. Every network topology must have all of its terminals be members of dev

We can immediately deduce that the total current entering all of the terminals of the entire network topology must also be 0. And now we

sserted that every physical circuit can be described (quite well) by a network topology.

Along with the topology comes a bunch of equations of the form

Ia+ Ib+ ... + Ic- Id- Ie... - If= 0

which express the fact that the total current entering each device must be zero. There will be one such equation for each device. The topology also

hat there must be a bunch of real numbers called voltages, one for each node, but it says nothing further about the voltages. Consequentl

quations involving the currents are the only restrictions on currents and voltages made by the topology.

One wants to also have descriptions of each of the devices in the network. In general, with each device there will be additional restrictio

he permissible choices of numbers for the currents and voltages. These restrictions are called the device characteristics. They may often take the

f one or more equations such as

Vi- Vj= RIi

Or of inequalities like

VjVi

When all the proper characteristics are combined with the topology, the result is a complete description of the circuit. The principle task of net

nalysis is then to find out exactly what choices of numbers for the currents and voltages are consistent with all restrictions (topology and d

haracteristics), if any.

There are 3 possibilities: 1. There are no choices of currents and voltages that are consistent with all restrictions; 2. There is exactly one u

et of voltages and currents that satisfy all restrictions; 3. There are many sets of currents and voltages that are consistent. I will say a few words

ach of these situations.

There may be no choice of currents and voltages which satisfies all restrictions. This is a situation similar to the case in algebra in simulta

near equations when the equations are "inconsistent". In fact, that is often exactly how this happens. There is perhaps a tendency to think of s

ase as abnormal. In fact in network analysis, this is a comparatively normal case and gives very useful information. It says DON'T DO IT!! M

ircuits can easily be built that result in descriptions with "no solutions". The analysis, in finding no voltages and currents that satisfy all requirem

telling you that the universe cannot exist in the state that you are describing. It is predicting the end of the universe if you construct this circu

eems in practice that some factor, not represented in the formal analysis, always intervenes to prevent destruction of the entire universe. Neverthf you insist on building the circuit you can expect in the worst case catastrophic failure of some of the devices, and in the best case the circuit

won't be useful.

It may be that there is a unique choice of currents and voltages that satisfy all restrictions. We are perhaps conditioned to think of th

ormal and desirable. In network analysis, this is extremely abnormal. In any cases we examine, it should not happen. The reason for this is tha

opology places no restrictions on the voltages - all restrictions on voltages come from device characteristics. All normal devices we will con

lace restrictions only on differences between voltages at pairs of nodes. Physicists have great confidence that it will never be possible to const

evice that can restrict voltages except in terms of differences between two voltages.

One can see that if one has a network (a network is considered to be a network topology along with all device characteristics) that h

olution (that is, there is a choice of currents and voltages satisfying all requirements) that in general, one can add a constant to all voltages and o

nother solution. This is so because all differences between pairs of voltages will remain the same. This is a very normal case. This is also equiv

o saying that there is one free parameter in the system or, stated still differently, one can choose any number at all for one of the voltages and

ill remains at least one choice of remaining voltages that produces a solution.In view of the fact that one voltage can be chosen arbitrarily, it has become customary to choose one node in a network and call it ground

rbitrarily dictates that the voltage at this node will be zero. The ground node is usually designated with the symbol:

It has further become customary to not explicitly draw the links connecting all the terminals of the ground node. Thus a network


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may be drawn

he ground symbol on a terminal means there is a link from that terminal to others of the ground node.

After arbitrarily dictating the voltage of the ground node, one is about equally likely to find that there is then a unique solution or m

olutions (assuming there is a solution at all). The job then is to list all the solutions or express them in some form.


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4. Some Important Devices and Some Examples.

4.1 One Terminal DevicesThere is only one reasonable one terminal device. It is called a tie point and it has no characteristics at all. Thus it places no further restric

n currents or voltages than just that required by the topology. Physically, the devices that correspond to tie points are just places where a numb

wires can be connected together and held, or splices in wires.

4.2 Two Terminal DevicesWhen one considers 2 terminal devices there is already a wealth of them. I will give a few.

.2.1 The Current Source

First, there is the current source. It's symbol and characteristics are:

where Iiis the current entering terminal t

i. I is the value of the current source. Physically, there are current regulator diodes that are well described

urrent source over a limited range of conditions. Otherwise current sources are generally made of a number of other components. Power supplie

ften be operated in "current regulating mode" in which case they are very well described as current sources. Current sources are very comm

synthesized" out of other components like transistors and resistors and appear as parts of circuits.

We will analyze two circuits as examples. The first is just the current source alone not connected to anything.

In the topology we see there are 2 terminals labeled t1and t

2. They form 2 nodes since they are not connected. There are no links. Consequ

here are no currents and the current entering terminal t1= 0. The current entering terminal t

2is 0 too. Topology requires that the current enterin

he current entering t2= 0, i.e., that the current entering the one device = 0. This is trivially satisfied. The device characteristic requires the cu

ntering terminal t1= I. Except in the special case where I = 0 this is inconsistent and there are no solutions. Current sources should not be "

ircuited"; they must always be connected to something.

Consider the second example:

ti

t1

tj

t2

Ii= I


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Again, there are two terminals, t1and t

2, belonging to the same one device. There is one link, l

1,2, from t

1to t

2. Consequently there is only one cu

,2. There is one node consisting of t

1and t

2. Consequently there is only one voltage V

1. The current entering t

1is -I

1,2and that entering t

2i

opology requires

-I1,2+ I1,2= 0

which is, of course, true for any value of I1,2

. The device characteristic requires

-I1,2= I.

here are therefore an infinite number of solutions all with the one current, I1,2

= -I, but with the one voltage V1being any number at all. This

tuation we talked about. If I now declare that the one node is ground, we have

r, as it might also appear

nd then there is a unique solution which is

V1= 0

I1,2= -I.

t2

t1 t2


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.2.2 The Voltage Source

The next 2-terminal device is the voltage source with the symbol and characteristics:

where Viand V

jare voltages at terminals t

iand t

j. V is the value of the voltage source. There are many devices that are well described by vo

ources: flashlight batteries, car batteries, the 115V wall receptacle and power supplies operated in their usual mode. Also, there are voltage reg

iodes called Zener diodes that are described well by voltage sources over a limited range of conditions.

We will also analyze 2 circuits with voltage sources. First consider:

he one device has two terminals. There are no links so there are no currents and there are 2 nodes. We have, therefore, 2 voltages, V1and V

2

opology contributes no restrictions since there are no currents. The device characteristic requires

V2- V1= V

here is an infinity of solutions. If we dictate that terminal 1 is ground then there is a unique solution

V1= 0

V2= V.

Next consider

ti

t1

tj

t2

Vj- Vi= V


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here is one link, l1,2

and one current, I1,2

. The current entering t1is -I

1,2and that entering t

2is I

1,2so the topology requires

-I1,2+ I1,2= 0

which is trivially satisfied. There is one node, since t1and t

2are joined by a link, and we call the voltage at this node V

1. The device characte

equires

V1- V1= V

ince the voltage at terminal 2 is defined to be the voltage of the node of which it is a part, it is V1. So is the voltage at terminal 1. Except f

pecial case V = 0 there can be no solutions. Don't short out car batteries, power supplies or the 115V wall receptacle. The existence of the univet stake!

.2.3 The Resistor

The next 2-terminal device is the resistor. Its symbol and characteristic are


iand V

iand V

jare the voltages at terminals t

iand t

j. R is the resistance of the resistor. Physically res

re bought as such. The degree to which this mathematical idealization describes a real resistor is particularly excellent.

ti tj

Vi- Vj= R Ii

t1 t2


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There is another number concerning the resistor above that is of interest. It is called the power dissipated. This number does not app

etwork analysis but it is of importance for considerations outside of network analysis. The power dissipated is:

RIi2

= (Vi- Vj) Ii= (Vi- Vj)2/ R

hysical resistors have a maximum power they can dissipate without being damaged or destroyed. They generate heat and the power dissipa

xactly the heat power generated.

Let us analyze one resistor circuit:

here are 3 devices containing 6 terminals. There are 3 links: l2,3

, l4,5

, l6,1

, and obviously 3 nodes we will call N1, N2, N4 (naming them afte

owest numbered terminal in the node). Consequently, there are 3 currents, I2,3

, I4,5

, I6,1

, and 3 voltages, V1, V

2, V

4. The topology requires th

otal current entering each device is zero:

I6,1- I2,3= 0

I2,3- I4,5= 0

I4,5- I6,1= 0

he device characteristics are:

V2- V1= V

V2- V4= I2,3R1

V4- V1= I4,5R2

n addition, we dictate that the node containing terminal 1 is ground so we have

V1= 0

Looking at the first 3 equations we immediately see that if there is any solution at all, all 3 currents must be equal. (As a point of interes

will also note that of these first 3 equations, which come from the topology, 1 equation, any one of them, is redundant. We could leave any o

hese 3 equations out and lose nothing.) From the rest of it we quickly get

V1= 0

V2= V

V4= V (R2/ (R1+ R2))


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I2,3= I4,5= I6,1= V / (R1+ R2)

his is the unique solution.

One further remark is that it is a little pedantic to go through this much work to analyze this simple circuit. With practice, much of it wou

one on sight. For example, it should be immediately obvious that all the currents are the same and so the first 3 equations would not even be w

own. With just a little experience, the whole circuit would be analyzed on sight.

.2.4 The Diode

The next 2-terminal device is the diode:


iand V

iand V

jare the voltages at terminals t

iand t

j. Notice that this device can exist in 2 distinct states.

Real silicon junction diodes are reasonably well described by this piecewise linear silicon junction diode. It does not describe germa

iodes which are rather little used now. Real diodes, however, have a maximum forward current and if it is exceeded the device can be dama

here is also a maximum value for Vj - Vi called the maximum reverse voltage. If this is exceeded, the diode will "breakdown".When diodes or other devices with multiple states are in the network the amount of work in the analysis can greatly increase. For a com

nalysis of a network with one diode, one would generally assume the diode is in the "ON STATE" and analyze using the on characteristics. T

may or may not be solutions. One would then assume the diode is in the off state and analyze using the off characteristics. Again, there may or

ot be solutions. One may find that there are solutions only when the diode is in one state or the other, or solutions in both states or none at all.

etwork contains, say 5 diodes, one would have to investigate 32 possible situations of various diodes in various states. The whole thing quickly

ut of hand. The only thing that saves us is that most of the possibilities can usually be discounted on sight.

There are two remarks that can be made about diodes:

The existence of two distinct states is very important. There are other devices with multiple states - some with more than 2 states. This

rigin of switching behavior in circuits. The performance of logic or switching circuits is directly traceable to these sorts of devices.

Secondly, there is the magic quantity 0.75 volts. This is the silicon junction diode forward voltage drop. The number also appears in si

ipolar transistor characteristics. It is not an absolute constant of nature. Various real diodes may show on voltages somewhat more or less tha

nd it also depends somewhat on the forward current. The piecewise linear model of the diode is an abstraction that is useful to model the quali

nd perhaps semiquantitative behavior of real silicon junction diodes. There are far more accurate nonlinear models which are required to get

uantitative results. These models describe a variation of the forward voltage with forward current, as well as with temperature, and manufact

rocess variables, and also a tiny reverse current when the diode has a negative Vi- V

j. The 0.75 volts in the piecewise linear model is rat

ypical, or rule of thumb number. It is, however, a very useful number that will come up again and again. Various notable voltages in devic

ircuits, especially logic circuits, are multiples of 0.75 volts. It is therefore sort of a basic unit or quantum of voltage at least in the bipolar world.

Let's analyze a diode circuit. For example

ti tj

ON STATE: Vi- Vj= 0.75 Volts

Ii 0

OFF STATE: Vi- Vj 0.75 Volts

Ii= 0


15/51

rom the topology:

I6,1- I2,3= 0

I2,3- I4,5= 0

I4,5- I6,1= 0

It will be noticed that these are exactly the same 3 equations we got from the topology for the 2 resistor circuit we analyzed. That is bec

he topology is the same. Only the characteristics of one of the devices have changed. R2 is here replaced by a diode. The resistor and diode bothterminals which is all the topology cares about. This being so, the conclusion is the same: all the currents are equal, which we should have kn

om sight. Let's just call the common value of these currents I.

The device characteristics are

V2- V1= 5

V2- V4= 1 X 103

I

+ diode characteristics

andV1= 0

Let us first assume the diode is off. In this state the diode characteristics are

V4- V1 0.75

I = 0

we quickly find

V2= V4

nd then

V2- V1 0.75

ut above we have V2- V

1= 5 and this certainly can never be! There is no solution with the diode off.

Let us now assume the diode is on. In this state the diode characteristics are

V4- V1= 0.75

I 0

Now we get

V1= 0(of course)


16/51

V2= 5 V

V4= 0.75 V

I = 4.25 ma.(milliamps)

nd with the indicated assumption that node 1 is ground, the solution is unique. There is, in this circuit, a solution only when the diode is on

herefore say that "the diode is on".

.2.5 The Inductor and the Capacitor

I would like to mention two other important 2-terminal devices, the inductor and the capacitor. In order to make sense of these devices a

evel of complication is required. Time is now involved. Speaking informally, what we want to do now is make the voltages and currents not num

ut functions. For each time t we want to have voltages V(t) and currents I(t).

In any event, we will assume for the next little while that the currents and voltages are, in general, time varying. Then the inductor is given

is required to be continuous and differentiable almost everywhere and

Vi(t) - Vj(t) = L Ii(t)

i means the derivative of I

i).

The Capacitor is given by:

Define VC= Vi- Vj. VCis required to be continuous and differentiable almost everywhere and

Ii(t) = C VC(t)

VC

means the derivative of VC

).

Physical inductors are basically coils of wire. The degree to which a real inductor is modeled by the mathematical inductor varies all the

om quite poorly to very well. This depends on the particular inductor. It also depends greatly on the nature of the rest of the circuit in which

sed. In general, the mathematical capacitor is a pretty good model of those on the market.

Apparently with the introduction of inductors and capacitors the restrictions on the currents and voltages become differential equations

arge and important fraction of the cases, the equations turn out to be linear. In this case, the idea of taking the Fourier or Laplace transfor

verything is popular. This leads to the concepts of frequency, impedance and all such. That process is called frequency domain analysis. If one

ot take transforms then he is doing time domain analysis. I will not pursue this part of the subject any further.

All real voltages and currents in real circuits take nonzero time to change values. The simple models of devices (other than the inducto

apacitor) given in this paper do not provide this. Capacitors and, to a lesser extent inductors, are frequently added to the simple models of

evices given here to produce composite devices (Section 5) that are better models of real devices. These improved models enable the networks

ti tj

ti tj


17/51

re in to model the temporal behavior of real circuits. It is also perfectly OK to define better atomic models that directly incorporate temporal beh

n the characteristics. This is done too.

4.3 Three Terminal Devices

.3.1 The Silicon Bipolar Transistor

A very important 3-terminal device is the Silicon Bipolar Transistor. It comes in 2 flavors: NPN and PNP. The NPN piecewise linear mod

OFF STATE: Ij= 0

Ik= 0

Vj- Vi 0.75 volts

Vj- Vk0.75 volts

ACTIVE STATE: Ij 0

Ik= b Ij

Vj- Vi= 0.75 volts

Vj- Vk0.75 volts

SATURATED STATE: Ij 0

Ikb Ij

Ii bRIj

Vj- Vi= 0.75 volts

Vj- Vk= 0.75 volts

REVERSE ACTIVE STATE: Ij 0

Ii= bRIj

Vj- Vk= 0.75 volts

Vj- Vi 0.75 volts

tk Collector

ti Emitter


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The PNP silicon transistor piecewise linear model is:

OFF STATE: Ij= 0

Ik= 0

Vj- Vi -0.75 volts

Vj- Vk-0.75 volts

ACTIVE STATE: Ij 0

Ik= b Ij

Vj- Vi= -0.75 volts

Vj

- Vk

-0.75 volts

SATURATED STATE: Ij 0

Ikb Ij

Ii bRIj

Vj- Vi= -0.75 volts

Vj- Vk= -0.75 volts

REVERSE ACTIVE STATE: Ij 0

Ii= bRIj

Vj- Vk= -0.75 volts

Vj- Vi -0.75 volts

The piecewise linear mathematical transistor is a remarkably adequate description of real silicon bipolar transistors in many cases. It m

he real transistor qualitatively very well, and semiquantitatively. There are more sophisticated nonlinear models that are required for acc

tk Collector

ti Emitter


19/51

uantitative modeling of real transistors. The magic number, 0.75 V. is the same magic number that is in the silicon junction diode piecewise

model. It is a rule of thumb number here just as it was there.

The Reverse Active state of the transistor is rarely used in practice. It is just like the active state but the functions of the emitter and col

re interchanged. In principle the transistor can work like this, but in manufacture it is optimized for the active state, not the reverse active s

he transistor will break down and can be damaged if the voltages, Vj- V

iand V

j- V

kare too low in the NPN case, or too high in the PNP

his is reverse voltage breakdown. The emitter reverse voltage breakdown generally happens at a very small reverse voltage of perhaps 2 V. o

with the appropriate sign) in Vj

- Vi. Generally the collector reverse breakdown voltage is very much higher. This is one of the reasons wh

Reverse Active State is generally regarded as not very useful. The other 3 states: cutoff, active and saturated, are all useful states and de

outinely use all of these states.

It can be seen that the transistor is characterized by two parameters (which conveniently turn out to be dimensionless): b, bR

, Beta

Reverse Beta. Transistor manufacturers will almost never specify Reverse Beta, and almost never test it. This is in keeping with the view th

everse Active state is not very useful. bR

also appears in the Saturate State characteristics in an inequality that describes the boundary betwee

aturated State and the Reverse Active State. In most practical cases it would be good enough to simply use 0 for bR

. This would make a part o

ange of the Saturated State unavailable, namely that part where the emitter current is reversed. This is usually not a very useful part of the satu

ate. In any event, we will usually not have any good number for bR

. For most practical purposes b is the one and only parameter for the piece

near silicon bipolar transistor.

The beta of a small signal audio preamplifier transistor may be 250-1000. Power transistors and switching transistors normally have l

etas like 25-150. The transistor betais not a "well controlled parameter". Different units from the same manufacturer and with the same type nu

may have much different betas. The parameter also depends on temperature and other factors. Consequently, it is poor design practice to mak

erformance of a circuit depend on the betas of the transistors. Techniques for making circuit performance depend mainly on resistor value

xample, and be almost independent of betas, are highly developed.

Just for information, bR

for a transistor is typically less than b by a factor of 10 to 50. A transistor with a b of 250 - 1000 could well have

f 5 to 50. But, as we said, bR

is usually unspecified.

One example transistor circuit will be analyzed in complete detail:

rom the topology we have

I10,11- I1,2= 0


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I1,2- I3,4= 0

I3,4- I5,6+ I9,10- I10,11= 0

I5,6- I7,8= 0

I7,8- I9,10= 0

om which we immediately deduce

I1,2

= I3,4

= I10,11

I5,6= I7,8= I9,10

hus there are two significant currents which we can take to be I3,4

and I5,6

. The ground node identification gives

V9= 0

The device characteristics are

V1- V9= VIN

V1- V3= R1I3,4

V5- V7= R2I5,6

V7- V9= VPWR

+ transistor characteristics.

We can deduce that

V1= VIN

V7= VPWR

V3= VIN- R1I3,4

V5= VPWR+ R2I5,6

A. Assume the transistor is off.

I3,4= 0

I5,6= 0

V3 .75

V3- V5 .75

We then find

V3= VIN

V5= VPWR

VIN .75

VIN- VPWR.75


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In the usual application of such a circuit VPWR

is positive and VPWR

VIN

. VPWR

, in fact, would normally be the "power supply". In tha

VIN

- VPWR

.75 is always satisfied. We then learn that the transistor will be cutoff if the "input voltage", VIN

, is less than .75 V., and under

onditions, the "output voltage", V5, = V

PWR, the "power supply voltage".

B. Assume the transistor is active

I3,4 0

-I5,6= b I3,4

V3= .75

V3- V5 .75

We find

I3,4= (VIN- .75) / R1

V5= VPWR- R2b (VIN- .75) / R1

VIN .75

VIN .75 + VPWRR1/ (b R2)

he transistor will be active if the "input voltage", VIN

, is between

.75 volts

and .75 + VPWRR1/ (b R2) volts.

n this case the "output voltage", V5, is

VPWR- b (VIN- .75) R2/ R1

Notice that the "output voltage" depends on b. It would be a poor design practice to use this circuit in the active state.

C. Suppose the transistor is Saturated.

I3,4 0

-I5,6 b I3,4

I5,6- I3,4 0

V3= .75

V3- V5= .75

Here I have said it is good enough to just use 0 for bR

. We can then find

V5= 0

I3,4= (VIN- .75) / R1

VIN .75

VIN .75 + VPWRR1/ (b R2)

VIN .75 - VPWRR1/ R2


22/51


23/51


24/51


25/51

Vj - Vk VT

Ij= 0

R Ik= Vj- Vi- VT

SATURATED STATE: Vj- Vi< VT

Vj- Vk< VT

Ij= 0

R Ik= Vk- Vi


26/51

5. Composite DevicesModern networks may often contain thousands or even millions of devices (consider a modern large scale computing system). The conce

roblem of dealing with any system consisting of so many parts is staggering. A better approach is to invent new devices that are built fr

manageable number of previously known devices - and then still bigger devices composed of a manageable number of the previously inv

omposites. This process can be continued indefinitely. One can then analyze all networks (even entire computer systems) in terms of a m

easonable number of pieces.

In this presentation of network analysis, the idea of a device is fundamental. In addition, there are practically no restrictions on what can

evice. All that is necessary is that the characteristics of the device be known. In particular, any combination of other devices can be defined

ertain of the terminals be designated as "externally available", and then if the characteristic can be found, this composite can be considered a d

rom then on, one need never be concerned with the internal details of the composite device - the characteristic is sufficient information.

Now the characteristic of a device is exactly the set of restrictions that are placed on the possible set of solutions to any network that con

he device. The other devices in the network may have characteristics, but if so, this only reduces the number of possible solutions still further. I

ase, the solution set for the network will be a subset of the possible solutions that are permitted by the characteristics of any one device.

Suppose that a network contains a composite device with some characteristics and all the other devices have no characteristics at all.

etwork will have the largest solution set of any network containing the composite. In fact, the solution set of this network is just a way of expre

he characteristics of the composite itself.

This gives a method for finding the characteristic of a composite. Make a complete network by connecting all the "externally avail

erminals of the composite to a device with the required number of terminals (device X). Device X should itself have no characteristics at a

ence, be completely general. Device X represents the collection of all the other devices in any network that contains the composite. Any networ

ontains the composite would differ from this at most by the addition of more characteristics and hence, would have a smaller solution set

etwork containing a composite and device X is a complete network and therefore, can be analyzed in the usual way. Its solution set is exactl

haracteristics of the composite.

For example, consider the composite device consisting of two resistors in series:

and tjare "externally available". t

mand t

kare not externally available.

To find the characteristics of the composite, connect it to device X which has two terminals and no characteristics.


27/51


28/51

Vi- Vj= Ii(R1+ R2)

his composite has exactly the same characteristic as a single resistor of value R1 + R2.

It could well be said that the elimination of internal voltages and currents from the composite device characteristics represents the whole

f making a composite device. If you cant eliminate any internal variables, you gain nothing. This is the only way that a network containin

omposite gets to be any simpler than that network with all the stuff that the composite is made of exposed.

There may be cases in which the internal currents and voltages cannot be expressed in terms of the external variables. This could be be

here is no solution to the test network made with device X, or it could be for other reasons. If the test network has no solutions, then any net

ontaining this composite cannot have any solutions. The composite device itself is internally contradictory. If there are other reasons that

nternal variable cannot be expressed in terms of external variables only, then this internal variable cannot be eliminated from the rest of the equan this case, the internal variable that cannot be eliminated is state internal to the composite device. This state may appear in its characteristics.


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6. Numbers of Equations and Independence of Equations

6.1 The EssentialsFor almost all practical purposes, including even writing a program to do circuit analysis, even a quite sophisticated circuit analysis pro

what you need to know is this:

Write one equation for each device that says the total current entering that device is 0. One of these equations will be redundant. Which

Any one. Pick any one of these current balance equations arbitrarily and throw it away. Add an equation that fixes the voltage of 1 arbitrarily c

or maybe predesignated) node at any arbitrary value (0 if that was defined in the network). For each state of all devices, add the device characte

quations for all devices. These are exactly the equations that you want for this network in this state.

If the equations are inconsistent, then they are supposed to be inconsistent. There will then be no solution in this state, and there shouldno

olution in this state.

If the equations are redundant, then they are supposed to be redundant. It is also possible that there may be fewer equations than unkn

voltages and currents). This happens only for multiply connected networks, which you may consider real odd balls. But, if this is so, then

upposed to be so. In either of these 2 cases, if there is a solution in this state, there will be an infinite set of solutions in this state. There truly ar

arameters for this network. You may then be able to add arbitrary conditions such as fixing certain voltages or certain currents, and arrive at a u

olution.

Whatever you get with these equations, it is absolutely notthe case that you have somehow not picked the right equations, and if yo

een smart enough to pick the right equations, they would be independent. You have the right equations and they are telling you the truth.

Or, you may find that the equations are independent and consistent and there are just as many equations as unknowns (voltages and curr

hen, if all the devices are piecewise linear devices, so the equations are all linear, there will be a unique solution. If there are nonlinear equations

perfectly OK, but it is much harder to say anything in general about the uniqueness of solutions.

The rest of this section goes into this in more depth. There is no need to look at this in more depth for almost all practical purposes. If yo

ot particularly interested in all the nitty gritty, I suggest you skip the rest of this section. In the event that you really are interested and want to s

he dirty laundry, then please enjoy it.

6.2 Topology

.2.1 Summary

Suppose we have a network topology with T terminals, D devices, and L links. In the following we will show that, under reaso

onditions, there will be N = T-L nodes. You can see this easily by just thinking about adding links one by one to a bunch of terminals. (U

easonable conditions) each link you add connects another terminal to an existing node, where you can consider a single terminal to be an ex

ode. To begin with, we have N nodes each starting out with one terminal. The L links use up L terminals connecting them to the N nodes, so T

L.

From this we can see that we will have L unknown currents and N unknown voltages for a total of L+N = T total unknowns.

The topology gives us D current balance equations. One of them is redundant (any one of them). So we through away one equation pi

rbitrarily. But, we add one equation that says that the voltage of some arbitrary node is some value, for example 0. We still have D equation

eneral, a device with u terminals will have u-1 equations in each state in its characteristics. Each device then has 1 terminal that gets it no equa

ut each terminal after that gets it an equation. So there are D terminals that did not get us any equations. All of the rest of the terminals g

quations. So there are T-D device characteristic equations in each state.

The topology plus picking a node to call ground got us D equations. There are T-D equations from device characteristics. The total equ

ount is T. It is, of course, very fortunate that, at least under reasonable conditions, we get exactly the same number of equations in each state as

re unknowns.

Under reasonable conditions there is one unknown and 1 equation for each terminal.

The work to follow determines exactly what are these reasonable conditions under which this happens, and exactly what happens undo reasonable conditions. Then there is the very big question of whether these equations are independent or not. We already know the an

ometimes they are and sometimes they are not. They are independent when they should be and they are dependent when they should be. We

hat it is certainly not a matter of doing a poor job of picking the equations. These are the right equations, giving us the right message. There

etter choice of equations. Here we try to get much more specific and more detailed about what is going on when the equations are not indepen

xactly what does it mean and how do we get useful results.

.2.2 Independence of the Current Balance Equations

We define that all of the terminals that belong to a single device areconnected. We also define that if there is a link from terminal a to ter

, then terminals a and b are connected. Next we define that if terminal a is connected to terminal b and terminal b is connected to terminal c,

erminals a and c are connected. Thus if you can get from terminal a to terminal b by any path from terminal to terminal that either goes throu

evice or through a link, then terminals a and b are connected.


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Define that a Network Topology, N, is fully connectedif every terminal in N is connected to every other terminal in N.

If a Network Topology, N, is not fully connected, then the devices can be put in mutually exclusive groups such that each group of devi

ully connected within the group. In fact, there is a unique way to do this such that no terminal in one group of devices is connected to any termi

nother group of devices. These groups of devices are totally isolated from each other. We may call these groups Subnetworks. A subnetwork is

ully connected within itself and not connected to any other subnetwork of the network Topology.

Theorem: If a Network Topology, N, has d devices in it, then we get d equations that express that for each of the d devices, the total cu

ntering that device is 0. Equation x for device X, is a linear combination of the equations for the other devices in the same subnetwork as device

Proof: Suppose we wrote all of the equations that say the sum of the currents entering device d is zero, for all of the devices in a subnetwo

We want to look carefully at what this list of equations looks like.

Each link L has a current ILthat goes from some terminal, t, on some device in S to some terminal, u, on some device in S. Terminals t

must be in S because there is no connection from any device in S to anything outside of S. L contributes a current out of one terminal, t, and int

erminal, u. L therefore causes exactly 2 terms to appear somewhere in the list of equations. The equation for the device containing terminal t g

erm -IL

and the equation for the device containing terminal u gets a term IL.

It is possible that terminals t and u are in the same device; it is even possible that terminals t and u are the same terminal. If t and u are i

ame device, then the terms ILand I

Lgo in the same equation where they cancel each other out and both disappear. If t and u are in different de

hen the termsILand I

Lgo in different equations. Either there will be no term involving I

Lin any form, includingI

L, or else a term involving I

L

ppear exactly twice in the whole list of equations, once asILand once as I

L. It will be so for every link in the subnetwork S.

We can conclude from this that if we add all of the equations, one for each device in S, what we get is 0 = 0. The right hand side of all o

quations is 0, to that clearly adds up to 0. On the left-hand side, for each term, I

L

, an exactly matching term, -I

L

, occurs somewhere in the

ancel it out.

Now suppose that in the list of equations, one for each device in S, we pick any equation. Lets call it e. Suppose we add up all of the

quations except e. We must get exactly -e. We know that because if we now add e in as well, we get 0 = 0, as we just showed. Hence, equatio

xactly minus the sum of all the other equations. This shows equation e is a linear combination of the current balance equations for the other devi

.

Theorem: If a Network Topology, N, has d devices in it, then we get d equations that express that for each of the d devices, the total cu

ntering that device is 0. Let Q be the list of such equations for a subnetwork, S, of N. Pick any equation, e, in Q. Let P be the list of equations Q

removed. All equations in the list P are linearly independent.

Proof: Suppose the theorem is not true. Then there is an equation, x, in P which is a linear combination of a set of other equations, R, in P

an then say that a linear combination of the equations R together with x exists that is 0 = 0, no matter what the values of any of the link current

N be the set of equations in Q which are not x, and not in R. There is at least one equation in N: e. There may or may not be any other equations in

Consider the set of devices, D, that correspond with the equation, x, and the list of equations, R. I claim that there could not be any link fr

o E, where E is the set of devices corresponding to the equations N. Suppose there was such a link, L. Then a term involving IL

must occur ex

nce somewhere in the equations, R, or equation x. It may have a + or - sign but it would appear just once. The other matching term involvi

would appear in the equations, N, with some sign. By assumption, a linear combination of equations R and x is 0 = 0, and there is a non

oefficient in front of each equation, R and x. There could be no way to make this single occurrence of ILgo away. These equations could not sum

0. Hence there must be no link connecting the non-empty set of devices E and the non-empty set of devices D in S. But S is a subnetwork an

herefore fully connected. It cannot have devices D and E in it that are not connected. We must conclude that the assumption that the theorem is

incorrect and in fact the theorem is true.

If a bunch of devices are connected together and we single out any device, we can ask what is the total current entering this device? Curr

link is always flowing from somewhere to somewhere else. It cannot go into one device without coming out of another. So the answer is th

otal current entering this device is the same as the total current leaving all the other devices. If we have already said that the total current leavi

he other devices is 0 (because the total current leaving each one of them individually is 0), this implies that the total current entering the sel

evice is 0. It is then redundant to say that again. So it makes sense.

This tells us that when we write the equations, one for each device, that says that the total current entering that device is 0, we can al

rbitrarily pick any one of those equations and leave it out.

If it turns out that the network is not fully connected, you can arbitrarily pick one equation from each subnetwork and leave it out. It is

air. A network with 2 subnetworks is exactly like two completely separate networks that you might write equations for separately and

eparately. If you did the 2 subnetworks as two completely separate problems, in each problem you could leave out 1 equation. So if you choose

hem both together you can also leave out 2 equations.

If a Network topology is not fully connected, we will find that we can pick the voltage on one node arbitrarily in each subnetwork. Ther

e no restrictions on the voltages except on the differences between voltages of nodes in the same subnetwork.


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.2.3 Equation Counting

Let N be a node in a Network Topology. We say node N is Simply Connectedif there is no link that could be removed and still have all

erminals of N connected by links. If N is not simply connected then we say N isMultiply Connected. If every node in a Network Topology is s

onnected, then we say that the Network topology is simply connected. If one or more nodes are multiply connected, then the Network Topolo

multiply connected.

If N is multiply connected then there is more than one route one could take along links to get from some terminal, t, to some terminal, u,

ince this is true, there is a closed loop somewhere following links among the terminals in N. In a degenerate case, a link may connect a termina

self. This makes the node containing t multiply connected. The node containing t might also contain other terminals or it could just contain t.

In a multiply connected node, since there is more than one route from some terminal, t, to some terminal, u, some of the current from

akes one route and some takes another route. Circuit analysis will have nothing to say about how much goes one way and how much goes the way. All of the equations of the topology only involve the total current from t to u. Even the device characteristics of any device cannot tell by w

oute the current arrives; they involve only the total current entering a terminal. If we have a set of currents that satisfies the Network, then we

ubtract any current from the current along one path and add it to the other and we still have a solution. In fact, there can be an arbitrary amou

urrent circulating in the loop of links.

This does happen in physical reality. In actual, physical circuits, there are sometimes redundant wires, sometimes put there intentionall

arious reasons, and sometimes by accident. There can be very good reasons (that are beyond the scope of this paper) for having redu

onnections. In the cases where this does happen, in fact, it is not known how much of the current takes one path or the other. In actual fact ther

e arbitrary currents circulating around the closed loop. We can get this under control by actually modeling the wires as devices rather than a

nks. If the wires are accurately modeled as devices, circuit analysis can tell us how much current is going one way or the other and even how

urrent is circulating.

Suppose we have a Network Topology with T terminals, D devices and L links. We already know that there are L unknown currents, o

ach link. We would like to know how many nodes there are because that will tell us how many unknown Voltages there are.

Think of starting with T terminals and no links so that each terminal is a node. There are therefore T nodes. Now add links one by one. I

hat if the network will be simply connected, then I can add links in such a way that each time I add a link, a single terminal is joined to some o

ode. This means that that single terminal is no longer a node by itself. Hence with each added link, the number of nodes is decreased by 1. Whe

re finished, we must have

N = T - L

It remains to show that links can be added in such as way that each link joins a single terminal to some other node.

First, partition the T terminals into groups that will be the nodes. Within each group, we will have a set of terminals at each time, which w

he growing node. All terminals in the growing node are connected by links. Initially pick any arbitrary terminal in each group and let that b

rowing node for the group. Now we add a link.

I must always be able to choose to add a link that connects to the growing node. If that was not possible then there are no links that connec

rowing node. This means there is no link that connects the remaining terminals in this group to the growing node. This group cannot form a

hen, since not all terminals are connected. But, by assumption, this group will form a node. Hence, it must be true that I can choose to add a lin

onnects to the growing node.

The other end of this link cannot connect to the growing node. This is because all terminals in the growing node are already connected. If

link that connects from the growing node to the growing node, then the growing node will be multiply connected. This means the finished nod

his group becomes will be multiply connected, contrary to assumptions that this network is simply connected. The link I add therefore connec

rowing node with some terminal that is not yet part of the growing node. The only other terminals in the group are single, unconnected termina

his link will cause 1 single unconnected terminal to be added to the growing node.

Observe that there are then N unknown voltages and L unknown currents. The total number of unknown variables is N + L which is exac

n a simply connected Network topology.

If the Network topology is not simply connected, the number of unknowns, N + L, will be greater than T. Consider the argument above

dd a link that connects to a growing node. But one or more such links now connect from the growing node back to the growing node. Such a link

ot add a new terminal to the growing node. This means that we will have to add an additional link to use up all the terminals in the group.

etwork was simply connected L = T N. If the network is multiply connected it will take more links so L > T N.

If the network is simply connected the number of unknowns, L + N, is T. If the network is multiply connected the number of unknown, L

more than T.

Now, how many equations do we have? The Topology gives us one current balance equation for each device. We therefore have D equa

We know they are not all independent. Even in a fully connected network, one is redundant, so we have D-1. If the network is not fully conne

hen there are even fewer independent equations. In fact if the network has S subnetworks, then we have D-S independent current balance equatio

ully connected network consists of exactly 1 subnetwork so S is 1, in this case.


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We assert that we can arbitrarily dictate the voltage of S nodes. This represents S more equations (very simple equations to be sure). If w

his, then we again have D independent equations from the Topology. Now it is up to the devices.

6.3 DevicesA fully defined, piecewise linear device with t terminals will have t-1 device characteristic equations in each state, not counting inequa

which serve to determine which states are possible. The Tie Point, a 1 terminal device, had no characteristics. The two terminal devices all ha

quation in each state, the three terminal devices, the transistors, had 2 equations in each state.

Go back to our Network Topology with D devices, and T terminals. All of the terminals belong to some device. We get one equation with

erminal, but for each device, we get shorted by one. The total piecewise linear device characteristic equations are

T - D

There were D independent equations from the Topology + ground reference choices. The total is therefore T. Conveniently there are a

nknown voltages and currents, if the network is simply connected. If the network is multiply connected, then there are more than T unknown

here are not enough equations to go around. But, as we said, if the network is simply connected then we have T unknowns and T equations.

Ah, but are the device characteristic equations all independent, and independent of the equations from the Topology?

A device is defined to be internally disconnectedif one or more of the equations that constitute its characteristics express that the total cu

ntering some subset of its terminals is zero. It must be possible to show that the total current entering this subset of terminals is 0 from

haracteristics alone, not using the current balance equation for the device from the topology.

An internally disconnected device has characteristics that demand that a subset of its terminals forms a semidevice. Note that we may fin

ertain terminals of a device form a semidevice in certain circuits by virtue of the circuit. This does not make the device internally disconnected.

nternally disconnected, the characteristics of the device itself must make a subset of its terminals a semidevice independent of what circuit it is

n.

We have already seen a trivial example of an internally disconnected device: the MOSFET. In each state, one of the equations

haracteristics is that the gate current is zero. Technically this makes it an internally disconnected device. As a practical matter though, a semid

onsisting of 1 terminal is not very interesting.

A better example is a new device called the Ideal Transformer. The ideal transformer is a model of physical transformers. A ph

ansformer is a fundamental device in that it is not made out of parts that are circuit devices. The Ideal Transformers symbol and characteristics

The single parameter, N, is called the turns ratio. It can be any real number, positive or negative or 0. A turns ratio of 0 is a degenerate

f limited interest. Notice that it has 4 terminals and, as expected, 3 equations in its characteristics.

Ij= - Ii

N Il= - Ij

Vl

Vk

= N (Vj

Vi

)


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The characteristics directly define that one pair of terminals, (ti, t

j), will be a port, i.e. the total current entering terminal i and terminal j

When the transformer is used in any network, including the trivial network that contains it alone and nothing else, the topology will demand th

otal current entering the ideal transformer is 0. This will imply that the other pair of terminals also forms a port. The ideal transformer is therefo

ort, enforced by its own characteristics.

There are other fundamental devices that are internally disconnected. In addition, a composite device can be internally disconnected. Th

appen if the composite device contains an internally disconnected device, or if it is a network topology that is not fully connected, as we defin

he beginning of this section.

It may also be noted that devices can become internally disconnected sort of by accident. For example an ideal current source is normal

nternally disconnected but if its strength just happens to be 0, then it is internally disconnected. All of the transistors are internally disconnected

utoff state. The diode is internally disconnected in the off state.

Lets use the ideal transformer as our example of an internally disconnected device, and see how it might be used in a network. The transfo

ould be used in a network like this

n this case, all of the devices in the network besides the transformer have been put into 2 groups. Group of devices A is connected to one port

ansformer and group of devices B is connected to the other port of the transformer. Anything you want can be in group of devices A or grou

evices B. It is important in this example that there is no connection whatever from group of devices A to group of devices B, except by virt

hem being connected to the transformer. There is no connection between one port on the transformer and the other port on the transformer ex

whatever is internal to the transformer itself.

In this example, one of the equations of the transformer characteristics will say that the current entering the first port must be 0. The toprovides a current balance equation for each device in group A. The effect of all of those current balance equations is also to require that the

urrent entering the first port of the transformer is 0. This is because the total current entering all of the devices of group A must be exactly the

urrent leaving the transformer port to which they are attached, since they are not connected to anything else. Then if one is 0, the other must

his shows that the equation in the transformer characteristic that says the current entering the first port is 0 is redundant with the equations fro

opology for the devices in group A. And we still have for the whole network, that one of the current balance equations is redundant besides,

sual.

Suppose we write the equations for this network as we usually do. From the topology we write one equation for each device stating tha

otal current entering that device is 0. We know that one of these equations is redundant. In usual fashion, we pick one of these equations arbitr

nd throw it away. In usual fashion we pick one node arbitrarily and we write 1 equation that arbitrarily fixes the voltage of that node. Then we a

f the equations of the device characteristics in some particular state of the whole system. If T is the number of terminals, the total number of cu


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nd voltage unknowns is T. We also now have T equations. These equations are, however, redundant as we just saw from the previous paragraph

olution to the equations (if any) will not be unique. In fact, in the case being considered, there will be one free variable. It will be a voltage.

In this case, it will be possible to arbitrarily dictate the voltages of not just 1 node, as we usually do, but 2 nodes. You can arbitrarily pic

ode on the left including in the group of devices A, or the first port of the transformer, and dictate that it shall be any arbitrary voltage. Then you

ick an arbitrary node on the right including in the group of devices B or the second port of the transformer, and dictate that it shall be any arb

oltage. If the rest of the network is reasonably normal then we can get a unique solution (at least in states for which there are any solutions).

In effect, the internally disconnected device, the transformer, has split this network into 2 disconnected pieces even though, in the topolo

ense, this is a fully connected network. It would be clear that this is happening if, instead of the transformer, we had a composite device there

was internally disconnected because it was itself a network that is not fully connected, and we could see inside the device to see that.

The transformer does this disconnection in a very nice way. The left and right sides of the network still greatly influence each otheroltage across one port of the transformer determines the voltage across the other port. The current passing through one port determines the cu

assing through the other port. But it is disconnected in the sense that everything on the left, for example, may be within a few volts of 0,

verything on the right may be within a few volts of 10,000 volts.

A transformer is sometimes used exactly for the purpose of dividing the network so that there is an arbitrary voltage on each side, exact

appened in this example. For this use, it is crucial that the transformer is internally disconnected and that is what makes it useful. A transform

lso frequently used for other purposes and it doesnt really matter if it is internally disconnected or not.

Now lets consider a slight variation on the previous network. Here we see the same network with all the same devices, but we have ad

more link that was not in the previous network. This link connects one terminal of the first port of the transformer to one terminal of the second p

he transformer.

Now the network topology equations that say that the total current entering all the devices in group A is 0 are not saying the total cu

eaving the first port of the transformer is 0. There is another place for that current to go: the link we added. We will now find that the equation

deal transformers characteristics that says that the total current e

ln-1.3.1-introduction to electronic circuit analysis

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