low power cmos digital circuit design methodologies with reduced voltage swing

8/14/2019 Low Power CMOS Digital Circuit Design Methodologies With Reduced Voltage Swing

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Low Power CMOS Digital Circuit Design Methodologies with Reduced Voltage SwingT.S. Cheung, K. Asada

Department of Electronic Engineering,University of Tokyo, Jap an.

K.L. Yip, H. Wong, Y.C. ChengDepartment of Electronic Engineering,

City University of Hong Kong, Hong Kong.

AbstractIn this paper, two techniques on low power circuit design,namely, Clock Separated Logic and Sub-Vdd Voltage-swingInterfacing, are introduced. In the former method, reducedvoltage-swing at in ternal nodes is used to achieve relativelylow power dissipation as compared to circuits with fullvoltage-swing. In the lat ter method, pass-transistor logicwith suppressed internal voltage-swing is used to reducepower dissipation on pass-transistor chain. Basic techniqueson design of these circuits are investigated and analyzed.

1 IntroductionA s clock ra te of circuits and systems increases year by year,power consumption has become an important considerationin circuit design. Power reduction on process technology,architecture design, and circuit design had become moreand more imp ort ant for portable low power electronic equip-ments. CMOS had its largest market share in the last decadeand in early 90s. However, there is serious increase in gat edelay as operating voltage is reduced to 2V or less [l].Onthe other hand, pass-transistor logics had become one of themost attractive logic families, from a view point of powerconsumption [2]. I n addition, another new approach on com-binational logic architecture had suggested the reduction ofoperati ng power by suppressing the signal swing to less than1V[3]. As a result, pass-transistor logic is one of the mostpromising logic families on low power consumption.

Furthermore, internal signal propagation with voltageswing less than supply voltage have been proposed throughvarious architecture or structures.

In cocerning power consumption of circuits, dynamicpower is considered t o be main portion [4]. Equation ofthe estimation of the dynamic power is :

where Vsw(i) is the voltage swing at node i,ci is the capacitance a t node i, andf i is the frequency of voltage switching at node i.The choice of Vdd is always considered to be Vdd = 3Kmcn.However, in pass-transistor logic, to account for the drop ofone threshold voltage, Vt, in the transversal transi stors, th echoice of Vdd should be Vdd = 4Xmcn.

Reduction in supply voltage is one of the most importanttrend in low power digital design[5]. However, a decreasein the supply voltage will bring about various circuit designproblems: drivabili ty of MOSTS will decrease, signals willbecome smaller, and the threshold voltage variation will bemore limiting. One method in achieving power-off strategiesis the introduction of the dual-rail coding, or the comple-mentary coding logics, which is implicit in certain logic fam-ilies such as the DCVSL[G]. However, the dual-rail DCVSLf&mily consumes at least twice more in energy per inp ut0-7803-2624-5/95/$4.00 @ 1995 IEEE

transition tha n a converntional sta tic family[7]. Another at-tractive logic family is the complementary pass-transistorlogic (CPL)[8] [2].

The concept of hyper design domain is introduced in Fig.1. In traditional digital design, voltage-swing and supplyvoltage are always kept constant . Thi s design methodologywill certainly lead to a limit in achieving low-power or high-speed design. However, if more th an one voltage-swing valueor transistor threshold voltage is chosen, new domain in de-sign can be explored. In this paper, two of the emergingtechniques based on the concept of hyper design domain,namely, Clock Separated Logic and Sub-Vdd Voltage-swingInterfacing, are introduced.

2 Clock Separated Logic (CSL)A Clock Separated Dynamic D-type flipflop (CSL-DFF)aims for low power logic circuit design is proposed [9]. Thefan-in of clock signal, Ck, at t he CSL-DFF is only connectedto 4 transistors instead of 8 in complex-gate-DFF (Fig. 2 ) .Low power consumption can be obtained by reducing volt-age swing at both internal signal nodes and driving clock.Calculation and simulation result showed that a choice ofaspec t ratio of 10 on PMOS and 5 on nMOS would result inan average reduction of consumption power of about 5 0 per-cents using st andard 1.Optm gate l ength CMOS technology.The proposed circuit gives an average reduction of consump-tion power of about 30 percents as compared to complex-gatest at ic D-type Flip-flop while giving a 20-percent of improve-ment on clock-to-output propagation delay[9]. According toanalysis on the circuit of CSL-DFF, the longest propagationdelay [9] s given by:

where W , s the width of the PMOS transistors,and u1,u2,u3 are constants. It is noted tha t the minimumpropagation delay can be obtained by adjusting W, accord-ing to number of fan-out or loading.

In concerning low power consumption, CMOS is always sup-posed to the best circuit configuration. However, since thereis redundancy in most CMOS circuits, the parasitic capaci-tance would result in unintended power loss.

In CSL, however, parasitic capacitance is minimized with-out affecting the logic str uct ure of the circuit. In addition,voltage in internal nodes is of s u b -Vdd swing instead of fullVdd swing.

On th e contrary, in domino or T SP C dynamic logics, therewill be continuous charge/discharge in internal nodes suchthat power dissipation is relatively high [4]. For example,in the TSPC latch (or DF F) [lo], charging and dischargingoccurs on every clock cycle even if the input data is not

2.1. Power Consumption

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changed (non-shuffle). It will result in unintended powerloss due to the pre-charge operation.The power dissipation of the circuits on different clock he-quency is illu strat ed in Fig. 3. Power dissipation wascompared on four types of DFF s (single-rail True SinglePhase Clock: TSPC [lo], complex-gate st ati c, dual-rail pass-transistor logic, and CSL). It is shown that CSL-DFF canachieve low power dissipation while attaini ng relatively highoperating frequency. Simulation result showed th at a choiceof aspect ratio of 10 on PMOS and 5 on nMOS would resultin an average reduction of consumption power of about 30percents as compared to complex-gate sta tic D-type Fli pflopwhile giving a 20-percent of improvement on clock-to-outputpropagation delay. Device parameters are based on stan dard1.Opm gate length CMOS technology, with transconduc-tances Kn=150pA/V2, Kp=38pA/V2 and threshold volt-ages, VT ~= O. ~V , =-0.5V, where indices n and p repre-sent nMO ST and pMOST respectively.

In short, CSL is characterized by the isolation of currentflow in half clock cycles. And, voltage swing in internal nodesis reduced by a threshold voltage drop at the cross-coupledtrans isto r pair a nd clock signal can also be reduced to certainexten t, according to application. However, disadva ntages ofthis circuit are the necessity of complementary inputs anddifference in Q and QB output propagation delays.

2.2. Result

3 Reduced (Sub-V&) Voltage-swing Interfacing

Another low power circuit design methodology is the applica-tion of sub-Vdd internal signals[3]. Consider the circuit con-nection in Fig. 4, which is applicable in both pass-transistorlogic and CPL. The overall propagation delay includes (1)the delay on the inverter (or driver) that drives the tran-sistor chain, (2) delay on the transistor chain, and (3) thereceiver delay. The driver is an inverter with pMOST andnMOST of low threshold voltages, and scaled supply volt-ages (Vci and Vsi), while the receiver is an ordinary inverterwith pMOST and nMOST of normal threshold voltages, andunscaled supply voltages (Vdd and 0) . It is noted th at delayon conventional scheme increases drastically as vdd is lessthan 2V . However, the driver- receiver link with reducedlogic signal swing can attain high performance even as thevoltage swing is scaled down to about 0.6V. This result isconsistent with the work of Nakagome [l].

In concerning t he ra tio of scaling of logic signal swing, cal-culation and simulation were done on the transistor chain.For preliminary analysis, t he delay time on the fall time orrise time is estimated by

where V*, is the normal nM OST threshold voltage,It is estimated th at a choice of y on 0.10 to 0.20 is suitablein sub-Vdd voltage-swing.

The total power consumption is estimated by:Ptotal= p d + p, + P o = P d +Pq + o v d d ................... 5 )

where P d is the dynamic power,P, is the short-circuit power,Po s the stati c power (power dissipation d ue t o leakage cur-rent), andIo is th e leakage current.The dynamic power consumption is defined in Eq . (1). Theshort-circuit curren t power consumption is given by

P, = fciockIm.$anVdd...... ... ......... 6 )And, th e leakage current is defined by an exponential func-tion on gate-source voltage[4].

Results on a bulk-MOSFET model suggested that nor-malized propagat ion delay and power dissipation of a driver-receiver link should be given by Table 1.

It is noted that with the introduction of low-vth transis-tor, propagation delay of a driver-receiver unit can be cut toabout one-third as compared to th at of inverter-inverter unitwith high-&h transi stors. In concerning power dissipation,the penalty wil l happen in leakage current and short-circuitcurrent. However, in compared with t he dominan t portio n ofthe dyn amic power, these factors has become negligible. Onthe other hand, as concerning circuit design on low supplyvoltage and exclusive 10W-Kh transistors, power dissipationcan be kept small (1/3) while achieving medium operatingspeed. As a result, design methodology depends mainly ona trade-off between expected operating speed and availablefabrication technology.

One of the criteria to minimize dynamic power can be re-flected by the Dynamic Power Factor:

DPF = Cf",,c,Vsw(z)........... 7)With reduced voltage-swing, it is noted that dynamic powercan be reduced (Fig. 5).

4 DiscussionIn general, the key to low power high speed logic design isa proper choice of supply voltage and threshold voltage. Ona mesurement on high frequency operation of an inverterarray with transistor threshold voltages, VT"=O.~V, VT~=-0.3V, leakage current is of the order of 40nA at V&=2.OV[ll]. It reflects the corresponding value of static power inthe power-off mode of CSL. Although th is value convincesa higher static power than prediction in modeling (Tablel), the value is negligible as compared to d ynamic power or

(19 - 287)Vdd - 20%; short-circuit power. In the application of Sub-Vdd voltage-(3) swing, Multiple-valued-Threshold CMOS (MTCMOS) is onen[ (1 + 8y)Vdd ].................LPn[(l - 7)Vdd - v] of the solutions[l2]. Practical d at a on tempe rature sensitiv-

ity suggests that MTCMOS can perform better than (morestable) conventional CMOS. For instance, t he average tem-perature coefficient of propagation delay of logic gates onMTCMOS can be reduced to O.lO%/degree below 80C, whiletha t of conventional CMOS is 0.14%.

where y is an index for scaling,V& is the low valued nMOST threshold voltage,Pn s the conduction factor of nMOST, andCL is the effective load capacitance.It is in contrast to the delay in conventional inverter[4]:

Upon several investigation on CSL and sub-Vdd voltage-swing interfacing logics, low power digital design can be

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h i p omain with constant Vth and Vswing//

1.0 -0.8 ~

0.6 -

Low power

A (mW)ower Dissipation j______

Examples on Hyper-Design Domain:

0.4 -

0 2 -

( 1 ) Reduced Swing in Data Line(2) Reduced Swing in Clock Signals (CSL)(3) SubVdd Interfacing(4) Reduced Swing CSL

comp1er-gate SlatiC/ J

Figure 1: Concept of the hyper design domain

achieved without loss of stability and reliablity on these twodesign methods.

A comparison on the performance of CMOS , CSL, CPL ,Sub-Vdd CPL, and dynamic logic are given in Table 2. Itis noted that features on different logic techniques are var-ious. Th e choice and tradeoff of technology depend mainlyon application and speed-power requirement.

Further application of reduced voltage-swing techniquescan be found in [13], in which reduced signal swing on databus is achieved by termination resistors. DP F on such ar-chitecture is very low because magnitude of the signal issuppressed to less than one-tenth of the supply voltage. An-other type of low swing circuit scheme was developed by[14] n which half-swing clock signal is used to reduce powerconsumption on clock circuitry. In this method, a practi-cal reduction of 67 percents of power was established on alatch circuit, while the theoretical limit is a reduction of 75percents at the clock drive.

Several methodologies in low power digital design are dis-cussed a nd two of the new circui t design techniques are pro-posed: CSL and Sub-Vdd Voltage-swing Interfac ing. In CSL,power dissipation is reduced with the reduced number oftransistors and with the introduction of the clock separa-tion transistors on vertical transistor tree. In the Sub-&Voltage-swing Interfacing technique, multiple voltage sup-plies are used to drive internal signal levels. High speedtransition is achieved by MTCMOS. However, there is stilldifficulty in th e fabrication process. In addition, further re-duction in voltages at internal nodes can reduce the powerdissipation to certain extent, in accordance with application.

5 Conclusion

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c c"Ai

0

T Clock period2T --*(a)

0

Figure 2: Internal voltage-swing in (a) complex-gate DFF, and (b) CSL-DFF

Figure 3: Power dissipation of different circuit con-figurations versus operating frequency


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References[I] Y.Nakagome et al , IEEE J.Solid-state circuit, vol. 28,

[2] K.Shimohigashi, et al, IEEE JSolid-state circuit, vol.[3] T.S.Cheung, K.Asada, IEICE Proc. 1994 Fall Confer-

[4] C.Mead, L.Conway, Addison-Wesley Pub. Co., 1988,

[5] D.Liu, C.Svensson, IEEE J.Solid-state circuit, vol. 28,

[6] K. Chu, IEE E J.Solid-state c ircu it, vol. 22, Aug., 1987,

[7] A.P.Chandrakasan, IEEE J.Solid-state circuit, vol. 27,

[8] K.Yano, et al, IEE E JSoli d-sta te circu it, vol. 25, no. 2[9] T.S.Cheung, K.Asada, Proceeding ASICON 1994, no.

[ lo] J.Yuan, C.Svensson, IEE E J.Solid-state circuit, vol. 24,[l l] H.Ito, K.Asada, The Japan Society of Applied Physics,

[12] T.Douseki, S.Mut oh, IE ICE Pro c. 1994 Fall Confer-

1131 M.Ikeda, et al, IEICE Trans. Electronics, E76-A, no.[14] H.Kojima, et al, 1994 IEEE Symp. on VLSI Circuits

no.4 , April, 1993, pp. 414-419.28, no. 4 , April, 1993, pp. 408-413.

ence, SC-9-5, pp.243-244.

pp. 221-237.

Aug., 1993, pp. 10-17.

pp. 528-532.

no. 4 , April, 1992, pp. 473-483.,April, 1990, pp. 388-395.

4.20, Beijing, China, Oct. 1994, pp. 275-278.no. 1 , Feb., 1989, pp. 62-70.19pZG-5, Sept. 1994.

ence, C-477, pp.155.

10 , pp. 1666-1675.Digest of Tech. Papers, pp. 23-24.

I1 2 -

1.1 -

1.0 -09 -

0.8 -

07 -

0.6 -

0.5 -04 -

0.3 -

0.2 -0.1 -

I (ai 250MHz)

VddI

I

I0 > V s w i n g ( ~ )0.5 I o 1.5 2.0

Figure 4:Simulated propagation delay versus logicsignal swing

CE%SUbVdd- --f-PLFigure 5 : Comparison of features of CMOS, CPLand sub-Vdd CPL full adder: (a ) power consump-tion, and (b) propagation delay.

Table 1. Comparison of normalized delay and power dissipationon full swing and reduced swing logicsLow Vth High Vth

Table 2. Comparison of performance of different logic circuittechniquesI 1 CMOS I CSL I CPL IPower dissipationSpeed

Stability (Noise margin)Stability (Power-off mode)Immunity to noise fromclock sianal

Power dissipation Lower HighStability (Noise margin) MediumImmunity to noise from Weak Weakclock signal

Speed Very Fast

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low power cmos digital circuit design methodologies with reduced voltage swing

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