low temperature plasma applications (in the semiconductor

1

Low Temperature Plasma Applications(In the Semiconductor Industry)

Gottlieb S. Oehrlein

Materials Science and Engineering Institute for Research in Electronics and Applied Physics

University of Maryland, College Park, MD 20742

© Copyright byG. S. Oehrlein

2015

ISPC 2015 Summer School

G. S. Oehrlein, ISPC 2015 Summer School

Outline

Moore’s Law• Plasma etching – key capability

Equipment

Conductor etch

Insulator deposition and etch

Advanced patterning/atomic layer deposition/line edge roughness (LER) of masking materials

Atomic layer etching

2


Plasma is Used to Transform Electrical Power

Electrical power

• Circuit, matching network

Electric fields – energetic electrons (several up to 10 eV) – “hot”, while gas remains “cold”

• Non-equilibrium

Collisions with atoms, molecules

• Excitation – light

• Ionization – ions

• Dissociation – atoms, radicals ….

Plasma can

• Serve as a light source

• Change materials through interactions with surfaces…

Plasma-based productsGoogle images


Plasma Create Chemically Reactive Species

Electron impact collisions on atoms and molecules produce reactive species

• Neutrals and ions

• Chemical reactions at surfaces for modification, synthesis of new materials, etching of intricate structures ….

Non-equilibrium: High chemical reactivity at low ambient gas temperature provides high flexibility for materials processing

4 3

x

e CF CF F e

F surface

etching

CF surface

deposition

3


“The Chip That Changed The World”

Sept. 12, 1958

“A small electronic component that has caused one of most dramatic outpourings of technological progress in human history turned 50 last week.

The integrated circuit, better known as the semiconductor chip, has unleashed change comparable to the Industrial Revolution by making the computer revolution and the digital age possible.

Today there are far more chips on earth than people. All around us, millions of them are tirelessly at work - in computers, phones, television sets, printers, copiers, CD players, PlayStations, cars, trains, airplanes, in almost all electronics.”

http://www.nytimes.com/2008/09/19/opinion/19iht-eddas.1.16308269.html

http://keranews.org/post/day-1958-ti-engineer-invented-chip-changed-world

G. S. Oehrlein, ISPC 2015 Summer SchoolG. Moore, Intel

Moore’s Law

4


Geometric Scaling: Scientific Basis of Moore’s Law

Dennard, Gaensslen et al, 1974 Simple rules for geometric scaling

Key Capabilities: Patterning Using Optical Lithography and Directional Plasma Etching

After photoresist coating, processing, optical exposures and development

After directional plasma etching

5


Reactive Ion Etching (RIE)

“Workhorse” for pattern transfer since late 70’s

Plasma density and ion bombardment energy are controlled by single Rf power supply

Pressure range: 20 mTorr - 250 mTorr


Plasma-Materials Interface

Interfacial region between plasma and material (may be solid, liquid …)

• Sheath physics

Interactions of incident fluxes with surfaces

• Neutrals

• Ions

• Electrons

• Photons

• The role of microscopic surface features

Etching, growth or modification for 3-D objects

Plasma

Sheath

Material

6


Processes that Occur During Reactive Ion Etching of a Silicon Wafer

Reactive ion etching is based on a complex sequence of microscopic reaction steps

Gasification of thin film requires

• chemical reaction of etchant w/ thin film material at acceptable rate

• formation of product w/ high vapor pressure

Oehrlein et al., 1992

Thorsten Lill, Lam Research

Capacitively and Inductively Coupled Systems

7


Dual Frequency Capacitively Coupled Etching System

Major attraction: Simplicity of design

Physics of electron heating based on traditional RF-based RIE

Higher density because of use of higher drive frequency

Werbaneth, et al., Tegal Corporation, 2000


Dual Frequency Etching System

Werbaneth, et al., Tegal Corporation, 2000

8


1-15

ICP Apparatus

Ventzek et al. 1994

“Stovetop” coil is driven at 13.56 MHz and produces plasma• Current in coil produces

oscillating magnetic field flux

• Time-dependent magnetic field in turn induces a current in the plasma (Lenz’s law of induction)


2-D Model of Azimuthal Electric Field and Power Deposition

Ar/Cl2 /BCl3 = 1/1/1

10 mTorr, 600 W ICP,

100 V bias, 150 sccm

M. Kushner et al.

9


2-D Model of Ion Densities10 mTorr, 600 W ICP,100 V bias, 150 sccm

M. Kushner et al.

Ar/Cl2 /BCl3 = 1/1/1


The Sheath Structure, Bohm Velocity and Ion Bombardment

Debye shielding is not complete in pre-sheath

This potential accelerates ions and they arrive at the sheath edge with a finite velocity

After Thornton

10


Origin of the Saddle-Shaped Energy Distribution (No Collisions)

Key parameters that determine ion energy distribution:

RF frequency relative to ion plasma frequency

Pressure - sheath width vs. gas mean free path

100 kHz.

Köhler et al., 1985

Ion Energy Distribution Function for Cl2

Discharge as a Function of Pressure

Manenschijn et al., 1991.

Pascal

RF system - ion energies determined by RF bias,plasma potential and collisions

11


Silicon Trench Etching: Recent Technology

Deep trench for storage capacitor

Dielectric mask – 1500 nm

Si trench depth – 8000 nm

Aspect ratio Depth/Width – 50:1

IBM, 2007


Outline


Equipment

Conductor etch




12


Ion Enhanced Etching

Ion/neutral synergy in etching of Si

Explained by thinning of reaction layer and ion bombardment driving a disproportionation reaction

Can explain achievement of etching directionality for some plasma conditions

Coburn & Winters, 1979


Silicon Surface Chemistry for Fluorine Attack

Reacted layer is formed on Si surface

SiF3 is abundant for Si etching without ion bombardment

Ar+ ion bombardment reduces the intensity of SiF3 relative to SiF and SiF2

Simultaneously, SiF2

density goes up, consistent with

Himpsel, 1985

13


Silicon Etching

Importance of energy barrier for backbond attack Not existent for F atoms – spontaneous etching Of the order of eV for Cl and Br atoms – etching requires ion bombardment

SiSi

Si

SILICON

HALOGEN

E

G. S. Oehrlein, ISPC 2015 Summer School Szabo et al. 1994

Measured Cl Coverage of Si vs. Exposure

14


Ion Enhanced Etching: Ion Neutral Synergy

Mayer and Barker, 1982

Neutral-dominated

Ion-dominated

N+ dopedSi

Complication: Doping Effect

Schwartz et al, 1983

Si etching using Cl2 discharge

15


Doping Effect

Fluorine-rich discharge

No ion bombardment

What explains the enhanced spontaneous reaction rate for n-type material?

Lee et al, 1984


Doping Effect

Spontaneous etching is related to band bending near surface of semiconductor

Electrostatic interaction with negatively charged halogen atoms, e.g. F -

Lee et al, 1985

16

G. S. Oehrlein, ISPC 2015 Summer Schoolh

Sidewall Passivation: Processes in Structure

Material that requiresion bombardment for etching SiO2

Fluorocarbon


Sidewall Passivation in Chlorine/Oxygen

An etch-resistant SiOxCly layer is formed on the sidewalls of Si trenches and lines


17


Sidewall Passivation: Model



Silicon Trench Etching: Recent Technology

Deep trench for storage capacitor

Dielectric mask – 1500 nm

Si trench depth – 8000 nm

Aspect ratio Depth/Width – 50:1

IBM, 2007

18


Gate Stack Patterning

One of the critical etching steps in information technology, since the accuracy of pattern transfer determines the switching speed of the field effect transistor

• Nearly perfect etching selectivity to gate insulator (for state of the art ~100 nm thick gate conductor vs. ~1 nm gate insulator thickness)

Normally performed using a three-step etching process

IntelSiO2

Gate

Source Drain


SEM of 15 nm Poly-Si Line Etched in an ICP Reactor

Demonstrates satisfactory etch profile control

• No trenching

• No notching, etc.

High etching selectivity to 1 nm thick gate dielectric

IBM

19

Representative Poly-Silicon Gate Etching Process

Breakthrough Main Etch OveretchDuration (s) 10 30 81 (100%)

Pressure (mTorr) 2 2 6

Source Power (W) 1000 1000 1000

Bias Power (W) 100 50 28

HBr Flow (sccm) 25 25 10

Cl2 Flow (sccm) 15 15 30

He/O2 Flow (sccm) 0 0 30

He Backside Pressure (Torr) 10 10 10

Chiller Temperature (oC) 20 20 20

R. Kraft and S. Prengle, 1995


Notching

The last line in an array of lines shows a notch

Notch forms during overetching (all the Si has been removed)

Origin?

Fujiwara et al, 1996

Si

ResistResist

SiO2

20


Giapis and Hwang, 1997

Notching During Gate Etching


Light Scattering for Dust and Nanoparticles

RF

PlasmaChamber

IncidentLaserRadiation

TransmittedLaserRadiation

Scattered LaserRadiation

Electrode

Electrode

Window Window

Reactor2.ppt partphotSelwyn et al., 1989

21


Light Scattering Due to nm-Scale and Larger Particles- Dusty Plasmas

dusty.physics.uiowa.edu/~goree/papers/Physics...

20−μm−diameter particle from dust cloud


Defects on Wafers

Wet cleaning can remove defects, but also can collapse patterns

Lee et al., 2014

22

Silicon Etching in MEMS Technology: Bosch Process

The Bosch process is used to etch high aspect ratio structures into Si.

Cyclic Process with two steps:Deposition: Passivating polymer coatingEtching: Aggressive SF6 based

Cycle times: ~ 15 sec.

Typical Process Results:Si Etch Rate: up to 4 m/minSelectivity: 80:1 to photoresist

250:1 to SiO2 mask

Aspect Ratios that can be achieved :> 60:1

1) Deposition of polymer

2) Plasma etching

F. Laermer and A. Schilp, “Method for anisotropic plasma etching of substrates,”US Pat. 5498312, March-12 (1996).

Bosch Process: Examples

3 m beam width, 250 m high.

350 m deep trenches, 3 to 10 m wide beams.

P.G. Hartwell, 44th National Symposium of the American Vacuum Society.

Stripes in sidewall

23


Outline


Equipment

Conductor etch




Interconnect Problem

Current integrated circuits may contain up to 5 billion transistors

Integrated circuits are dominated by interconnect wiring which locally and globally connect units of the IC

IBM (http:\\www.chips.ibm.com)

Metal

Dielectric

24


Dominance of Interconnects for Integrated Circuits of Billions of Transistors

From Bottom:

• word lines -poly-Si w/ silicide• local interconnections -tungsten• global interconnections -Ti/Al(Cu)/Ti/TiN

Mann et al., 1995Multilayer Metal Lines and Studs in Partially Completed SRAM

Dominance of Wiring for Integrated Circuits

Fabrication Requires 1) Etching of Metal

1) Approach is very similar to Si directional etching2) Deposition of a planarized SiO2 layer

2) Or etching of high-aspect ratio trenches/holes into SiO2;1. Filling of the high-aspect ratio holes by electroplating

• Metal liner• Metal

2. Chemical-mechanical polishing of the excess metal.

25


Plasma Enhanced Chemical Vapor Deposition of Silicon Dioxide

Most common: SiH4 + 4 N2O (nitrous oxide)

SiO2 + 4 N2 + 2 H2O Si(OC2H5)4 (tetraethoxysilane – TEOS)

SiO2 + 4 C2H4 + 2 H2O SiH4 + 2O2(+Ar)

SiO2 + 2 H2O(+Ar)

Common problems: Hydrogen or carbon incorporation


Proposed Gas Phase Mechanism of Silicon Dioxide Deposition in a High-Density Plasma

O2/Ar/SiH4 – 37.5/40/22.5 %

Composition of plasma: 25.5% Ar; 4.4% Ar* 18.5% H; 13.5% H2 11.2% O; 9.3% O2; 6.3%

O* 2.3% SiH; 2.2% SiH2; 3.5%

SiO; 2% OH Rest of species < 2%Film Growth SiH, SiH2 – major silicon

containing precursors Ionized SiH and SiH2 are

minor contributors SiO is another important

precursor

"Modeling High-Density-Plasma Deposition of SiO2 in SiH4/O2/Ar", E. Meeks, R. Larson, P. Ho, S. Han, E. Edelberg, E. Aydil and C. Apblett, JVST A 16(2) 1998, p. 544-563.

26


Bias Sputter Deposition of SiO2:IR Data

Little evidence of hydrogen incorporation

Lam Research/Sumitomo


Bias Sputter Deposition of SiO2: Breakdown Diagram

Near-thermal quality silicon dioxide characteristics


27


Deposition Onto Structured Substrates

Substrate

Directional DepositionConformal Deposition(e.g. atomic layer deposition) High-density plasma


Silicon Dioxide Deposition for Wiring Insulation

Filling of high aspect ratio features is important challenge

Plasma-assisted chemical vapor deposition of dielectric thin films for ULSI semiconductor circuits by D. R. Cote, S. V. Nguyen, A. K. Stamper, D. S. Armbrust, D. Tobben, R. A. Conti, and G. Y. Lee, IBM J. Res. & Devel. 43 p. 5, (1999)

(a) PECVD – little ion bombardment(b) Thermal CVD – no ion bombardment(c) High-Density Plasma CVD – intenseion bombardment

SiO2

Metal

28


ECR Tool for Bias Sputter Deposition of SiO2


Typical Angular Dependence of Etching Rate

ER(Θ)= ER0S(Θ) cos(Θ)Normalized at Θ=0.

Modeling and simulation methods for plasma processing,S. Hamaguchi, IBM J. Res. & Devel. 43, 199 (1999)

29

Sputter Based Deposition Process

Sumitomo 1989


Bias Sputter Deposition of SiO2: Mechanism


Burggraaf, Semicond. Int. May 1994, pp. 56ICP System

Al

SiO2

30


Evolution of Gate (Transistor) Delay and Wiring (Interconnect) Delay

Device Generation

From D. R. Cottrell

Copper Metal

Reduce RC delays by replacing Al with Cu

• (and SiO2 with low-dielectric constant materials).

Since copper cannot be patterned by plasma etching, it is deposited into trenches and holes plasma etched into the dielectric and patterned by chemical mechanical planarization (CMP).

Copper Damascene Process

31


Plasma Etching of Quartz

Quartz and silicon dioxide

Extremely high chemical stability

Plasma etching normally performed in fluorocarbon plasmas using significant ion bombardment

Volatile compounds

• SiF4

• CO, CO2 , COF2

Controlling the amount of free fluorine and carbon flux enables control of etching selectivity relative to other materials

Cristobalite


Selectivity Challenge in Oxide RIE

Problem:

Acceptable etching rates of SiO2

in fluorine-based plasmas require significant ion bombardment

Energetic ion bombardment makes it difficult to stop etching on mask or underlayer

Simko et al., 1991

Solution: Deposit selectively an etch stop layer

on the underlayer to prevent ion induced etching

Use of fluorocarbon chemistry enables to exploit oxygen produced by etching of SiO2 to prevent film formation on SiO2

32


Heinecke: US Patent 3,940,506, 1976:

Fluorocarbon-based Plasma Etching and

Deposition


RF Bias Voltage Dependence of the Silicion Dioxide Etch Rate in Fluorocarbon Plasma

The oxide etch rate exhibits regimes of

• fluorocarbon deposition (a)

• fluorocarbon suppression (b)

• reactive sputtering (c)

Oehrlein, et al., 1994

33


Selective Surface Etching Mechanisms for Fluorocarbon Plasmas as Described by Heinecke

RF bias voltage creates ~ 200 eV ions Discharge composition is adjusted to affect selective deposition and

etching processes


Selective Oxide etch mechanism in a fluorocarbon plasma

Fluorocarbon Film

Substrate

CFx

+n

Si

SiF4

volatileCFx

CFx

+n

SiO2

SiF4

volatileCFx

COCO2

COF2

Fluorocarbon-based Etching

34

Substrate Steady-State Etching Model Through Fluorocarbon Film

Fluorocarbon balance (steady-state substrate etching):

Substrate etching rate for steady-state:

0

01sub

FC

net

ERER

DR CR

ER

Fluorocarbon

Substrate

DRFC ERFC ERSub

CRFC

Substrate Etching and Concomitant FluorocarbonRemoval (oxidation, etc)

ERSub

CRFC

ERFC

DRFC

FluorocarbonEtching

FluorocarbonDeposition byNeutrals and Ions

ERnet MeasuredFluorocarbonEtching Rate

CR0Stoichiometric FC Removal


Effect of the Steady-State Fluorocarbon Film on Etch Rates

For SiO2, Si3N4, and Si

• fluorocarbon films of process-dependent thickness exist on etching surfaces

• the ER decreases w/ the thickness of the fluorocarbon layer

Schaepkens, et al., 1997

35

1-69

Changes in Silicon Surface After Fluorocarbon Contact Hole Etching Process

Contact resistance


Outline


Equipment

Conductor etch




36


Current semiconductor lithography – still 193 nm based, but 22 nm devices are being fabricated

How is this possible?

Lag of Extreme Ultra-Violet Lithography


Gap in Lithography Roadmap

Hard masks and double patterning enable below-wavelength patterning

Double patterning, quadruple patterning …, necessitate many additional deposition steps using atomic layer deposition, followed by plasma etching steps

Thorsten Lill

37


Pitch-Splitting with 193i

Pitch-splitting by Sidewall Image Transfer (or Self-Aligned-Double Patterning (SADP)

Core removal – also called mandrel pull

Lee et al., 2014


Atomic Layer Deposition

Profijt et al., 2011

38


Remote Plasma ALD Reactor Equipped With An Inductively Coupled Plasma Source

H. B. Profijt et al. Electrochem. Solid-State Lett. 2011;15:G1-G3


Silicon Dioxide Spacer by Atomic Layer Deposition

The ALD-SiO2 film formation uses a Pre-X for Si source that has the amino group and 0 radicals or 03 excited by an O2 plasma as the oxidation source.

Ｈ.Yaegashi, TEL; T. Shibata, TEL

39


Conformal Coating

T. Shibata, TEL


Line Edge Roughness (LER) and Wiggling

Wiggling

C. Labelle, 2009

Transition from 248nm to 193nm lithography required a change in polymer structure

248nm PR

E. Hudson, et al., Proc. Dry Process Int. Symp. 253 (2003)

193nm PR

40


Challenge of Plasma-Polymer Interactions For Nanoscale Patterning Of Materials

30 nm wide line is defined by 6-10 polymer molecules (~ 3-5 nm diameter) Current resists do not satisfy LER requirement for 22 nm lines < 1nm

Photon (UV)-Modified Region

Ion and Neutral-Modified Region

e-

Polymer Molecules (3-5 nm diam.)

0 s

193nm Photoresist PatternHua et al. C4F8/90%Ar etching process

Hua et al.

41

0s193nm Resist

1.6 s

Surface roughness, randomorientation of grains

193nm PR

0s193nm Resist

7.0 s

Pronounced formation of surface roughness

42

0s15 s

Pronounced surface roughnessBegins to be transferred in sidewall

0s29 s

Hua et al.

Continued transfer of surface roughness to sidewall

43

0s45 s

Hua et al.

Pronounced vertically oriented striationsform for longer exposure times

0s193nm Resist

29s

45s

60 s

Pronounced columnar structurefully extends to bottom of line

44

» 4.0 x 1017 ions•cm-2 150 eV Ar+ and 40 min VUV (Ar plasma)

Synergistic Ar+ Bombardment and VUV Effects in Surface Roughness Formation

50°C 60°C 75°C 100°C

193

nm

PR

200 nm

248

nm

PR

200 nm

0.76 nm 9.80 nm

25 nm

5.19 nm

25 nm

2.16 nm

10 nm

0.34 nm 1.59 nm

10 nm

2.30 nm

10 nm

1.04 nm

0 nm

2.5 nm

unless notedon the image

200 nm

200 nm

1 m

Nest et al., 2008


Wrinkling by interaction of dense ion induced surface layer and weakened UV modified photoresist

Mechanism of Synergistic Roughness Formation

1) R. L. Bruce, et al., (2010);

After PEpristine30 nm

h = 1.8 nm

h ≤ 200 nm

Ions

UV

Es ≈ 20-60 MPa

EF ≈ 100 GPa

Limitations in pattern fidelity

UV modification, material dependent1

Ion bombardment, material independent1

Formation of compressive stress

45


30 nmAfter PEpristine

Wrinkling by interaction of dense ion induced surface layer and weakened UV modified photoresist

Mechanism of Synergistic Roughness Formation

1) R. L. Bruce, et al., (2010);

h = 1.8 nm

h ≤ 200 nm

Ions

UV

Es ≈ 20-60 MPa

EF ≈ 100 GPa

250 nm

Limitations in pattern fidelity

UV modification, material dependent1

Ion bombardment, material independent1

Formation of compressive stress

stiff film

soft underlayer

stre

ssbucklinginstability

wrinklingstiff film

soft underlayer

stre

ss


Formation of ~ 1nm Thick Carbon Films

Metzler et al, 2015

46


Plasma Pretreatment (PPT)

Plasma pretreatment• UV plasma radiation reduces plane

strain modulus Es (chain-scissioning) and densifies material without stress before actual PE

• Increased plasma etch durability

Helium PPT:• Helium, 100 mTorr pressure, 800 W

source power, no bias (Eion ≤ 25 eV)

• Little ion crust

• More photons at low wavelengths (58.4 nm) than for Ar using high source power

He Ar

Plasma etch (PE):

– Argon, 20 mTorr pressure, 200 W source power, -100 V bias (Eion ≤ 125 eV)

Similar to typical fluorocarbon/Arpattern transfers


F. Weilnboeck et al, Appl Phys Lett 99 (26), 261501 (2011).

Improvement of Trench Patterns

While PE introduces significant roughness, PPT is not affecting surface morphology

For combined process, features and pattern free areas show strong reduction of surface roughness

FTIR shows significant change when applying the PPT before the PE :

• Bulk modification saturation similar to after PE

• Reduced oxygen content leads to increased etch resistivity

Total changes of thicknesscomparable for short tomedium PPT

0 30 60 90 1200

10

20

30

40

50

-CHx

C=O

C-O-C

abso

rba

nce

loss

[%]

PPT time [s]

47


Outline


Equipment

Conductor etch




Ying Zhang, Applied Materials

48


Intel's 22nm FET: Tri-gate Technology

The Tri-Gate system features

• 3D source-drain "fins“

• Wrap around gate

Move away from planar technology

source

drain


Atomic Layer Etching

Nanoelectronics – need for atomic scale fidelity

Kanarik et al, Solid State Tech. 2013

49


ALE Window

Ion Energy (Directed Energy)

EpsthEceth

(i), (ii), (iii) – increasing amount of chemical reactant up to surface saturation

Th

ickn

ess

Los

s P

er C

ycle

(i)

(iii)

(ii)

ALE WindowSpontaneous

ChemicalEtching

Physical SputterEtching

1. Iterative process cycles are enabled by excellent control over surface reactions. Self-limitation requires:

a. Insignificant physical sputtering

b. Negligible spontaneous chemical etching

2. Low ion energies for a. Self-limitation, high selectivity

b. Damage-free surface processing


ALE Advantages: Flat, Smooth Etch Front

Lam Research, 2014

50


• Crystalline SiO2

A Molecular Dynamics Investigation of Fluorocarbon Based Layer-by-Layer Etching of Silicon and SiO2

Laboratory for Plasma Processing of Materials


SiO2 sample after CF3+ ion bombardment

• Crystalline SiO2


≈ 5 Å


51



For low ion energies:

• Self-limited Si removal

For 50 eV:

• Sputter rates decrease



ALE of SiO2 - Process Description

52


• Good reproducibility

• Stepwise etching

Time-Dependent Etch Rates

35 sBias

10 s

No Bias

1.5 s C4F8

Pulse

0 50 100 150 200 250 300 350

-20

-15

-10

-5

0

5T

hic

kne

ss C

ha

ng

e [Å

]

Time [s]

C4F

8 pulsed

Ar continuous 10 mTorr 25 eV E

Ion

200 W

Metzler et al, 2014


Concluding Statements

The application of low temperature plasma in semiconductor technology has dynamically evolved over about 40 years and is still rapidly developing. It is just one example of the application of LTP to materials processing

We are seeing similar advances in

Synthesis, modifications of other materials

Human healthcare LTP applications

Control of bacteria and viruses that are drug-resistant strains, treatment of air, water by using LTP

Additionally, we anticipate LTP to play important roles in

Advanced combustion, energy, …

Some of these areas are at this point at a development stage that corresponds to that of the application of LTP to semiconductor technology in the early 1980’s

53


An Overview of other Applications is presented in

“The 2012 Plasma Roadmap”S. Samukawa et al., J. Phys. D: Appl. Phys. 45 (2012) 253001

Plasma-etching processes for future nanoscale devices

Plasma deposition processes for ultimate functional devices

Very large area plasma processing

Microplasmas

Plasmas in and in contact with liquids: a retrospective and an outlook

Plasma medicine

Plasma catalysis

Thermal plasma applications, including welding, cutting and spraying

Plasma for environmental applications

Plasma-assisted ignition and combustion

‘Nanodusty’ plasmas: nanoparticle formation in chemically reactive plasmas

Plasma thrusters

Plasma lighting

Plasma modelling at a crossroad

Plasma diagnostics

Atomic and molecular data for plasma physics—challenges and opportunities

low temperature plasma applications (in the semiconductor

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