lt spice

(Focus Test Pattern)

LTspice/SwitcherCAD III

Mike Engelhardt

Linear Technology Corporation

Copyright © 2004, 2005 Linear Technology Corporation

Historical Timeline1969 CANCER (Computer Analysis of Nonlinear Circuits Excluding

Radiation)

1972 SPICE 1 (Simulation Program with Integrated Circuit Emphasis)

1975 SPICE 2 (L. Nagel’s Ph.D. thesis is the user guide)

1981 Linear Technology Corp. founded

1983 SPICE 2G6

1985 SPICE 3

1991 DOS SwitcherCAD(equation based)

1993 SPICE 3F4

1996 µPower SwitcherCAD(simulation based)

1999 LTspice/SwitcherCAD III(SPICE based)

2004 500,000 base LTspice downloads(excluding updates & redistrib.)


LT1533 Case Study

• Voltage and current slew rate limiting

• Complex control logic

• External timing capacitor

• Timing-cap current look-up table

• Demo board available

• Difficult to get efficiency analytically


Demo Board Schematic


Demo Board


The Bench


Minimum Slew Limits

Vin = 5VVout = +/-5VIout = 28mA


With Voltage Slew Limit

Vin = 5VVout = ±5VIout = 28mA


LT1533 Efficiency Comparison

SwCAD III Demo Board

Min. Slew Rate Limit 73.0% 73.0%

With Current Slew Limit 66.0% 65.4%

With Voltage Slew Limit 63.0% 62.0%


Drafting Your Own Circuits• General purpose schematic capture

- Unlimited schematic size

- Unlimited depth of hierarchy

- Graphical symbol editor

- Complete documentation

• Integrated with Industry superlative SPICE simulator

- Unlimited, professional-quality SPICE proven for IC design

- Unmatched combination of robustness, accuracy, speed and compatibility

- Advanced analysis/simulation options, parameter sweeps, FFT’s, etc.

- Run 3rd party models

- Active independent users’ group

• Macromodels of over 950 Linear Technology products


Waveform Display Features• Plot expressions of data assisted with cross

probing

- Cross probe voltages, device and port currents- Differential crossprobing- Dissipation expression composed by the schematic- Dimensional analysis

• Waveform average and RMS calculator

• Fourier analysis (both .four statements and FFT's)

• Parametric plotting (X-Y plotting)

• Multiple plot planes

- Attached cursors ganged across plot panes

• Eye diagrams

• Complex data: Bode, Nyquist, and Cartesian

• Dynamic waveform data compressionCopyright © 2004, 2005 Linear Technology Corporation

LTspice Core Simulator• Rewrite Berkeley SPICE 3F4/5 for machines with faster CPU’s

than RAM- Reduced address calculation and function calling overhead- Improved timestep control and numerical methods- Enhanced integration methods and convergence improvements- Alternate solver/SPARSE matrix package 1000x more accurate.- Circuit size limited by computer memory

• Added/Enhanced semiconductor models- Diode recombination current- JFET impact ionization current- BJT quasi-saturation- VBIC- Binned BSIM3v3.2.4- BSIM4.4.0- VDMOS(a new vertical double diffused MOSFET for power MOS)- EKV 2.6- BSIMSOI3.2

• Advanced Analog Behavioral Modeling Technology- Traditional ABM, specialized behavioral devices, HDL, co-simulation

• Leadership in the SPICE community- Subcircuit port current monitoring- Unlimited output file size, i.e., >> 2GB


Benchmarking SPICE LTspice PSPICE¹ hspice²ab_ac 4.750* 7.59 14.63ab_integ 0.109* .23 0.17ab_opamp 5.454* 6.44 7.72arom 3.656 6.94 3.34*astabl 1.046* 4.52 5.21b330 2.172 3.16 1.90*bias 3.234* 5.19 8.63bjtff 2.453* 4.17 2.94bjtinv 7.594* 13.03 14.28counter 7.234* 15.16 7.40cram 0.625* .91 0.74e1480 0.250 (fails) 0.09*g1310 3.969* 10.91 5.45gm1 5.562* 12.39 11.14gm17 2.703* 4.47 2.92gm19 12.625 (fails) 9.37*gm2 1.125* 4.91 3.21gm3 3.453* 8.66 8.13gm6 5.109* 13.45 11.84hussamp 0.781* (fails) 1.42jge 33.875 (fails) 9.08*latch 0.969* 2.30 2.42


1] PSPICE is a Cadence Trademark 2] hspice is a Synopsis Trademark

Transistor-level performance

Benchmarking SPICE(Cont.) LTspice PSPICE hspiceloc 46.687 8.86* 10.64mike2 5.797* 37.83 21.39mosrect 9.734* 17.22 29.14mux8 6.531* 12.00 11.91nagle 0.672* 1.28 1.53nand 2.250 1.08* 2.45opampal 5.109 1.41* 4.50optrans 7.500 6.17 3.14*pump 0.016* .23 0.49rca 1.719 1.53 1.45*reg0 4.406* 37.22 28.78rich3 35.610 (fails) 4.67*ring 5.562* 10.33 19.36ring11 2.360* 3.11 4.72schmitecl 0.015* .16 0.06schmitfast 8.297* 21.16 29.09schmitslow 10.781* 23.84 37.28slowlatch 0.156 .22 0.11*todd3 0.156 .22 0.06*toronto 5.031* 11.74 11.72vreg 0.735* 2.16 2.86

WINS: 30 3 10Copyright © 2004, 2005 Linear Technology Corporation

LTspice Behavioral Simulator


• PSPICE style behavioral modeling

- Legacy POLY() statements

- Arbitrary expressions

- Laplace

- Look-up tables.

• Arbitrary capacitance: write an expression for the charge.

• Arbitrary inductor: write an expression for the flux.

• An original mixed-mode simulator -- not xspice based.

Mixed-Mode Simulator

• Computationally lightweight

• Tight feedback between analog and digital circuitry

- Implemented as a mix of intrinsic SPICE devices and ~30 optimizing HDL compilers.

- Predictors aid timestep control.

• Easy to program so that models for new products are usually quick to be generated.


Example Mixed-Mode Simulation


LTspice's Special Enhancements for SMPS

Simulation• Automatic Steady State Detection and Efficiency

Computation

• Node Reduction

• VDMOS MOSFET Model

• Mixed-Mode Simulator with intrinsic SMPS controller functions

• Nonlinear magnetics with gapped magnetic circuit solver


SPICE Solver Overview


I

1mA

D I

1mA G[n] I[n]

I

1mA G[n] I[n]

I

1mA

D

V[n] V[n+1]D D

V[0] = 0V

[G][V]=[I]Linearize

Linearize About New Voltage Solution

Newton-Raphson Iteration

Solve Matrixfor Voltages

Initial Solution Guess

Circuit to Simulate

SPICE Solver

G[n] I[n+1]G[n+1] I[n]

Circuit MatrixNodal analysis: [G][V] = [I]G: Conductivity matrixV: Unknown voltage vectorI: Known current vector

• Node count is more important than part count.

• It’s best to avoid floating voltage sources

Modified Nodal analysis: [ G “1”] [v] = [I] [“1” R ] [i] = [V]G: Conductivity matrixv: Unknown voltage vectori: Unknown current vectorV: Known voltage vectorI: Known current vector


Capacitor Companion Model


Inductor Companion Model


VDMOS MOSFET

Source

Gate

Drain


Source Gate

Bulk(Substrate)

Drain

Normal Monolithic MOSFET(Used in IC’s)

VDMOS(Discrete Power

MOSFET)

Drain-SourceCurrent Path

LTC Proprietary VDMOS ModelReplace a problematic subcircuit with a single new intrinsic SPICE

device


VDMOS Gate Charge Behavior


Two-Phase SMPS & PLL Capture


Total elapsed time: 19.809 seconds.

Chan et al. Nonlinear Magnetics


A computationally lightweight model that uses only three parameters to specify the core’s major

hysteresis loop:

Hc: Coercive force [Amp-turns/meter] Br: Remnant Flux Density [Tesla] Bs: Saturation Flux Density [Tesla]

Gapped Core Magnetic Solver


• Core physical dimensions specified with four parameters:

Lm: Magnetic Length(excl. gap)[meter]Lg : Length of gap [meter]A: cross sectional area [meter**2]N: number of turns

Core Saturation Considerations

If you use the worst inductor that works in simulation, you will have failures over service temperature and

production scatter.Copyright © 2004, 2005 Linear Technology Corporation

• Saturation flux density goes down monotonically with temperature

• Maximum service temperature plus self-heating• Controller peak current production scatter• Startup/transient/short circuit conditions

Simulating Transformers


Mutual coupling K-statement

placed as a SPICE directive

on the schematic

Multiple Windings


For N windings, the number of mutual couplings is

=

Misc. Advanced Features• Waveform plot annotations

• Hierarchy

• BUS’s

• Fast Access file format.

• .measure statements

• Optional double precision data files

• Read/Write .wav files

• URL's in a .lib and .inc statements

• Color Preference Editor

• Programmable Keyboard Shortcuts


Misc. Advanced Techniques• User-defined parameters & functions

• .step’ing a user-defined parameter - Overlay simulation runs - Parameter sweeps - Monte Carlo - Optimization

• Open loop response from closed loop system

• Using the Universal Opamp Model

• Adding 3rd party models


Common Pitfalls

• Mirror & Rotate buttons greyed out

• Copy block from one schematic to another

• Hidden filename extensions

• Start-up overshoot

• Dissipation: RMS or Average?

• Finding steady state


Adding 3rd Party Models• RCL databases - standard.res - standard.cap - standard.ind - standard.bead

• Intrinsic Devices - standard.dio - standard.bjt - standard.mos - standard.jft

• Subcircuits - define on schematic - program symbol to

automatically include the required library - explicitly .inc the model


Built-in Help System


Updates With Field Sync• Incrementally updates your installation off the

web

• Automatically merges databases of devices

• Free Lifetime Updates


Reporting a Bug


• Make sure you’re using the current version with Field sync.

• All bug reports are appreciated and will be resolved.

lt spice

Documents

radiation1972 spice

current slew rate

current slew limit66

professionalquality

voltage slew limit63

slew rate limit73

circuit size

power mos ekv