mac7100 microcontroller family reference manual - keil · contents paragraph number title page...

Preliminary

MAC7100RMRev. 1.010/2004

MAC7100 Microcontroller FamilyReference Manual

Devices Supported:MAC7101 MAC7106MAC7111 MAC7112MAC7116 MAC7121MAC7122 MAC7126MAC7131 MAC7136MAC7141 MAC7142

Preliminary

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Freescale Semiconductor, Inc. 2004

MAC7100RMRev. 1.010/2004

MAC7100 Microcontroller Family Reference Manual, Rev. 1.0

Freescale Semiconductor Preliminary iii

1Introduction2Signal Description3Voltage Regulator Module (VREG)4System Clocks Module (OSC and CRG)5Resets6Exceptions7Modes of Operation8Device Memory Map9ARM7TDMI-S Processor Core

10Interrupt Controller Module (INTC)11Miscellaneous Control Module (MCM)12Enhanced Direct Memory Access Controller Module (eDMA)13External Interface Module (EIM)14Cross-Bar Switch Module (XBS)15Common Flash Module (CFM)16AMBA to IP Bus Bridge Module (AIPS)17DMA Channel Multiplexer Module (DMAMux)18Port Integration Module (PIM)19Analog-to-Digital Converter Module (ATD)20Enhanced Modular I/O Subsystem Module (eMIOS)21Enhanced Serial Communications Interface Module (eSCI)22Deserial Serial Peripheral Interface Module (DSPI)23Controller Area Network Module (FlexCAN)24Inter-Integrated Circuit Bus Module (I2C)25Periodic Interrupt Timer Module (PIT)26System Services Module (SSM)ADebug InterfaceBA7S Nexus 2 ModuleCRegister Memory Map Quick ReferenceDMask Set Differences Summary

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iv Preliminary Freescale Semiconductor

1 Introduction2 Signal Description3 Voltage Regulator Module (VREG)4 System Clocks Module (OSC and CRG)5 Resets6 Exceptions7 Modes of Operation8 Device Memory Map9 ARM7TDMI-S Processor Core

10 Interrupt Controller Module (INTC)11 Miscellaneous Control Module (MCM)12 Enhanced Direct Memory Access Controller Module (eDMA)13 External Interface Module (EIM)14 Cross-Bar Switch Module (XBS)15 Common Flash Module (CFM)16 AMBA to IP Bus Bridge Module (AIPS)17 DMA Channel Multiplexer Module (DMAMux)18 Port Integration Module (PIM)19 Analog-to-Digital Converter Module (ATD)20 Enhanced Modular I/O Subsystem Module (eMIOS)21 Enhanced Serial Communications Interface Module (eSCI)22 Deserial Serial Peripheral Interface Module (DSPI)23 Controller Area Network Module (FlexCAN)24 Inter-Integrated Circuit Bus Module (I2C)25 Periodic Interrupt Timer Module (PIT)26 System Services Module (SSM)A Debug InterfaceB A7S Nexus 2 ModuleC Register Memory Map Quick ReferenceD Mask Set Differences Summary

Contents

ParagraphNumber Title

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Tables............................................................................................................................. xxixFigures ......................................................................................................................... xxxix

Preface

Document Structure ............................................................................................................ liHow To Use This Document............................................................................................... liConventions ....................................................................................................................... liiTerminology...................................................................................................................... liiiRegister Descriptions ....................................................................................................... lvii

Revision History

Content Changes by Document Version ........................................................................... lix

Chapter 1 Introduction

1.1 Overview.......................................................................................................................... 1-11.2 Block Diagram................................................................................................................. 1-21.3 Features ............................................................................................................................ 1-41.4 Modes of Operation ......................................................................................................... 1-9

Chapter 2 Signal Description

2.1 External Signal Description ........................................................................................... 2-112.1.1 Clocks and Control .................................................................................................... 2-112.1.1.1 EXTAL, XTAL Oscillator ................................................................................ 2-112.1.1.2 XFC PLL Loop Filter ....................................................................................... 2-112.1.1.3 RESET External Reset...................................................................................... 2-112.1.1.4 TCK Test Clock ................................................................................................ 2-112.1.1.5 TMS Test Mode ................................................................................................ 2-112.1.1.6 TDI Test Data In ............................................................................................... 2-112.1.1.7 TDO Test Data Out ........................................................................................... 2-122.1.1.8 TA / AS Transfer Acknowledge / Address Strobe............................................ 2-122.1.1.9 TEST Factory Test ............................................................................................ 2-12


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2.1.1.10 Configuration and Optional Control Signals ......................................................... 2-122.1.2 General Purpose / Peripheral I/O............................................................................... 2-122.1.2.1 Port A Signal Group .............................................................................................. 2-132.1.2.2 Port B Signal Group............................................................................................... 2-152.1.2.3 Port C Signal Group............................................................................................... 2-162.1.2.4 Port D Signal Group .............................................................................................. 2-162.1.2.5 Port E Signal Group............................................................................................... 2-172.1.2.6 Port F Signal Group ............................................................................................... 2-182.1.2.7 Port G Signal Group .............................................................................................. 2-182.1.2.8 Port H Signal Group .............................................................................................. 2-202.1.2.9 Port I Signal Group................................................................................................ 2-202.2 Power Supply, Bypass and Reference............................................................................ 2-202.2.1 VDDX,VSSX I/O Drivers Power and Ground ....................................................... 2-202.2.2 VDDR, VSSR Internal Voltage Regulator Supply ................................................. 2-202.2.3 VDDA, VSSA Analog Reference Supply .............................................................. 2-212.2.4 VDD2.5, VSS2.5 Core Power Supply Bypass........................................................ 2-212.2.5 VDDPLL, VSSPLL PLL Power Supply Bypass .................................................... 2-212.2.6 VRH, VRL ATD Reference Voltage ....................................................................... 2-212.3 Signal Properties Summary ........................................................................................... 2-222.4 Packaging Options ......................................................................................................... 2-27

Chapter 3 Voltage Regulator Module (VREG)

3.1 Overview........................................................................................................................ 3-293.2 Features .......................................................................................................................... 3-293.3 Modes of Operation ....................................................................................................... 3-313.4 Signal Description.......................................................................................................... 3-313.4.1 VDDR, VSSR Regulator Power Input.................................................................... 3-323.4.2 VDDA, VSSA Regulator Reference Input ............................................................. 3-323.4.3 VDD2.5, VSS2.5 Regulator Output 1 (Core Logic)............................................... 3-323.4.4 VDDPLL, VSSPLL Regulator Output 2 (PLL)...................................................... 3-323.5 Memory Map / Register Definition ............................................................................... 3-323.5.1 Register Descriptions................................................................................................. 3-333.5.1.1 VREG High Temperature Control Register (VREGHTCL).................................. 3-333.5.1.2 VREG Control Register (VREGCTRL) ................................................................ 3-333.5.1.3 VREG Autonomous Periodic Interrupt Control Register (VREGAPICL)............ 3-343.5.1.4 VREG Autonomous Periodic Interrupt Trimming Register (VREGAPITR)........ 3-353.6 Functional Description................................................................................................... 3-363.6.1 REG Regulator Core............................................................................................... 3-36


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3.6.1.1 Full Performance Mode ......................................................................................... 3-363.6.1.2 Reduced Power Mode............................................................................................ 3-373.6.2 LVD Low Voltage Detect........................................................................................ 3-373.6.3 POR Power-On Reset ............................................................................................. 3-373.6.4 LVR Low Voltage Reset ......................................................................................... 3-373.6.5 CTRL Regulator Control ........................................................................................ 3-373.6.6 API Autonomous Periodic Interrupt ....................................................................... 3-373.6.7 Resets ......................................................................................................................... 3-383.6.7.1 Power-On Reset (POR).......................................................................................... 3-383.6.7.2 Low-Voltage Reset (LVR) ..................................................................................... 3-383.6.8 Interrupts.................................................................................................................... 3-383.6.8.1 LVI Low Voltage Interrupt.................................................................................. 3-383.6.8.2 API Autonomous Periodic Interrupt................................................................... 3-393.7 Initialization / Application Information......................................................................... 3-393.7.1 Circuit Board Layout ................................................................................................. 3-39

Chapter 4 System Clocks Module (OSC and CRG)

4.1 Overview........................................................................................................................ 4-454.2 On-Chip Oscillator (OSC) Module................................................................................ 4-474.2.1 OSC Overview........................................................................................................... 4-474.2.2 OSC Features ............................................................................................................. 4-474.2.3 OSC Modes of Operation .......................................................................................... 4-484.2.4 OSC Signal Description............................................................................................. 4-484.2.4.1 VDDPLL, VSSPLL ................................................................................................. 4-484.2.4.2 EXTAL, XTAL ...................................................................................................... 4-484.2.4.3 CLKOUT / XCLKS............................................................................................... 4-494.2.5 OSC Functional Description...................................................................................... 4-504.2.5.1 Gain control ........................................................................................................... 4-504.2.5.2 Clock Monitor........................................................................................................ 4-504.3 Clock and Reset Generator (CRG) Module ................................................................... 4-504.3.1 CRG Overview .......................................................................................................... 4-504.3.2 CRG Features............................................................................................................. 4-514.3.3 CRG Modes of Operation .......................................................................................... 4-524.3.4 CRG Signal Description ............................................................................................ 4-524.3.4.1 XFC........................................................................................................................ 4-524.3.4.2 RESET ................................................................................................................... 4-534.3.4.3 CLKOUT / XCLKS............................................................................................... 4-534.3.5 CRG Memory Map / Register Definition .................................................................. 4-53


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4.3.5.1 CRG Synthesizer Register (SYNR)....................................................................... 4-544.3.5.2 CRG Reference Divider Register (REFDV).......................................................... 4-544.3.5.3 CRG Flags Register (CRGFLG)............................................................................ 4-554.3.5.4 CRG Interrupt Enable Register (CRGINT) ........................................................... 4-564.3.5.5 CRG Clock Select Register (CLKSEL)................................................................. 4-574.3.5.6 CRG PLL Control Register (PLLCTL) ................................................................. 4-584.3.5.7 CRG Stop/Doze Control Register (SDMCTL)...................................................... 4-594.3.5.8 CRG BDM Control Register (BDMCTL) ............................................................. 4-604.3.6 CRG Functional Description ..................................................................................... 4-604.3.6.1 Phase Locked Loop (PLL)..................................................................................... 4-604.3.6.2 System Clocks Generator ...................................................................................... 4-634.3.6.3 Clock Monitor (CM).............................................................................................. 4-644.3.6.4 Clock Quality Checker .......................................................................................... 4-644.3.6.5 Software Watchdog Timer (SWT) ......................................................................... 4-664.3.6.6 Real Time Interrupt (RTI)...................................................................................... 4-664.3.6.7 Resets..................................................................................................................... 4-664.3.6.8 Software Watchdog Timer (SWT) Reset ............................................................... 4-694.3.6.9 Interrupts................................................................................................................ 4-704.3.6.10 CRG Operating Mode Details ............................................................................... 4-704.4 System Clocks Summary ............................................................................................... 4-81

Chapter 5 Resets

5.1 Effects of Reset .............................................................................................................. 5-835.1.1 I/O pins ...................................................................................................................... 5-835.1.2 Memory...................................................................................................................... 5-835.2 Keyboard Wake-up on Port Pins.................................................................................... 5-83

Chapter 6 Exceptions

6.1 Exception Vector Assignments ...................................................................................... 6-85

Chapter 7 Modes of Operation

7.1 Chip Hardware Configuration Summary....................................................................... 7-877.1.1 MCU Mode Selection ................................................................................................ 7-87


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7.1.1.1 Expanded Modes ................................................................................................... 7-887.1.1.2 Single-Chip Modes ................................................................................................ 7-887.1.1.3 Data Flash Boot Mode ........................................................................................... 7-887.1.2 Oscillator Type Selection........................................................................................... 7-887.1.3 External Bus Interface Configuration ........................................................................ 7-887.1.4 Nexus Port Configuration .......................................................................................... 7-887.2 Security .......................................................................................................................... 7-897.2.1 Securing the Microcontroller ..................................................................................... 7-897.2.2 Operation of the Secured Microcontroller ................................................................. 7-897.2.2.1 Secured Single-Chip Mode.................................................................................... 7-897.2.2.2 Secured Expanded Mode ....................................................................................... 7-897.2.3 Unsecuring the Microcontroller................................................................................. 7-907.2.3.1 Backdoor Access Key............................................................................................ 7-907.2.3.2 Lockout Recovery Procedure ................................................................................ 7-907.3 Power Consumption Considerations.............................................................................. 7-907.3.1 Run Mode .................................................................................................................. 7-917.3.2 Doze Mode................................................................................................................. 7-917.3.3 Stop Mode.................................................................................................................. 7-917.3.4 Pseudo-Stop Mode..................................................................................................... 7-917.4 Mode and Configuration Identification ......................................................................... 7-91

Chapter 8 Device Memory Map

8.1 Memory Map Details ..................................................................................................... 8-938.1.1 Normal Single-Chip Mode......................................................................................... 8-958.1.2 Secured Single-Chip Mode........................................................................................ 8-958.1.3 Normal Expanded Mode............................................................................................ 8-968.1.4 Secured Expanded Mode ........................................................................................... 8-978.1.5 Normal/Secured Data Flash Boot Mode.................................................................... 8-978.1.6 Peripheral Bus Memory Map..................................................................................... 8-998.2 Accessing Registers ..................................................................................................... 8-1008.2.1 32-Bit Register Accesses ......................................................................................... 8-1008.2.2 16-Bit Register Accesses ......................................................................................... 8-1008.2.3 8-Bit Register Accesses ........................................................................................... 8-100

Chapter 9 ARM7TDMI-S Processor Core

9.1 Overview...................................................................................................................... 9-101


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Chapter 10 Interrupt Controller Module (INTC)

10.1 Overview.................................................................................................................... 10-10310.2 Features ...................................................................................................................... 10-10410.3 Review of ARM7 Interrupt Architecture ............................................................... 10-10410.4 Signal Description...................................................................................................... 10-10510.4.1 XIRQ...................................................................................................................... 10-10510.4.2 IRQ......................................................................................................................... 10-10510.5 Memory Map / Register Definition ........................................................................... 10-10510.5.1 Register Descriptions............................................................................................. 10-10810.5.1.1 INTC Interrupt Pending Register (IPRH, IPRL) ............................................... 10-10810.5.1.2 INTC Interrupt Mask Register (IMRH, IMRL)................................................. 10-10910.5.1.3 INTC Force Interrupt Register (INTFRCH, INTFRCL) ................................... 10-11010.5.1.4 INTC Module Configuration Register (ICONFIG)............................................10-11110.5.1.5 INTC Set Interrupt Mask Register (SIMR) ....................................................... 10-11210.5.1.6 INTC Clear Interrupt Mask Register (CIMR) ................................................... 10-11210.5.1.7 INTC Current Level Mask Register (CLMASK) .............................................. 10-11310.5.1.8 INTC Saved Level Mask Register (SLMASK) ................................................. 10-11410.5.1.9 INTC Interrupt Control Registers (ICRn).......................................................... 10-11510.5.1.10 INTC IRQ Acknowledge Register (IRQIACK) ................................................ 10-11510.5.1.11 INTC FIQ Acknowledge Register (FIQIACK) ................................................. 10-11610.6 Functional Description............................................................................................... 10-11610.6.1 Interrupt Recognition............................................................................................. 10-11710.6.2 Interrupt Prioritization and Level Masking ........................................................... 10-11710.6.3 Vector Generation During IACK ........................................................................... 10-11710.7 Initialization / Application Information..................................................................... 10-11910.7.1 Typical Applications .............................................................................................. 10-11910.7.2 Interrupt Service Routines ..................................................................................... 10-11910.7.3 Performance ........................................................................................................... 10-121

Chapter 11 Miscellaneous Control Module (MCM)

11.1 Overview.................................................................................................................... 11-12311.2 Features ...................................................................................................................... 11-12311.3 Memory Map / Register Definition ........................................................................... 11-12311.3.1 Register Descriptions............................................................................................. 11-12411.3.1.1 MCM Processor Core Type Register (PCT)...................................................... 11-12411.3.1.2 MCM Device Revision Register (REV) ............................................................ 11-125


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11.3.1.3 MCM XBS Master Configuration Register (AMC) .......................................... 11-12611.3.1.4 MCM XBS Slave Configuration Register (ASC).............................................. 11-12611.3.1.5 MCM IPS On-Platform Module Configuration Register (IOPMC) .................. 11-12611.3.1.6 MCM Reset Status Register (MRSR)................................................................ 11-12711.3.1.7 MCM Wake-up Control Register (MWCR) ...................................................... 11-12811.3.1.8 MCM Software Watchdog Timer Control Register (MSWTCR)...................... 11-12911.3.1.9 MCM Software Watchdog Timer Service Register (MSWTSR) ...................... 11-13111.3.1.10 MCM Software Watchdog Timer Interrupt Register (MSWTIR) ..................... 11-13211.3.1.11 MCM XBS Address Map Register (AAMR) .................................................... 11-13211.3.1.12 MCM Core Fault Address Register (CFADR) .................................................. 11-13511.3.1.13 MCM Core Fault Location Register (CFLOC) ................................................. 11-13611.3.1.14 MCM Core Fault Attributes Register (CFATR) ................................................ 11-13711.3.1.15 MCM Core Fault Data Register (CFDTR) ........................................................ 11-13811.4 Initialization / Application Information..................................................................... 11-13811.4.1 Using The PCT And REV Registers...................................................................... 11-138

Chapter 12 Enhanced Direct Memory Access Controller Module (eDMA)

12.1 Overview.................................................................................................................... 12-14112.2 Features ...................................................................................................................... 12-14312.3 Memory Map / Register Definition ........................................................................... 12-14312.3.1 Register Descriptions............................................................................................. 12-14412.3.1.1 eDMA Control Register (DMACR) .................................................................. 12-14412.3.1.2 eDMA Error Status Register (DMAES) ............................................................ 12-14512.3.1.3 eDMA Enable Request Register (DMAERQ)................................................... 12-14712.3.1.4 eDMA Enable Error Interrupt Registers (DMAEEI)......................................... 12-14812.3.1.5 eDMA Set Enable Request Register (DMASERQ)........................................... 12-14912.3.1.6 eDMA Clear Enable Request Register (DMACERQ)....................................... 12-14912.3.1.7 eDMA Set Enable Error Interrupt Register (DMASEEI).................................. 12-15012.3.1.8 eDMA Clear Enable Error Interrupt Register (DMACEEI).............................. 12-15012.3.1.9 eDMA Clear Interrupt Request Register (DMACINT) ..................................... 12-15112.3.1.10 eDMA Clear Error Register (DMACERR) ....................................................... 12-15212.3.1.11 eDMA Set START Bit Register (DMASSRT) .................................................. 12-15212.3.1.12 eDMA Clear DONE Status Register (DMACDNE).......................................... 12-15312.3.1.13 eDMA Interrupt Request Register (DMAINT) ................................................. 12-15312.3.1.14 eDMA Error Register (DMAERR).................................................................... 12-15412.3.1.15 eDMA Channel Priority Registers (DCHPRIn) ................................................ 12-15512.3.1.16 Transfer Control Descriptors (TCDn)................................................................ 12-15612.4 Functional Description............................................................................................... 12-163


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12.4.1 eDMA Microarchitecture....................................................................................... 12-16312.4.2 eDMA Basic Data Flow......................................................................................... 12-16412.5 Initialization / Application Information..................................................................... 12-16712.5.1 eDMA Transfer Control Descriptor Header File Example.................................... 12-16712.5.2 eDMA Basic Channel Operation ........................................................................... 12-16812.5.3 eDMA Initialization Sequence............................................................................... 12-17112.5.4 eDMA Programming Errors .................................................................................. 12-17312.5.5 eDMA Arbitration Mode Considerations .............................................................. 12-17312.5.5.1 Fixed-Priority Arbitration.................................................................................. 12-17412.5.5.2 Round-Robin Arbitration................................................................................... 12-17412.5.6 eDMA Transfers .................................................................................................... 12-17412.5.6.1 Single Request ................................................................................................... 12-17412.5.6.2 Multiple Requests .............................................................................................. 12-17512.5.6.3 Modulo Operation.............................................................................................. 12-17612.5.7 eDMA TCDn Status Monitoring ........................................................................... 12-17712.5.7.1 Minor Loop Complete ....................................................................................... 12-17712.5.7.2 Active Channel TCDn Reads............................................................................. 12-17812.5.7.3 Preemption Status .............................................................................................. 12-17812.5.8 Channel Linking .................................................................................................... 12-17812.5.9 Dynamic Channel Linking and Scatter/Gather Operation..................................... 12-180

Chapter 13 External Interface Module (EIM)

13.1 Overview.................................................................................................................... 13-18113.2 Features ...................................................................................................................... 13-18213.3 Modes of Operation ................................................................................................... 13-18213.4 Signal Description...................................................................................................... 13-18313.4.1 CLKOUT ............................................................................................................... 13-18313.4.2 Address Bus (ADDR[21:0]) .................................................................................. 13-18313.4.3 Data Bus (DATA[15:0])......................................................................................... 13-18313.4.4 Read/Write Signal (R/W)....................................................................................... 13-18413.4.5 Address Strobe (AS) .............................................................................................. 13-18413.4.6 Transfer Acknowledge (TA) .................................................................................. 13-18413.4.7 Output Enable (OE) ............................................................................................... 13-18413.4.8 Chip Selects (CS[2:0]) ........................................................................................... 13-18413.4.9 Byte Selects (BS[1:0]) ........................................................................................... 13-18413.5 Memory Map / Register Definition ........................................................................... 13-18513.5.1 Register Descriptions............................................................................................. 13-18513.5.1.1 EIM Chip Select Address Registers (CSARn) .................................................. 13-185


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13.5.1.2 EIM Chip Select Mask Registers (CSMRn) ...................................................... 13-18613.5.1.3 EIM Chip Select Control Registers (CSCRn) ................................................... 13-18713.6 Functional Description............................................................................................... 13-18913.6.1 Chip Select Operation............................................................................................ 13-18913.6.1.1 8- and 16-Bit Port Sizing ................................................................................... 13-19113.6.1.2 Global Chip Select............................................................................................. 13-19113.6.2 External Bus Operation.......................................................................................... 13-19213.6.2.1 Data Transfers.................................................................................................... 13-19213.6.2.2 Bus Cycle Execution.......................................................................................... 13-19313.6.2.3 Data Transfer Cycle States................................................................................. 13-19413.6.2.4 Read Cycle......................................................................................................... 13-19513.6.2.5 Write Cycle ........................................................................................................ 13-19613.6.2.6 Fast Termination Cycles .................................................................................... 13-19713.6.2.7 Back-to-Back Bus Cycles .................................................................................. 13-19813.6.2.8 Burst Cycles....................................................................................................... 13-19813.7 Initialization / Application Information..................................................................... 13-20113.7.1 Using Global Chip Select Mode ............................................................................ 13-20113.7.2 Configuring Chip Selects....................................................................................... 13-20113.7.3 Dynamic Chip Select Configuration...................................................................... 13-202

Chapter 14 Cross-Bar Switch Module (XBS)

14.1 Overview.................................................................................................................... 14-20314.2 Features ...................................................................................................................... 14-20314.3 Modes of Operation ................................................................................................... 14-20414.4 Memory Map / Register Definition ........................................................................... 14-20414.4.1 Register Descriptions............................................................................................. 14-20514.4.1.1 XBS Priority Registers (PR_port) ..................................................................... 14-20514.4.1.2 XBS Control Registers (CR_port)..................................................................... 14-20614.5 Functional Description............................................................................................... 14-20714.5.1 Arbitration.............................................................................................................. 14-20714.5.1.1 Fixed-Priority Operation.................................................................................... 14-20714.5.1.2 Round-Robin Priority Operation ....................................................................... 14-20814.5.1.3 Priority Assignment ........................................................................................... 14-20814.6 Initialization / Application Information..................................................................... 14-208


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Chapter 15 Common Flash Module (CFM)

15.1 Overview.................................................................................................................... 15-20915.2 Features ...................................................................................................................... 15-21115.3 Memory Map / Register Definition ........................................................................... 15-21215.3.1 Register Descriptions............................................................................................. 15-21415.3.1.1 CFM Module Configuration Register (CFMMCR)........................................... 15-21415.3.1.2 CFM Clock Divider Register (CFMCLKD)...................................................... 15-21615.3.1.3 CFM Security Register (CFMSEC)................................................................... 15-21715.3.1.4 CFM Program Flash Protection Register (CFMPROT) .................................... 15-21815.3.1.5 CFM Data Flash Protection Register (CFMDFPROT) ..................................... 15-22015.3.1.6 CFM Program Flash Supervisor Access Register (CFMSACC)....................... 15-22115.3.1.7 CFM Data Flash Supervisor Access Register (CFMDFSACC) ........................ 15-22115.3.1.8 CFM Program Flash Data Access Register (CFMDACC) ................................ 15-22215.3.1.9 CFM Data Flash Data Access Register (CFMDFDACC) ................................. 15-22315.3.1.10 CFM User Status Register (CFMUSTAT) ......................................................... 15-22315.3.1.11 CFM Command Register (CFMCMD).............................................................. 15-22515.3.1.12 CFM Data Registers (CFMDATA1/0)............................................................... 15-22515.3.1.13 CFM Disable Upper Block Register (CFMDISU) ............................................ 15-22615.3.1.14 CFM Clock Select Register (CFMCLKSEL) .................................................... 15-22715.4 Functional Description............................................................................................... 15-22715.4.1 Flash Normal Mode ............................................................................................... 15-22715.4.1.1 Read Operation .................................................................................................. 15-22815.4.1.2 Write Operation ................................................................................................. 15-22815.4.1.3 Command Launch Sequence ............................................................................. 15-22815.4.1.4 Initializing the CFMCLKD Register ................................................................. 15-22915.4.1.5 Program, Erase, and Verify Operations ............................................................. 15-23115.4.1.6 Flash Normal Mode Illegal Operations ............................................................. 15-24615.4.1.7 Stop Mode.......................................................................................................... 15-24615.4.2 Flash Security Operation ....................................................................................... 15-24715.4.2.1 Backdoor Access Sequence ............................................................................... 15-24715.4.2.2 Blank Check....................................................................................................... 15-24815.4.2.3 JTAG Lockout Recovery ................................................................................... 15-24815.5 Initialization / Application Information..................................................................... 15-24815.5.1 Using The Data Signature Command .................................................................... 15-248


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Chapter 16 AMBA to IP Bus Bridge Module (AIPS)

16.1 Overview.................................................................................................................... 16-25116.2 Features ...................................................................................................................... 16-25116.3 Modes of Operation ................................................................................................... 16-25116.4 Memory Map / Register Definition ........................................................................... 16-25316.4.1 Register Descriptions............................................................................................. 16-25516.4.1.1 AIPS Master Protection Registers (MPRx) ....................................................... 16-25516.4.1.2 AIPS Peripheral Access Control Registers (PACRx) ........................................ 16-25516.4.1.3 AIPS Off-Platform Peripheral Access Control Registers (OPACRx)................ 16-25616.5 Functional Description............................................................................................... 16-25716.5.1 Access Protections ................................................................................................. 16-25716.5.2 Access Support ...................................................................................................... 16-25716.5.3 Read Cycles ........................................................................................................... 16-25716.5.4 Write Cycles........................................................................................................... 16-25716.5.5 Aborted Cycles ...................................................................................................... 16-25716.6 Initialization / Application Information..................................................................... 16-258

Chapter 17 DMA Channel Multiplexer Module (DMAMux)

17.1 Overview.................................................................................................................... 17-25917.2 Features ...................................................................................................................... 17-25917.3 Modes of Operation ................................................................................................... 17-26017.4 Memory Map / Register Definition ........................................................................... 17-26017.4.1 Register Descriptions............................................................................................. 17-26117.4.1.1 DMAMux Channel Configuration Registers (CHCONFIGn)........................... 17-26117.5 Functional Description............................................................................................... 17-26217.5.1 eDMA Channels 0 to 7 .......................................................................................... 17-26317.5.2 eDMA Channels 8 to 15 ........................................................................................ 17-26417.5.3 Always Enabled DMA Request Sources ............................................................... 17-26517.6 Initialization / Application Information..................................................................... 17-26617.6.1 Simple Setup .......................................................................................................... 17-26617.6.1.1 Configure eDMA Channel 0 to Service eSCI_A Transmit Requests ................ 17-26617.6.2 Using the Always Enabled Feature to Periodically Drive GPIO Pins ............... 17-26717.6.3 Disabling a Source ................................................................................................. 17-26717.6.4 Enable Source With Periodic Triggering ............................................................... 17-26817.6.4.1 DSPI Channel Configured For Periodic Service .............................................. 17-26817.6.5 Enable Source With Transparent Triggering ......................................................... 17-268


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17.6.5.1 DSPI Channel Configured for Immediate Service ........................................... 17-26917.6.6 Switching DMA Request Source to eDMA Channel Assignment ........................ 17-26917.6.6.1 Switch eDMA Channel 9 from DSPI_A Transmit to eSCI_D Transmit........... 17-270

Chapter 18 Port Integration Module (PIM)

18.1 Overview.................................................................................................................... 18-27118.2 Features ...................................................................................................................... 18-27318.3 Modes of Operation ................................................................................................... 18-27318.4 Signal Description...................................................................................................... 18-27318.5 Memory Map / Register Definition ........................................................................... 18-27618.5.1 Register Descriptions............................................................................................. 18-28618.5.1.1 PIM Port x Pin Configuration Registers (CONFIGn_x).................................... 18-28618.5.1.2 PIM Port x Interrupt Flag Register (PORTIFR_x)............................................. 18-28718.5.1.3 PIM Port x Data Register (PORTDATA_x) ....................................................... 18-28818.5.1.4 PIM Port x Input Register (PORTIR_x)............................................................. 18-28818.5.1.5 PIM Port x Pin Data Registers (PINDATAn_x)................................................. 18-28918.5.1.6 PIM Global Interrupt Status Register (GLBINT) .............................................. 18-28918.5.1.7 PIM Global Configuration Register (PIMCONFIG)......................................... 18-29018.5.1.8 PIM Configure TDI Pin Register (CONFIG_TDI) ........................................... 18-29118.5.1.9 PIM Configure TDO Pin Register (CONFIG_TDO) ........................................ 18-29218.5.1.10 PIM Configure TMS Pin Register (CONFIG_TMS) ........................................ 18-29318.5.1.11 PIM Configure TCK Pin Register (CONFIG_TCK)......................................... 18-29418.5.1.12 PIM Configure TA / AS Pin Register (CONFIG_TA)....................................... 18-29418.5.1.13 PIM Port x/x 32-bit Input Registers (PORT32IR_xx)........................................ 18-29518.6 Functional Description............................................................................................... 18-29618.6.1 Reset....................................................................................................................... 18-29618.6.2 Peripheral Mode..................................................................................................... 18-29618.6.3 General Purpose Input Mode ................................................................................. 18-29818.6.3.1 Interrupts............................................................................................................ 18-29918.6.4 General Purpose Output Mode .............................................................................. 18-30118.7 Initialization / Application Information..................................................................... 18-30318.7.1 Using a Pin in Peripheral Mode............................................................................. 18-30318.7.1.1 PIM Example Enable the I2C module .......................................................... 18-30318.7.2 Using a Pin in GPIO Mode .................................................................................... 18-30418.7.2.1 GPIO Mode Initialization .................................................................................. 18-30418.7.2.2 PIM Example Use PB[1:0] in GPO/GPI Mode ............................................ 18-30418.7.2.3 Accessing Data .................................................................................................. 18-30518.7.2.4 Using Port Interrupts.......................................................................................... 18-309


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18.7.3 PD2 / CLKOUT Configuration.............................................................................. 18-31318.7.3.1 Using PD2 GPI Functionality............................................................................ 18-31318.7.3.2 Using CLKOUT Functionality .......................................................................... 18-31318.7.4 TA / AS Configuration........................................................................................... 18-31418.7.5 E-ICE JTAG Port Configuration............................................................................ 18-31418.7.6 Using the PIMCONFIG Register........................................................................... 18-31418.7.6.1 Using the PORTHSEL Bit ................................................................................. 18-31518.7.6.2 Using the EIMCLKEN Bit ................................................................................ 18-31518.7.7 Minimizing Power Consumption........................................................................... 18-315

Chapter 19 Analog-to-Digital Converter Module (ATD)

19.1 Overview.................................................................................................................... 19-31719.2 Features ...................................................................................................................... 19-31819.3 Modes of Operation ................................................................................................... 19-31919.4 Signal Description...................................................................................................... 19-31919.4.1 ANn_x .................................................................................................................... 19-32019.4.2 VRH / VRL .............................................................................................................. 19-32019.4.3 VDDA / VSSA......................................................................................................... 19-32019.5 Memory Map / Register Definition ........................................................................... 19-32019.5.1 Register Descriptions............................................................................................. 19-32119.5.1.1 ATD Trigger Control Register (ATDTRIGCTL)............................................... 19-32119.5.1.2 ATD External Trigger Channel Register (ATDETRIGCH)............................... 19-32219.5.1.3 ATD Prescaler Register (ATDPRE)................................................................... 19-32319.5.1.4 ATD Operating Mode Register (ATDMODE)................................................... 19-32419.5.1.5 ATD Interrupt Register (ATDINT) .................................................................... 19-32519.5.1.6 ATD Flag Register (ATDFLAG) ....................................................................... 19-32619.5.1.7 ATD Command Word Register (ATDCW)........................................................ 19-32819.5.1.8 ATD Result Register (ATDRR) ......................................................................... 19-33019.6 Functional Description............................................................................................... 19-33319.6.1 General................................................................................................................... 19-33319.6.2 Analog Sub-Module............................................................................................... 19-33319.6.2.1 Analog Input Multiplexer .................................................................................. 19-33319.6.2.2 Sample Buffer Amplifier ................................................................................... 19-33319.6.2.3 Sample and Hold Machine................................................................................. 19-33419.6.2.4 DAC................................................................................................................... 19-33419.6.2.5 Comparator ........................................................................................................ 19-33419.6.2.6 Schmitt Trigger .................................................................................................. 19-33419.6.3 Digital Sub-Module ............................................................................................... 19-334


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19.6.3.1 Mode / Timing Control ...................................................................................... 19-33419.6.3.2 Clock Prescaler .................................................................................................. 19-33419.6.3.3 IPS Bus Interface ............................................................................................... 19-33519.6.3.4 SYSTRIG0, SYSTRIG1, External Trigger Input .............................................. 19-33519.6.4 ATD Operating Mode Details ................................................................................ 19-33519.6.4.1 ATD Normal Mode ............................................................................................ 19-33519.6.4.2 ATD Debug Mode.............................................................................................. 19-33519.6.4.3 ATD Disabled Mode .......................................................................................... 19-33619.6.4.4 ATD Doze Mode................................................................................................ 19-33619.6.4.5 ATD Stop Mode ................................................................................................. 19-33719.6.5 Conversion process ................................................................................................ 19-33719.6.6 Reset....................................................................................................................... 19-34019.6.7 Interrupts................................................................................................................ 19-34019.7 Initialization / Application Information..................................................................... 19-34119.7.1 ATD Initialization Sequence.................................................................................. 19-34119.7.2 ATD Example 1 Simple Conversion................................................................. 19-34119.7.3 ATD Example 2 Three Consecutive Conversions ............................................ 19-34219.7.4 ATD Example 3 Interrupted Continuous Conversion....................................... 19-34319.7.5 ATD Example 4 Edge Triggered Conversion ................................................... 19-34319.7.6 ATD Example 5 Level Triggered Conversion .................................................. 19-34419.7.7 ATD Example 6 Using External Triggers ......................................................... 19-34519.7.8 ATD Example 7 Using System Triggers........................................................... 19-34519.7.9 Conversion Mechanism CWCH, CWNF, CWGI and CWSC Bits................... 19-34619.7.10 Conversion Mechanism CWSL, CWSB and CW8 Bits ................................... 19-34719.7.11 Measuring Internal Reference Voltages ................................................................. 19-348

Chapter 20 Enhanced Modular I/O Subsystem Module (eMIOS)

20.1 Overview.................................................................................................................... 20-35120.2 Features ...................................................................................................................... 20-35220.3 Modes of Operation ................................................................................................... 20-35220.4 Signal Description...................................................................................................... 20-35320.4.1 emiosin eMIOS Unified Channel n Input Signal.............................................. 20-35320.4.2 emioson eMIOS Unified Channel n Output Signal .......................................... 20-35320.5 Memory Map / Register Definition ........................................................................... 20-35320.5.1 Register Descriptions............................................................................................. 20-35420.5.1.1 eMIOS Module Configuration Register (MCR)................................................ 20-35420.5.1.2 eMIOS Global Flag Register (GFLAG) ............................................................ 20-35520.5.1.3 eMIOS Output Update Disable Register (OUDIS) ........................................... 20-356


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20.5.1.4 eMIOS Channel Disable Register (UCDIS) ...................................................... 20-35620.5.1.5 eMIOS Channel A Data Registers (UCAn)....................................................... 20-35720.5.1.6 eMIOS Channel B Data Registers (UCBn) ....................................................... 20-35820.5.1.7 eMIOS Channel Counter Registers (UCCNTn) ................................................ 20-35920.5.1.8 eMIOS Channel Control Registers (UCCRn).................................................... 20-35920.5.1.9 eMIOS Channel Status Registers (UCSRn) ...................................................... 20-36320.6 Functional Description............................................................................................... 20-36420.6.1 eMIOS Operating Mode Details ............................................................................ 20-36420.6.1.1 eMIOS Normal Mode ........................................................................................ 20-36420.6.1.2 eMIOS Debug Mode.......................................................................................... 20-36520.6.1.3 eMIOS Disabled Mode ...................................................................................... 20-36520.6.1.4 eMIOS Doze Mode............................................................................................ 20-36520.6.1.5 eMIOS Stop Mode ............................................................................................. 20-36520.6.2 IP Bus Interface Unit (BIU)................................................................................... 20-36520.6.2.1 Effect of Debug Mode on the BIU..................................................................... 20-36620.6.3 Global Clock Prescaler (GCP) Submodule............................................................ 20-36620.6.3.1 Effect of Debug Mode on the GCP.................................................................... 20-36620.6.4 Unified Channel (UC)............................................................................................ 20-36620.6.4.1 Effect of Debug Mode on Unified Channels ..................................................... 20-36620.6.5 Clock Prescaler (CP).............................................................................................. 20-36720.6.6 Input Programmable Filter (IPF) ........................................................................... 20-36820.6.7 UC Modes of Operation......................................................................................... 20-36820.6.7.1 General Purpose Input/Output (GPIO) Mode.................................................... 20-36920.6.7.2 Single Action Input Capture (SAIC) Mode ....................................................... 20-36920.6.7.3 Single Action Output Compare (SAOC) Mode................................................. 20-36920.6.7.4 Input Pulse Width Measurement (IPWM) Mode............................................... 20-37020.6.7.5 Input Period Measurement (IPM) Mode............................................................ 20-37120.6.7.6 Double Action Output Compare (DAOC) Mode............................................... 20-37220.6.7.7 Pulse/Edge Accumulation (PEA) Mode ............................................................ 20-37320.6.7.8 Pulse/Edge Counting (PEC) Mode .................................................................... 20-37520.6.7.9 Quadrature Decode (QDEC) Mode ................................................................... 20-37620.6.7.10 Windowed Programmable Time Accumulation (WPTA) Mode........................ 20-37820.6.7.11 Modulus Counter (MC) Mode ........................................................................... 20-37920.6.7.12 Output Pulse Width and Frequency Modulation (OPWFM) Mode................... 20-38020.6.7.13 Center Aligned Output Pulse Width Modulation (OPWMC) Mode ................. 20-38320.6.7.14 Output Pulse Width Modulation (OPWM) Mode.............................................. 20-38520.6.7.15 Modulus Counter, Buffered (MCB) Mode ........................................................ 20-38620.6.7.16 Output Pulse Width and Frequency Modulation, Buffered (OPWFMB) Mode .. 20-38920.6.7.17 Center Aligned Output Pulse Width Modulation, Buffered (OPWMCB) Mode . 20-39320.6.7.18 Output Pulse Width Modulation, Buffered (OPWMB) Mode........................... 20-39820.7 Initialization / Application Information..................................................................... 20-401


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20.7.1 Changing UC Mode Considerations ...................................................................... 20-40220.7.2 Correlated Output Signal Generation .................................................................... 20-40220.7.3 Time Base Generation............................................................................................ 20-402

Chapter 21 Enhanced Serial Communications Interface Module (eSCI)

21.1 Overview.................................................................................................................... 21-40521.2 Features ...................................................................................................................... 21-40621.2.1 LIN support............................................................................................................ 21-40621.3 Modes of Operation ................................................................................................... 21-40721.4 Signal Description...................................................................................................... 21-40721.4.1 TXD_x SCI Transmit Data ............................................................................... 21-40721.4.2 RXD_x SCI Receive Data................................................................................. 21-40721.5 Memory Map / Register Definition ........................................................................... 21-40721.5.1 Register Descriptions............................................................................................. 21-40821.5.1.1 eSCI Baud Rate Registers (ESCIBDH, ESCIBDH).......................................... 21-40821.5.1.2 eSCI Control Registers (ESCICR1 through ESCICR4) .................................... 21-40921.5.1.3 eSCI Data Registers (ESCIDRH, ESCIDRL) ................................................... 21-41421.5.1.4 eSCI Status Registers (ESCISR1, ESCISR2) .................................................... 21-41521.5.1.5 LIN Status Registers (LINSTAT1, LINSTAT2)................................................. 21-41721.5.1.6 LIN Control Registers (LINCTRL1, LINCTRL2, LINCTRL3) ....................... 21-41821.5.1.7 LIN TX Register (LINTX) ................................................................................ 21-42021.5.1.8 LIN RX Register (LINRX)................................................................................ 21-42321.5.1.9 LIN CRC Polynomial Registers (LINCRCP1, LINCRCP2)............................. 21-42321.6 Functional Description............................................................................................... 21-42421.6.1 Overview................................................................................................................ 21-42421.6.2 Data Format ........................................................................................................... 21-42421.6.3 Baud Rate Generation............................................................................................ 21-42521.6.4 Transmitter............................................................................................................. 21-42621.6.5 Transmitter Character Length ................................................................................ 21-42721.6.6 Character Transmission ......................................................................................... 21-42721.6.7 Break Characters.................................................................................................... 21-42821.6.8 Idle Characters ....................................................................................................... 21-42921.6.9 Fast Bit Error Detection......................................................................................... 21-42921.6.10 Receiver ................................................................................................................. 21-43021.6.11 Receiver Character Length .................................................................................... 21-43021.6.12 Character Reception............................................................................................... 21-43121.6.13 Data Sampling........................................................................................................ 21-43121.6.14 Framing Errors....................................................................................................... 21-435


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21.6.15 Baud Rate Tolerance.............................................................................................. 21-43521.6.15.1 Slow Data Tolerance.......................................................................................... 21-43621.6.15.2 Fast Data Tolerance ........................................................................................... 21-43721.6.16 Receiver Wake-up.................................................................................................. 21-43721.6.16.1 Idle Input Line Wake-up (WAKE = 0)............................................................... 21-43821.6.16.2 Address Mark Wake-up (WAKE = 1)................................................................ 21-43821.6.17 Single-Wire Operation ........................................................................................... 21-43821.6.18 Loop Operation ...................................................................................................... 21-43921.6.19 eSCI Operating Mode Details................................................................................ 21-43921.6.19.1 Run Mode .......................................................................................................... 21-43921.6.19.2 Doze Mode......................................................................................................... 21-43921.6.19.3 Module Disable.................................................................................................. 21-44021.6.19.4 Stop Mode.......................................................................................................... 21-44021.6.20 Interrupt Operation ................................................................................................ 21-44021.6.20.1 Interrupt Flags and Masks ................................................................................. 21-44021.7 Initialization / Application Information..................................................................... 21-44121.7.1 Using the eSCI in 9-bit Data Mode ....................................................................... 21-44121.7.2 Using the LIN hardware ........................................................................................ 21-44221.7.2.1 LIN Setup........................................................................................................... 21-44321.7.2.2 Features of the LIN Hardware ........................................................................... 21-44321.7.2.3 Generating a TX frame ...................................................................................... 21-44421.7.2.4 Generating an RX frame.................................................................................... 21-44521.7.2.5 LIN Error Handling ........................................................................................... 21-44621.7.2.6 LIN Wake-up ..................................................................................................... 21-44721.7.2.7 System Wake-up on LIN Bus Activity .............................................................. 21-447

Chapter 22 Deserial Serial Peripheral Interface Module (DSPI)

22.1 Overview.................................................................................................................... 22-44922.2 Features ...................................................................................................................... 22-45022.3 Modes of Operation ................................................................................................... 22-45122.4 Signal Description...................................................................................................... 22-45122.4.1 PCS0_x / SS_x Peripheral Chip Select or Slave Select .................................... 22-45222.4.2 PCS[1:4, 6:7]_x Peripheral Chip Selects 14, 67 ........................................... 22-45222.4.3 PCS5_x / PCSS_x Peripheral Chip Select 5 or Chip Select Strobe .................. 22-45222.4.4 SIN_x Serial Input ............................................................................................ 22-45222.4.5 SOUT_x Serial Output...................................................................................... 22-45222.4.6 SCK_x Serial Clock .......................................................................................... 22-45222.5 Memory Map / Register Definition ........................................................................... 22-452


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22.5.1 Register Descriptions............................................................................................. 22-45322.5.1.1 DSPI Module Configuration Register (DSPIx_MCR) ...................................... 22-45322.5.1.2 DSPI Transfer Count Register (DSPIx_TCR) ................................................... 22-45622.5.1.3 DSPI Clock and Transfer Attributes Registers (DSPIx_CTARn)...................... 22-45722.5.1.4 DSPI Status Register (DSPIx_SR)..................................................................... 22-46222.5.1.5 DSPI DMA/Interrupt Request Select / Enable Register (DSPIx_RSER).......... 22-46422.5.1.6 DSPI PUSH TX FIFO Register (DSPIx_PUSHR) ............................................ 22-46622.5.1.7 DSPI POP RX FIFO Register (DSPIx_POPR).................................................. 22-46722.5.1.8 DSPI Transmit FIFO Registers (DSPIx_TXFRn) ............................................. 22-46822.5.1.9 DSPI Receive FIFO Registers (DSPIx_RXFRn)............................................... 22-46822.6 Functional Description............................................................................................... 22-46922.6.1 DSPI Operating Mode Details ............................................................................... 22-47022.6.1.1 DSPI Master Mode ............................................................................................ 22-47022.6.1.2 DSPI Slave Mode .............................................................................................. 22-47122.6.1.3 DSPI Disabled Mode ......................................................................................... 22-47122.6.1.4 DSPI Stop Mode ................................................................................................ 22-47122.6.1.5 DSPI Debug Mode............................................................................................. 22-47122.6.2 Start and Stop of DSPI Transfers ........................................................................... 22-47222.6.3 Serial Peripheral Interface (SPI) Configuration..................................................... 22-47222.6.3.1 Master Mode...................................................................................................... 22-47322.6.3.2 Slave Mode ........................................................................................................ 22-47322.6.3.3 FIFO Disable Operation .................................................................................... 22-47322.6.3.4 Transmit First In First Out (TX FIFO) Buffering Mechanism .......................... 22-47322.6.3.5 Receive First In First Out (RX FIFO) Buffering Mechanism ........................... 22-47422.6.4 DSPI Baud Rate and Clock Delay Generation ...................................................... 22-47522.6.4.1 Baud Rate Generator.......................................................................................... 22-47522.6.4.2 PCS to SCK Delay (tCSC) .................................................................................. 22-47622.6.4.3 After SCK Delay (tASC)..................................................................................... 22-47622.6.4.4 Delay after Transfer (tDT) .................................................................................. 22-47622.6.4.5 Peripheral Chip Select Strobe Enable (PCSS)................................................... 22-47722.6.5 Transfer Formats.................................................................................................... 22-47822.6.5.1 Classic SPI Transfer Format (CPHA = 0) ......................................................... 22-47922.6.5.2 Classic SPI Transfer Format (CPHA = 1) ......................................................... 22-47922.6.5.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0) ................................... 22-48022.6.5.4 Modified SPI Transfer Format (MTFE = 1, CPHA = 1) ................................... 22-48122.6.5.5 Continuous Selection Format ............................................................................ 22-48222.6.6 Continuous Serial Communications Clock............................................................ 22-48322.6.7 Interrupts/DMA Requests ...................................................................................... 22-48422.6.7.1 End of Queue Interrupt Request ........................................................................ 22-48522.6.7.2 Transmit FIFO Fill Interrupt or DMA Request ................................................. 22-48522.6.7.3 Transfer Complete Interrupt Request ................................................................ 22-485


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22.6.7.4 Transmit FIFO Underflow Interrupt Request .................................................... 22-48522.6.7.5 Receive FIFO Drain Interrupt or DMA Request ............................................... 22-48522.6.7.6 Receive FIFO Overflow Interrupt Request........................................................ 22-48622.7 Initialization / Application Information..................................................................... 22-48622.7.1 Changing Queues................................................................................................... 22-48622.7.2 Baud Rate Settings................................................................................................. 22-48722.7.3 Delay Settings ........................................................................................................ 22-48722.7.4 Calculation of FIFO Pointer Addresses ................................................................. 22-48822.7.4.1 Address Calculation for First-in Entry / Last-in Entry in RX FIFO.................. 22-489

Chapter 23 Controller Area Network Module (FlexCAN)

23.1 Overview.................................................................................................................... 23-49123.1.1 References.............................................................................................................. 23-49123.2 Features ...................................................................................................................... 23-49223.3 Modes of Operation ................................................................................................... 23-49323.4 Signal Description...................................................................................................... 23-49423.4.1 CNRX_x................................................................................................................. 23-49423.4.2 CNTX_x................................................................................................................. 23-49423.5 Memory Map / Register Definition ........................................................................... 23-49423.5.1 Message Buffer Structure ...................................................................................... 23-49523.5.2 Register Descriptions............................................................................................. 23-49823.5.2.1 FlexCAN Module Configuration Register (MCR) ............................................ 23-49823.5.2.2 FlexCAN Control Register (CTRL) .................................................................. 23-50123.5.2.3 FlexCAN Timer Register (TIMER)................................................................... 23-50423.5.2.4 Rx Mask Registers............................................................................................. 23-50423.5.2.5 FlexCAN Error Counter Register (ECR)........................................................... 23-50623.5.2.6 FlexCAN Error and Status Register (ESR)........................................................ 23-50723.5.2.7 FlexCAN Interrupt Mask Register (IMASK) .................................................... 23-51023.5.2.8 FlexCAN Interrupt Flags Register (IFLAG) ..................................................... 23-51123.6 Functional Description............................................................................................... 23-51123.6.1 Overview................................................................................................................ 23-51123.6.2 Transmit Process.................................................................................................... 23-51223.6.3 Arbitration Process ................................................................................................ 23-51223.6.4 Receive Process ..................................................................................................... 23-51323.6.5 Matching Process................................................................................................... 23-51423.6.6 Data Coherence...................................................................................................... 23-51423.6.6.1 Message Buffer Deactivation............................................................................. 23-51423.6.6.2 Message Buffer Lock Mechanism ..................................................................... 23-515


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23.6.7 CAN Protocol Related Features............................................................................. 23-51623.6.7.1 Remote Frames .................................................................................................. 23-51623.6.7.2 Overload Frames................................................................................................ 23-51623.6.7.3 Time Stamp........................................................................................................ 23-51623.6.7.4 Protocol Timing ................................................................................................. 23-51723.6.7.5 Arbitration and Matching Timing...................................................................... 23-51823.6.8 FlexCAN Operating Mode Deta

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