mach 5 cpld family

Publication#

20446

Rev:

J

Amendment/

0

Issue Date:

April 2002

MACH 5 CPLD FamilyFifth Generation MACH Architecture

Select devices have been discontinued. See O

rdering Information section for product status.

FEATURES◆ High logic densities and I/Os for increased logic integration

— 128 to 512 macrocell densities— 68 to 256 I/Os

◆ Wide selection of density and I/O combinations to support most application needs— 6 macrocell density options— 7 I/O options — Up to 4 I/O options per macrocell density— Up to 5 density & I/O options for each package

◆ Performance features to fit system needs— 5.5 ns tPD Commercial, 7.5 ns tPD Industrial— 182 MHz fCNT— Four programmable power/speed settings per block

◆ Flexible architecture facilitates logic design— Multiple levels of switch matrices allow for performance-based routing— 100% routability and pin-out retention— Synchronous and asynchronous clocking, including dual-edge clocking— Asynchronous product- or sum-term set or reset— 16 to 64 output enables— Functions of up to 32 product terms

◆ Advanced capabilities for easy system integration— 3.3-V & 5-V JEDEC-compliant operations— IEEE 1149.1 compliant for boundary scan testing— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port— PCI compliant (-5/-6/-7/-10/-12 speed grades)— Safe for mixed supply voltage system design— Bus-Friendly™ Inputs & I/Os— Individual output slew rate control— Hot socketing— Programmable security bit

◆ Advanced E2CMOS process provides high performance, cost effective solutions

Select devices have been discontinued.

See Ordering Inform

ation section for product status.

Note:1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.

GENERAL DESCRIPTION

The MACH® 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.

Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The 5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.

Table 1. MACH 5 Device Features 1

FeatureM5-128/1M5LV-128

M5-192/1 M5-256/1M5LV-256

M5-320M5LV-320

M5-384M5LV-384

M5-512M5LV-512

Supply Voltage (V) 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3

Macrocells 128 128 192 256 256 320 320 384 384 512 512

Maximum User I/O Pins 120 120 120 160 160 192 160 160 160 256 256

tPD (ns) 5.5 5.5 5.5 5.5 5.5 6.5 6.5 6.5 6.5 6.5 6.5

tSS (ns) 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0 3.0

tCOS (ns) 4.5 4.5 4.5 4.5 4.5 5.0 5.0 5.0 5.0 5.0 5.0

fCNT (MHz) 182 182 182 182 182 167 167 167 167 167 167

Typical Static Power (mA) 35 35 45 55 55 70 70 75 75 100 100

IEEE 1149.1 Boundary Scan Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

PCI-Compliant Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes

2 MACH 5 Family


See Ordering Inform


Note:1. C = Commercial grade, I = Industrial grade

2. /1 version recommended for new designs

With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512 macrocells to support full system logic integration. Extensive routing resources ensure pinout retention as well as high utilization. It is ideal for PAL® block device integration and a wide range of other applications including high-speed computing, low-power applications, communications, and embedded control. At each macrocell density point, Lattice offers several I/O and package options to meet a wide range of design needs (Table 3).

Note:1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.

Advanced power management options allow designers to incrementally reduce power while maintaining the level of performance needed for today’s complex designs. I/O safety features allow for mixed-voltage design,

Table 2. MACH 5 Speed Grades

Device

Speed Grade1

-5 -6 -7 -10 -12 -15 -20

M5-1282 C C, I C, I C, I I

M5-128/1 C C, I C, I C, I C, I I

M5LV-128 C C,I C, I C, I I

M5-192/1 C C, I C, I C, I C, I I

M5-2562 C C, I C, I C, I I

M5-256/1 C C, I C, I C, I C, I I

M5LV-256 C C, I C, I C, I I

M5-320 C C, I C, I C, I C, I I

M5LV-320 C C, I C, I C, I C, I I

M5-384 C C, I C, I C, I C, I I


M5-512 C C, I C, I C, I C, I I


Table 3. MACH 5 Package and I/O Options 1

M5-128/1M5LV-128 M5-192/1

M5-256/1M5LV-256

M5-320M5LV-320

M5-384M5LV-384

M5-512M5LV-512

Supply Voltage 5 3.3 5 5 3.3 5 3.3 5 3.3 5 3.3

100-pin TQFP 68 68, 74 68 68 68*, 74

100-pin PQFP 68 68* 68* 68* 68

144-pin TQFP 104 104

144-pin PQFP 104 104* 104* 104* 104*

160-pin PQFP 120 120 120 120 120 120* 120 120* 120 120* 120

208-pin PQFP 160 160 160 160 160 160 160 160

240-pin PQFP 184* 184* 184* 184* 184* 184*

256-ball BGA 192 192* 192* 192* 192* 192*

352-ball BGA 256 256

MACH 5 Family 3


See Ordering Inform


and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE 1149.1 Test Access Port (TAP) interface.

FUNCTIONAL DESCRIPTION

The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the segments together. The only logic difference between any two MACH 5 devices is the number of segments. Therefore, once a designer is familiar with one device, consistent performance can be expected across the entire family. All devices have four clock pins available which can also be used as logic inputs.

The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block resembles an independent PAL device, it has superior control and logic generation capabilities.

◆ I/O cells

◆ Product-term array and Logic Allocator

◆ Macrocells

◆ Register control generator

◆ Output enable generator

I/O Cells

The I/Os associated with each PAL block have a path directly back to that PAL block called local feedback. If the I/O is used in another PAL block, the interconnect feeder assigns a block interconnect line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide connections between any two signals in a device. The block feeder assigns block interconnect lines and local feedback lines to the PAL block inputs.

Blo

ck In

terc

onne

ct

4

CLKBlock:

16 MCs

Segment:4 Blocks

Segment Interconnect

20446G-001

Figure 1. MACH 5 Block Diagram

4 MACH 5 Family


See Ordering Inform


Product-Term Array and Logic Allocator

The product-term array uses the same sum-of-products architecture as PAL devices and consists of 32 inputs (plus their complements) and 64 product terms arranged in 16 clusters. A cluster is a sum-of-products function with either 3 of 4 product terms.

Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of three or four product terms, but a given cluster can only be steered to one macrocell (Table 4). If only three product terms in a cluster are steered, the fourth can be used as an input to an XOR gate for separate logic generation and/or polarity control.

The wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic allocation scheme in the MACH 5 device allows for the implementation of large equations (up to 32 product terms) with only one pass through the logic array.

Table 4. Product Term Steering Options for PT Clusters and Macrocells

Macrocell Available Clusters Macrocell Available Clusters

M0 C0, C1, C2, C3, C4 M8 C5, C6, C7, C8, C9, C10, C11, C12

M1 C0, C1, C2, C3, C4, C5 M9 C6, C7, C8, C9, C10, C11, C12, C13

M2 C0, C1, C2, C3, C4, C5, C6 M10 C7, C8, C9, C10, C11, C12, C13, C14

M3 C0, C1, C2, C3, C4, C5, C6, C7 M11 C8, C9, C10, C11, C12, C13, C14, C15

M4 C0, C1, C2, C3, C4, C5, C6, C7 M12 C8, C9, C10, C11, C12, C13, C14, C15

M5 C1, C2, C3, C4, C5, C6, C7, C8 M13 C9, C10, C11, C12, C13, C14, C15

M6 C2, C3, C4, C5, C6, C7, C8, C9 M14 C10, C11, C12, C13, C14, C15

M7 C3, C4, C5, C6, C7, C8, C9, C10 M15 C11, C12, C13, C14, C15

Blo

ck In

terc

onne

ct

Interconnect Feeder

BlockFeeder

32

I/Os

16

2

Mac

roce

lls

Logi

c A

loca

tor

Control Generator

OE Generator

Product-termArray

32

32

Input RegisterPath

2Loca

l Fee

dbac

k

20446G-002

Figure 2. PAL Block Structure

MACH 5 Family 5



Macrocells

The macrocells for MACH 5 devices consist of a storage element which can be configured for combinatorial, registered or latched operation (Figure 3). The D-type flip-flops can be configured as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell.

Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In order to use this option, these macrocells must be accessed via the I/O pins associated with macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it cannot be used for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be used as “buried” macrocells to drive device logic via the matrix.

Control Generator

The control generator provides four configurable clock lines and three configurable set/reset lines to each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can be independently selected by any flip-flop within a block. The clock lines can be configured to provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks, and latch enables (Figure 4). Three of the four global clocks, as well as two product-term clocks and one sum-term clock, are available per PAL block. Positive or negative edge clocking is available as well as advanced clocking features such as complementary and biphase clocking. Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful in applications such as fast data paths. A biphase clock line clocks flip-flops on both the positive and negative edges of the clock. The configuration options for the four clock lines per PAL block are as follows:

Clock Line 0 Options

◆ Global clock (0, 1, 2, or 3) with positive or negative edge clock enable

◆ Product-term clock (A*B*C)

◆ Sum-term clock (A+B+C)


◆ Global clock (0, 1, 2, or 3) with positive edge clock enable

◆ Global clock (0, 1, 2, or 3) with negative edge clock enable

LogicAllocator

5-8Clusters/

MC

Prog. PolarityMode

Selection

Con

trol

Bus

Macrocell

D Q

20446G-003

Figure 3. Macrocell Diagram

6 MACH 5 Family



◆ Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase)


◆ Global clock (0, 1, 2, or 3) with clock enable


◆ Complement of clock line 2 (same clock enable)

◆ Product-term clock (if clock line 2 does not use clock enable

The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for the PAL block. Each macrocell can choose one of these three lines or choose no set/reset at all. All three lines can be configured for product term set/reset and two of the three lines can be configured as sum term set/reset and one of the lines can be configured as product-term or sum-term latch enable. While the set/reset signals are generated in the control generator, whether that signal sets or resets a flip-flop is determined within the individual macrocell. The same signal can set one flip-flop and reset another. PT2 or /PT2 can also be used as a latch enable for macrocells configured as latches.

0123

0123

0123

CLKINClock Enable

N (0)

N (1)

OUT

MUX 2TO1

/CLK

F0

/CLK

CLK

CLKEN1BIPHASECLKEN2

OUT

CLK0

CLK1

CLK2

CLK3

CLKINClock Enable

MUX 2TO1

/CLK2

PTCLK

F0BlockClocks0–3

PT (0:3)

PINCLK (0:3)

PT0

PT1

PT2

PT3

MUX 4TO1

IN (0)IN (1)IN (2)IN (3)

OUT

U1F0 F1

MUX 4TO1

IN (0)IN (1)IN (2)IN (3)

OUT

U2F0 F1

MUX 4TO1

IN (0)IN (1)IN (2)IN (3)

OUT

U3F0 F1 MUX

2TO1

MUX 2TO1

F0

20446G-004

Figure 4. Clock Generator

SET2/RST2/LE

BlockSets/Reset0–2, LE

PT (0:2)

PT0

PT1

PT2

SET1/RST1

SET0/RST0

MUX 2TO1

OUT

F0

PT1

/PT1(ST)

MUX 2TO1

OUT

F0

PT2

/PT2

20446G-005

Figure 5. Set/Reset Generator

MACH 5 Famil
y 7



OE Generator

There is one output enable (OE) generator per PAL block that generates two product-term driven output enables. Each I/O cell is simply an output buffer. Each I/O cell within the PAL block can choose to be permanently enabled, permanently disabled, or choose one of the two product term output enables per PAL block (Figure 6).

Output EnableGenerator

VCC

Internal Feedback

External Feedback

20446G-006

Figure 6. Output Enable Generator and I/O Cell

8 MACH 5 Family



MACH 5 TIMING MODEL

The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5 device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback.

The parameter, tBUF, is defined as the time it takes to go through the output buffer to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 5 timing model is shown in Figure 7. Refer to the Technical Note entitled MACH 5 Timing and High Speed Design for a more detailed discussion about the timing parameters.

INPUT REG/�INPUT LATCH

tSIR (S/A)�tHIR (S/A)�tSIL�tHIL�tSRR�tCES�tCEH

tCO (S/A) i�tPDILi �tGOAi�tSRi��

tBLK �tSEG�

��

CE SR

(External Feedback)

(Internal Feedback)

Q

tS (S/A)�tH (S/A)�tSAL�tHAL�tSRR�tCES�tCEH

tPDi �tCO (S/A) i �tPDLi�tGOAi�tSRi��

COMB/DFF/�LATCH

CE SR

tPL1 �tPL2�tPL3�

��

IN OUT

tPT ��

tEA�tER �

��

tBUF��

tSLW��

PIN CLK

Q

20446G-014

Figure 7. MACH 5 Timing Model

MACH 5 Family 9



MULTIPLE I/O AND DENSITY OPTIONS

The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers to choose a device close to their logic density and I/O requirements, thus minimizing costs. For the same package type, every density has the same pin-out. With proper design considerations, a design can be moved to a higher or lower density part as required.

IEEE 1149.1 - COMPLIANT BOUNDARY SCAN TESTABILITY

Most MACH 5 devices have boundary scan registers and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a board-level serial scan path for more complete board-level testing.

IEEE 1149.1 - COMPLIANT IN-SYSTEM PROGRAMMING

Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All MACH 5 devices provide in-system programming (ISP) capability through their IEEE 1149.1-compliant Boundary Scan Test Access Port. By using the IEEE 1149.1-compliant Boundary Scan Test Access Port as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface.

MACH 5 devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of MACH 5 devices. LatticePRO software takes the JEDEC file output produced by design implementation software, along with information about the Boundary Scan chain, and creates a set of vectors that are used to drive the Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Scan chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equipment can then be used to program MACH 5 devices during the testing of a circuit board.

PCI COMPLIANT

MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature. MACH 5 devices provide the speed, drive, density, output enables and I/Os for the most complex PCI designs.

10 MACH 5 Family



SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS 1

Both the 3.3-V and 5-V VCC MACH 5 devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V devices will accept inputs up to 5.5 V. Both the 3.3-V and 5-V versions have the same high-speed performance and provide easy-to-use mixed-voltage design capability.

Note:1. Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please refer to Application Note titled “Hot

Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices”.

BUS-FRIENDLY INPUTS AND I/OS

All MACH 5 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is a good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level “1.” For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site.

POWER MANAGEMENT

There are 4 power/speed options in each MACH 5 PAL block (Table 5). The speed and power tradeoff can be tailored for each design. The signal speed paths in the lower-power PAL blocks will be slower than those in the higher-power PAL blocks. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in a lower-power mode. In large designs, there may be several different speed requirements for different portions of the design.

PROGRAMMABLE SLEW RATE

Each MACH 5 device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power.

POWER-UP RESET/SET

All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be monotonic and the clock must be inactive until the reset delay time has elapsed.

Table 5. Power Levels

High Speed/High Power 100% Power

Medium High Speed/Medium High Power 67% Power

Medium Low Speed/Medium Low Power 40% Power

Low Speed/Low Power 20% Power

MACH 5 Family 11



SECURITY BIT

A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device.

12 MACH 5 Family



MACH 5 PAL BLOCK0 4 8 12 16 20 24 28 32

I/O�Cell I/O

SwitchMatrix

Output Enable

Output Enable

CLK

I/O�Cell

I/O�Cell

I/O�Cell

I/O�Cell

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I/O

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16 16

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6336 40 44 48 52 56 60

0 4 8 12 16 20 24 28 32 6336 40 44 48 52 56 60

20446G-015

MACH 5 Family 13



BLOCK DIAGRAM — M5(LV)-128/XXX

Macrocells

64 x 73�AND Logic Array�

and Logic Allocator

� Control�Generator

64 PT

2 PT OE

I/O Cells

16

16

32

7 PT7

2

32

16

Macrocells


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64 PT

2 PT OE

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16

16

32

7 PT7

2

32

16

Macrocells � Control�Generator

64 PT

2 PT OE16

16

32

7 PT

72

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16

�

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and Logic Allocator


64 PT

2 PT OE16

16

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7 PT

72

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16

�

I/O Cells


and Logic Allocator

Block A/Macrocells 0-15 Block D/Macrocells 0-15

Block B/Macrocells 0-15 Block C/Macrocells 0-15

Block Interconnect

Macrocells


and Logic Allocator


64 PT

2 PT OE

I/O Cells

16

16

32

7 PT7

2

32

16

Macrocells


and Logic Allocator


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72

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and Logic Allocator

Block A/Macrocells 0-15 Block D/Macrocells 0-15

Block B/Macrocells 0-15 Block C/Macrocells 0-15

Block Interconnect

S E G M E N T I N T E R C O N N E C TCLK0�CLK1�CLK2�CLK3��

4

SEGMENT 0

SEGMENT 1

I0, 1

I2, 3

2

2

20446G-007

14 MACH 5 Family



BLOCK DIAGRAM — M5-192/XXX

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MACH 5 Family 19




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20 MACH 5 Family



ABSOLUTE MAXIMUM RATINGSM5Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Device JunctionTemperature (Note 1) . . . . . . . . . . . . . . . . +130°C or +150°CSupply Voltage with Respect to Ground . . . . . . . . . . . . . . . . .-0.5 V to +7.0 V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2000 V

Latchup Current (-40°C to +85°C) . . . . . . . . . . . . . . . 200 mA

Stresses above those listed under Absolute Maximum Ratings may cause per-manent device failure. Functionality at or above these limits is not implied. Expo-sure to Absolute Maximum Ratings for extended periods may affect devicereliability.

OPERATING RANGESCommercial (C) DevicesAmbient Temperature (TA)Operating in Free Air . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . +4.75 V to +5.25 V

Industrial (I) DevicesAmbient Temperature (TA)Operating in Free Air . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

Supply Voltage (VCC) with Respect to Ground. . . . . . . . . . . . . . . . +4.5 V to +5.5 V

Operating ranges define those limits between which the functionality of the device is guaranteed.

Note:1. 150° for M5-128, M5-192 and M5-256 devices. 130° for M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384 and M5-512 devices.

2. Total IOL between ground pins should not exceed 64 mA.

3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included.

4. I/O pin leakage is the worst case of IIL and IOZL or IIH and IOZH.

5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.

5-V DC CHARACTERISITICS OVER OPERATING RANGESParameter

Symbol Parameter Description Test Description Min Typ Max Unit

VOH

Output HIGH Voltage

(For M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384, M5-512 Devices)

IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V

IOH = -100 µA, VCC = Max, VIN = VIH or VIL 3.3 3.6 V

Output HIGH Voltage

(For M5-128, M5-192, M5-256 Devices)

IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL 2.4 V

IOH = -2.5 mA, VCC = 5.25 V, VIN = VIH or VIL 3.6 V

VOL Output LOW Voltage (Note 2) IOL = +16 mA, VCC = Min, VIN = VIH or VIL 0.5 V

VIH Input HIGH VoltageGuaranteed Input Logical HIGH Voltage for all Inputs (Note 3)

2.0 V

VIL Input LOW VoltageGuaranteed Input Logical LOW Voltage for all Inputs (Note 3)

0.8 V

IIH Input HIGH Leakage Current VIN = 5.25, VCC = Max (Note 4) 10 μA

IIL Input LOW Leakage Current VIN = 0, VCC = Max (Note 4) -10 μA

IOZH Off-State Output Leakage Current HIGH VOUT = 5.25, VCC = Max, VIN = VIH or VIL (Note 4) 10 μA

IOZL Off-State Output Leakage Current LOW VOUT = 0, VCC = Max, VIN = VIH or VIL (Note 4) -10 μA

ISC Output Short-Circuit Current VOUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 5) -30 -180 mA

MACH 5 Family 21



ABSOLUTE MAXIMUM RATINGSM5LVStorage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C

Device Junction Temperature. . . . . . . . . . . . . . . . . . . . +130°C

Supply Voltage with Respect to Ground . . . . . . . . . . . . . . . . .-0.5 V to +4.5 V

DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . . . . . 2000 V

Latchup Current (-40°C to +85°C) . . . . . . . . . . . . . . . 200 mA

Stresses above those listed under Absolute Maximum Ratings may cause per-manent device failure. Functionality at or above these limits is not implied. Expo-sure to Absolute Maximum Ratings for extended periods may affect devicereliability.

OPERATING RANGESCommercial (C) DevicesAmbient Temperature (TA)Operating in Free Air . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C


Industrial (I) DevicesAmbient Temperature (TA)Operating in Free Air . . . . . . . . . . . . . . . . . . . .-40°C to +85°C


Operating ranges define those limits between which the functionality of the device is guaranteed.

Notes:1. Total IOL between ground pins should not exceed 64 mA.

2. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included.

3. I/O pin leakage is the worst case of IIL and IOZL or IIH and IOZH.

4. Not more than one output should be shorted at one time. Duration of the short-circuit should not exceed one second.

3.3-V DC CHARACTERISITICS OVER OPERATING RANGESParameter

Symbol Parameter Description Test Description Min Max Unit

VOH Output HIGH VoltageVCC = Min IOH = -100 μA VCC -0.2 V

VIN = VIH or VIL IOH = 3.2 mA 2.4 V

VOL Output LOW VoltageVCC = Min

VIN = VIH or VIL

IOL = 100 μA 0.2 V

IOL = 16 mA (Note 1) 0.5 V

VIH Input HIGH Voltage VOUT ≥ VOH Min or VOUT ≤ VOL Max (Note 2) 2.0 5.5 V

VIL Input LOW Voltage VOUT ≥ VOH Min or VOUT ≤ VOL Max (Note 2) -0.3 0.8 V

IIH Input HIGH Leakage Current VIN = 3.6, VCC = Max (Note 3) 10 μA

IIL Input LOW Leakage Current VIN = 0, VCC = Max (Note 3) -10 μA

IOZH Off-State Output Leakage Current HIGH VOUT = 3.6, VCC = Max, VIN = VIH or VIL (Note 3) 10 μA

IOZL Off-State Output Leakage Current LOW VOUT = 0, VCC = Max, VIN = VIH or VIL (Note 3) -10 μA

ISC Output Short-Circuit Current VOUT = 0.5 VCC = Max, VIN = VIH or VIL (Note 4) -15 -160 mA

22 MACH 5 Family



M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 -5 -6 -7 -10 -12 -15 -20

UnitMin Max Min Max Min Max Min Max Min Max Min Max Min Max

Combinatorial Delay:

tPDiInternal combinatorial propagation delay

3.5 4.5 5.5 8.0 10.0 13.0 18.0 ns

tPD Combinatorial propagation delay 5.5 6.5 7.5 10.0 12.0 15.0 20.0 ns

Registered Delays:

tSS Synchronous clock setup time 3.0 3.0 4.0 5.0 6.0 8.0 10.0 ns

tSA Asynchronous clock setup time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns

tHS Synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

tHA Asynchronous clock hold time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns

tCOSi Synchronous clock to internal output 2.5 3.0 4.0 5.0 6.0 8.0 10.0 ns

tCOS Synchronous clock to output 4.5 5.0 6.0 7.0 8.0 10.0 12.0 ns

tCOAi Asynchronous clock to internal output 6.0 6.0 8.0 10.0 13.0 15.0 18.0 ns

tCOA Asynchronous clock to output 8.0 8.0 10.0 12.0 15.0 17.0 20.0 ns

Latched Delays:

tSAL Latch setup time 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns

tHAL Latch hold time 3.0 3.0 4.0 5.0 6.0 7.0 8.0 ns

tPDLi Transparent latch internal 6.0 7.0 7.0 8.0 9.0 10.0 10.0 ns

tPDLPropagation delay through transparent latch

8.0 9.0 9.0 10.0 11.0 12.0 12.0 ns

tGOAi Gate to internal output 7.0 8.0 8.0 9.0 10.0 11.0 12.0 ns

tGOA Gate to output 9.0 10.0 10.0 11.0 12.0 13.0 14.0 ns

Input Register Delays:

tSIRSInput register setup time using a synchronous clock

2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns

tSIRAInput register setup time using an asynchronous clock

0.0 0.0 0.0 0.0 0.0 0.0 0.0 ns

tHIRSInput register hold time using a synchronous clock

3.0 3.0 3.0 4.0 4.0 4.0 4.0 ns

tHIRAInput register hold time using an asynchronous clock

6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns

Input Latch Delays:

tSIL Input latch setup time 2.0 2.0 2.0 3.0 3.0 3.0 3.0 ns

tHIL Input latch hold time 6.0 6.0 6.0 7.0 7.0 7.0 7.0 ns

tPDILi Transparent input latch 5.0 5.0 5.5 6.0 6.0 6.0 6.0 ns

Output Delays:

tBUF Output buffer delay 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns

tSLW Slow slew rate delay 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns

tEA Output enable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns

tER Output disable time 7.5 7.5 9.5 10.0 12.0 15.0 20.0 ns

MACH 5 Family 23



Power Delays:

tPL1 Power level 1 delay (Note 2)4.0

(5.0)4.0

4.0 (5.0)

4.0 (5.0)

4.0 (5.0)

4.0 (5.0)

4.0 (5.0)

ns


(9.0)6.0

6.0 (9.0)

6.0 (9.0)

6.0 (9.0)

6.0 (9.0)

6.0 (9.0)

ns


(17.5)9.0

9.0 (17.5)

9.0 (17.5)

9.0 (17.5)

9.0 (17.5)

9.0 (17.5)

ns

Additional Cluster Delay:

tPT Product term cluster delay 0.3 0.3 0.3 0.3 0.3 0.3 0.3 ns

Interconnect Delays:

tBLK Block interconnect delay 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns

tSEG Segment interconnect delay 4.5 4.5 5.0 6.0 6.0 6.0 6.0 ns

Reset and Preset Delays:

tSRiAsynchronous reset or preset to internal register output

6.0 8.0 8.0 10.0 12.0 14.0 16.0 ns

tSRAsynchronous reset or preset to register output

8.0 10.0 10.0 12.0 14.0 16.0 18.0 ns

tSRR Reset and set register recovery time 5.5 7.5 7.5 8.0 9.0 10.0 11.0 ns

tSRW Asynchronous reset or preset width 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns

Clock Enable Delays:

tCES Clock enable setup time 4.0 5.0 5.0 6.0 7.0 7.0 8.0 ns

tCEH Clock enable hold time 3.0 4.0 4.0 5.0 6.0 6.0 7.0 ns

Width:

tWLS Global clock width low (Note 3) 2.5 3.0 3.0 4.0 5.0 6.0 6.0 ns

tWHS Global clock width high (Note 3) 2.5 3.0 3.0 4.0 5.0 6.0 6.0 ns

tWLA Product term clock width low 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns

tWHA Product term clock width high 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns

tGWAGate width low (for low transparent) or high (for high transparent)

3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns

tWIR Input register clock width low or high 3.0 4.0 4.0 5.0 6.0 7.0 8.0 ns

M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)-5 -6 -7 -10 -12 -15 -20


24 MACH 5 Family



Notes:1. See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site.

2. Numbers in parentheses are for M5-128, M5-192, M5-256.

3. If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (fMAX/2).

Frequency:

fMAX

External feedback, PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS)

133 125 100 83.3 71.4 55.6 45.5 MHz

Internal feedback, PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS +tCOSi)

182 167 125 100 83.3 62.5 50.0 MHz

No feedback PAL block level. Min of 1/(tWLS + tWHS) or 1/(tSS + tHS)

200 167 167 125 100 83.3 83.3 MHz

fMAXA

External feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA + tCOA)

91 91 71.4 58.8 47.6 41.7 35.7 MHz

Internal feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA +tCOAi)

111 111 83.3 66.7 52.6 45.5 38.5 MHz

No feedback, PAL block level. Min of 1/(tWLA + tWHA) or 1/(tSA + tHA)

167 125 125 100 83.3 71.4 62.5 MHz

fMAXIMaximum input register frequency 1/(tSIRS+tHIRS) or 1/(2 x tWICW)

167 125 125 100 83.3 71.4 62.5 MHz

M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)-5 -6 -7 -10 -12 -15 -20


MACH 5 Family 25



1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where these parameters may be affected.

ICC vs. FREQUENCY

These curves represent the typical power consumption for a particular device at system frequency. The selected “typical” pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power. For a more detailed discussion about MACH 5 power consumption, refer to the application note entitled MACH 5 Power in the Application Notes section on the Lattice Data Book CD-ROM or Lattice web site.

ICC CURVES AT HIGH /LOW POWER MODES

CAPACITANCE1

Parameter SymbolParameter

Description Test conditions Typ Unit

CIN I/CLK pin VIN =2.0 V 3.3 V or 5 V, 25º C, 1 MHz 12 pF

CI/O I/O pin VOUT =2.0 V 3.3 V or 5 V, 25º C, 1 MHz 10 pF

700

600

500

400

300

200

100

0

0 10 20 30 40 50 60 70 80 90 100

110

120

130

140

150

VCC = 5 V or 3.3 V, TA = 25º C

M5(LV)-512 high power



M5-256/1 and M5LV-25 high power

M5-128/1 and M5LV-128 high power

M5(LV)-384 low powerM5(LV)-320 low power

M5-256/1 and M5LV-256 low power

M5-128/1 and M5LV-128 low power

I CC

(m

A)

Frequency (MHz) 20446G-048

Figure 8. ICC Curves at High/Low Power Modes

M5-192/1 high power

M5-192/1 low power

M5(LV)-512 low power

26 MACH 5 Family



700

600

500

400

300

200

100

0

0 10 20 30 40 50 60 70 80 90 100

110

120

130

140

150

VCC = 5 V, TA = 25º C

M5-256 high power

M5-256 low power

I CC

(m

A)

Frequency (MHz)

M5-192 high power

M5-128 high power

M5-192 low power

M5-128 low power

20446G-049

Figure 9. ICC Curves at High/Low Power Modes

MACH 5 Family 27



100-PIN PQFP CONNECTION DIAGRAM

Top View

123456789101112131415161718192021222324252627282930

GNDGND

TDII/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7I/O8

I0/CLK0VCCVCC

GNDGND

I1/CLK1I/O9

I/O10I/O11I/O12I/O13I/O14I/O15I/O16I/O17TCKGNDGND

M5-128M5LV-128*

M5-128M5LV-128*

M5-192*

M5-256*M5LV-256

M5-256*M5LV-256

M5-256*M5LV-256

M5-256*M5LV-256

M5-192*

M5-192*

M5-192*

M5-128M5LV-128*

*Package obsolete, contact factory.

M5-128M5LV-128*

0A120B130B120B11

0B80B70B40B30B2

1B21B31B41B71B8

1B111B121B131A12

0A120B130B120B11

0B80B70B40B30B2

1B21B31B41B71B8

1B111B121B131A12

0A140B130B120B11

0B80B70B40B30B2

1B21B31B41B71B8

1B111B121B131A14

3A123B133B123B113B83B73B43B33B2

2B22B32B42B72B82B112B122B132A12

2A122B132B122B112B82B72B42B32B2

2C22C32C42C72C82C112C122C132D12

0D140C130C120C110C80C70C40C30C2

1C21C31C41C71C81C111C121C131D14

GNDGNDTDOI/O51I/O50I/O49I/O48I/O47I/O46I/O45I/O44I/O43I3/CLK3GNDGNDVCCVCCI2/CLK2I/O42I/O41I/O40I/O39I/O38I/O37I/O36I/O35I/O34TMSGNDGND

807978777675747372717069686766656463626160595857565554535251

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

I/O24

I/O25

VC

CG

ND

GN

DV

CC

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

I/O32

I/O33

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1A13

1A12

1A11

1A8

1A7

1A4

1A3

1A2

1D2

1D3

1D4

1D7

1D8

1D11

1D12

1D

13

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

3A0

3A1

3A2

3A3

3A4

3A5

3A6

3A7

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

0D2

0D3

0D4

0D7

0D8

0D11

0D12

0D13

0A13

0A12

0A11

0A8

0A7

0A4

0A3

0A2

I/O67

I/O66

I/O65

I/O64

I/O63

I/O62

I/O61

I/O60

VC

CG

ND

GN

DV

CC

I/O59

I/O58

I/O57

I/O56

I/O55

I/O54

I/O53

I/O52

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

20446G-016

100-Pin PQFP (68 I/O)

3 D 15CLK = ClockGND = GroundI = InputI/O = Input/OutputNC = No Connect

VCC = Supply VoltageTDI = Test Data InTCK = Test ClockTMS = Test Mode SelectTDO = Test Data Out

Pin Designations

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

28 MACH 5 Family



100-PIN TQFP CONNECTION DIAGRAM – 68 I/O

Top View100-Pin TQFP (68 I/O)

12345678910111213141516171819202122232425

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

75747372717069686766656463626160595857565554535251

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76


I0/CLK0VCC

GNDGND

I1/CLK1I/O9

I/O10I/O11I/O12I/O13I/O14I/O15I/O16I/O17TCK

GN

DG

ND

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

I/O24

I/O25 NC

VC

CG

ND

GN

DV

CC

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

I/O32

I/O33

GN

DG

ND

GN

DG

ND

NC

I/O67

I/O66

I/O65

I/O64

I/O63

I/O62

I/O61

I/O60

VC

CG

ND

GN

DV

CC

NC

I/O59

I/O58

I/O57

I/O56

I/O55

I/O54

I/O53

I/O52

GN

D

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

3A0

3A1

3A2

3A3

3A4

3A5

3A6

3A7

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

0A13

0A12

0A11

0A8

0A7

0A4

0A3

0A2

0D2

0D3

0D4

0D7

0D8

0D11

0D12

0D13

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1A13

1A12

1A11

1A8

1A7

1A4

1A3

1A2

1D2

1D3

1D4

1D7

1D8

1D11

1D12

1D13

GNDTDOI/O51I/O50I/O49I/O48I/O47I/O46I/O45I/O44I/O43I3/CLK3GNDVCCI2/CLK2I/O42I/O41I/O40I/O39I/O38I/O37I/O36I/O35I/O34TMS

3A123B133B123B113B83B73B43B33B2

M5-128M5LV-128

M5-128M5LV-128

M5-128M5LV-128

M5-192

M5-256M5LV-256*

M5-256M5LV-256*

M5-256M5LV-256*

M5-256M5LV-256*

M5-192

M5-192

M5-192

M5-128M5LV-128

2B22B32B42B72B82B112B122B132A12

2A122B132B122B112B82B72B42B32B2

2C22C32C42C72C82C112C122C132D12

0D140C130C120C110C80C70C40C30C2

1C21C31C41C71C81C111C121C131D14

0A120B130B120B110B80B70B40B30B2

1B21B31B41B71B8

1B111B121B131A12

0A120B130B120B110B80B70B40B30B2

1B21B31B41B71B8

1B111B121B131A12

0A140B130B120B110B80B70B40B30B2

1B21B31B41B71B8

1B111B121B131A14


20446G-017



Pin Designations

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

MACH 5 Family 29



100-PIN TQFP CONNECTION DIAGRAM – 74 I/OTop View

100-Pin TQFP (74 I/O)

12345678910111213141516171819202122232425

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

75747372717069686766656463626160595857565554535251

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76


I0/CLK0VCC

GNDGND

I1/CLK1I/O9


GN

DI/O

18I/O

19I/O

20I/O

21I/O

22I/O

23I/O

24I/O

25I/O

261/

O27

VC

CG

ND

GN

DV

CC

I/O28

I/O29

I/O30

I/O31

I/O32

I/O33

I/O34

I/O35

1/O

36G

ND

GN

DI/O

73I/O

72I/O

71I/O

70I/O

69I/O

68I/O

67I/O

66I/O

65I/O

64V

CC

GN

DG

ND

VC

CI/O

63I/O

62I/O

61I/O

60I/O

59I/O

58I/O

57I/O

56I/O

55

GN

D

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

0D11

0D12

3D12

3A0

3A1

3A2

3A3

3A4

3A5

3A6

3A7

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

1D11

1D12

2D12

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

0A13

0A12

0A11

0A10

0A9

0A8

0A7

0A4

0A3

0A2

0D1

0D2

0D3

0D4

0D7

0D8

0D11

0D12

0D13

1A13

1A12

1A11

1A10

1A8

1A7

1A4

1A3

1A2

1A1

1D2

1D3

1D4

1D7

1D8

1D10

1D11

1D12

1D13

GNDTDOI/O54I/O53I/O52I/O51I/O50I/O49I/O48I/O47I/O46I3/CLK3GNDVCCI2/CLK2I/O45I/O44I/O43I/O42I/O41I/O40I/O39I/O38I/O37TMS

3A123B133B123B113B83B73B43B33B2

M5LV-256

M5LV-128M5LV-128

M5LV-128M5LV-128

M5LV-256

M5LV-256

M5LV-256

2B22B32B42B72B82B112B122B132A12

0D140C130C120C110C80C70C40C30C2

1C21C31C41C71C81C111C121C131D14

0A120B130B120B110B80B70B40B30B2

1B21B31B41B71B8

1B111B121B131A12

0A140B130B120B110B80B70B40B30B2

1B21B31B41B71B8

1B111B121B131A14

20446G-018



Pin Designations

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

30 MACH 5 Family



144-PIN PQFP CONNECTION DIAGRAMTop View

144-Pin PQFP

123456789101112131415161718192021222324252627282930313233343536

TDII/O0I/O1I/O2I/O3I/O4

GNDI/O5I/O6I/O7I/O8

GNDI/O9

I/O10I/O11I/O12

I0/CLK0VCC

GNDI1/CLK1

I/O13I/O14I/O15I/O16GNDI/O17I/O18I/O19I/O20GNDI/O21I/O22I/O23I/O24I/O25TCK

0A80A9

0A100A110A12

0B130B120B11

0B8

0B50B40B30B2

1B21B31B41B5

1B81B111B121B13

1A121A111A10

1A91A8

0A120A130A140B130B12

0B110B80B50B4

0B30B20B10B0

1B01B11B21B3

1B41B51B8

1B11

1B121B131A141A131A12

0A140B130B120B110B10

0B80B70B60B5

0B40B30B20B1

1B11B21B31B4

1B51B61B71B8

1B101B111B121B131A14

M5-128M5LV-128*

M5-256*M5LV-256*

M5-256*M5LV-256*

M5-256*M5LV-256*

M5-256*M5LV-256*

M5-192*

M5-192*

M5-192*

M5-192*

M5-128M5LV-128*

M5-128M5LV-128*

M5-128M5LV-128*

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

GN

DV

CC

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

I/O32

GN

DI/O

33I/O

34I/O

35I/O

36I/O

37I/O

38V

CC

GN

DG

ND

VC

CI/O

39I/O

40I/O

41I/O

42I/O

43I/O

44G

ND

I/O45

I/O46

I/O47

I/O48

I/O49

I/O50

I/O51

VC

CG

ND

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1D3

1D4

1D7

1D8

1D11

1D12

2D12

2D11

2D8

2D7

2D4

2D3

2A1

2A2

2A3

2A4

2A5

2A6

2A7

1A11

1A10

1A8

1A7

1A6

1A5

1A4

1A3

1A2

1D2

1D3

1D4

1D7

1D8

1D11

1D12

1D13

2D2

2D3

2D4

2D5

2D6

2D7

2D8

2D10

2D11

1A13

1A12

1A11

1A10

1A8

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

1D10

1D11

1D12

1D13

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

GN

DV

CC

I/O10

3I/O

102

I/O10

1I/O

100

I/O99

I/O98

I/O97

GN

DI/O

96I/O

95I/O

94I/O

93I/O

92I/O

91V

CC

GN

DG

ND

VC

CI/O

90I/O

89I/O

88I/O

87I/O

86I/O

85G

ND

I/O84

I/O83

I/O82

I/O81

I/O80

I/O79

I/O78

VC

CG

ND

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0D3

0D4

0D7

0D8

0D11

0D12

3D12

3D11

3D8

3D7

3D4

3D3

3A1

3A2

3A3

3A4

3A5

3A6

3A7

0A11

0A10

0A8

0A7

0A6

0A5

0A4

0A3

0A2

0D2

0D3

0D4

0D7

0D8

0D11

0D12

0D13

2A2

2A3

2A4

2A5

2A6

2A7

2A8

2A10

2A11

0A13

0A12

0A11

A10

0A8

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

0D0

0D1

0D2

0D3

0D4

0D5

0D6

0D7

0D8

0D10

0D11

0D12

0D13

108107106105104103102101100

999897969594939291908988878685848382818079787776757473

TDOI/O77I/O76I/O75I/O74I/O73GNDI/O72I/O71I/O70I/O69GNDI/O68I/O67I/O66I/O65I3/CLK3GNDVCCI2/CLK2I/O64I/O63I/O62I/O61GNDI/O60I/O59I/O58I/O57GNDI/O56I/O55I/O54I/O53I/O52TMS

3A83A93A103A113A12

3B133B123B113B8

3B53B43B33B2

2B22B32B42B5

2B82B112B122B13

2A122A112A102A92A8

2A122A132A142B132B12

2B112B82B52B4

2B32B22B12B0

2C02C12C22C3

2C42C52C82C11

2C122C132D142D132D12

0D140C130C120C110C10

0C80C70C60C5

0C40C30C20C1

1C11C21C31C4

1C51C61C71C8

1C101C111C121C131D14


20446G-019



Pin Designations

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

MACH 5 Family 31



144-PIN TQFP CONNECTION DIAGRAMTop View

144-Pin TQFP

123456789101112131415161718192021222324252627282930313233343536

TDII/O0I/O1I/O2I/O3I/O4

GNDI/O5I/O6I/O7I/O8

GNDI/O9

I/O10I/O11I/O12

I0/CLK0VCC

GNDI1/CLK1

I/O13I/O14I/O15I/O16GNDI/O17I/O18I/O19I/O20GNDI/O21I/O22I/O23I/O24I/O25TCK

0A80A9

0A100A110A12

0B130B120B110B8

0B50B40B30B2

1B21B31B41B5

1B81B111B121B13

1A121A111A101A91A8

0A140B130B120B110B10

0B80B70B60B5

0B40B30B20B1

1B11B21B31B4

1B51B61B71B8

1B101B111B121B131A14

M5LV-128

M5LV-256 M5LV-256

M5LV-256 M5LV-256

M5LV-128

M5LV-128

M5LV-128

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

GN

DV

CC

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

I/O32

GN

DI/O

33I/O

34I/O

35I/O

36I/O

37I/O

38V

CC

GN

DG

ND

VC

CI/O

39I/O

40I/O

41I/O

42I/O

43I/O

44G

ND

I/O45

I/O46

I/O47

I/O48

I/O49

I/O50

I/O51

VC

CG

ND

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1D3

1D4

1D7

1D8

1D11

1D12

2D12

2D11

2D8

2D7

2D4

2D3

2A1

2A2

2A3

2A4

2A5

2A6

2A7

1A13

1A12

1A11

1A10

1A8

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

1D10

1D11

1D12

1D13

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

GN

DV

CC

I/O10

3I/O

102

I/O10

1I/O

100

I/O99

I/O98

I/O97

GN

DI/O

96I/O

95I/O

94I/O

93I/O

92I/O

91V

CC

GN

DG

ND

VC

CI/O

90I/O

89I/O

88I/O

87I/O

86I/O

85G

ND

I/O84

I/O83

I/O82

I/O81

I/O80

I/O79

I/O78

VC

CG

ND

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0D3

0D4

0D7

0D8

0D11

0D12

3D12

3D11

3D8

3D7

3D4

3D3

3A1

3A2

3A3

3A4

3A5

3A6

3A7

0A13

0A12

0A11

A10

0A8

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

0D0

0D1

0D2

0D3

0D4

0D5

0D6

0D7

0D8

0D10

0D11

0D12

0D13

108107106105104103102101100999897969594939291908988878685848382818079787776757473

TDOI/O77I/O76I/O75I/O74I/O73GNDI/O72I/O71I/O70I/O69GNDI/O68I/O67I/O66I/O65I3/CLK3GNDVCCI2/CLK2I/O64I/O63I/O62I/O61GNDI/O60I/O59I/O58I/O57GNDI/O56I/O55I/O54I/O53I/O52TMS

3A83A93A103A113A12

3B133B123B113B8

3B53B43B33B2

2B22B32B42B5

2B82B112B122B13

2A122A112A102A92A8

0D140C130C120C110C10

0C80C70C60C5

0C40C30C20C1

1C11C21C31C4

1C51C61C71C8

1C101C111C121C131D14

20446G-020



Pin Designations

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

32 MACH 5 Family




160-Pin PQFP (128, 192, 256 Macrocells)

12345678910111213141516171819202122232425262728293031323334353637383940

TDII/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7

GNDI/O8I/O9

I/O10I/O11I/O12I/O13I/O14I/O15

I0/CLK0VCC

GNDI1/CLK1

I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23GNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31TCK

0A80A9

0A100A110A120A130A140A15

0B130B120B110B80B50B40B30B2

1B21B31B41B51B8

1B111B121B13

1A151A141A131A121A111A101A91A8

0A120A130A140A150B150B140B130B12

0B110B80B50B40B30B20B10B0

1B01B11B21B31B41B51B8

1B11

1B121B131B141B151A151A141A131A12

0A140A150B140B130B120B110B100B9

0B80B70B60B50B40B30B20B1

1B11B21B31B41B51B61B71B8

1B91B101B111B121B131B141A151A14

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

GN

DV

CC

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

GN

DV

CC

I/O40

I/O41

I/O42

I/O43

I/O44

I/O45

VC

CG

ND

GN

DV

CC

I/O46

I/O47

I/O48

I/O49

I/O50

I/O51

VC

CG

ND

I/O52

I/O53

I/O54

I/O55

I/O56

I/O57

I/O58

I/O59

VC

CG

ND

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

1D3

1D4

1D7

1D8

1D11

1D12

2D12

2D11

2D8

2D7

2D4

2D3

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

1A11

1A10

1A9

1A8

1A7

1A6

1A5

1A4

1A3

1A2

1D2

1D3

1D4

1D7

1D8

1D11

1D12

1D13

2D2

2D3

2D4

2D5

2D6

2D7

2D8

2D9

2D10

2D11

1A13

1A12

1A11

1A10

1A9

1A8

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D8

1D9

1D10

1D11

1D12

1D13

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

GN

DV

CC

I/O11

9I/O

118

I/O11

7I/O

116

I/O11

5I/O

114

I/O11

3I/O

112

GN

DV

CC

I/O11

1I/O

110

I/O10

9I/O

108

I/O10

7I/O

106

VC

CG

ND

GN

DV

CC

I/O10

5I/O

104

I/O10

3I/O

102

I/O10

1I/O

100

VC

CG

ND

I/O99

I/O98

I/O97

I/O96

I/O95

I/O94

I/O93

I/O92

VC

CG

ND

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

0D3

0D4

0D7

0D8

0D11

0D12

3D12

3D11

3D8

3D7

3D4

3D3

3A0

3A1

3A2

3A3

3A4

3A5

3A6

3A7

0A11

0A10

0A9

0A8

0A7

0A6

0A5

0A4

0A3

0A2

0D2

0D3

0D4

0D7

0D8

0D11

0D12

0D13

2A2

2A3

2A4

2A5

2A6

2A7

2A8

2A9

2A10

2A11

0A13

0A12

0A11

0A10

0A9

0A8

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

0D0

0D1

0D2

0D3

0D4

0D5

0D6

0D7

0D8

0D9

0D10

0D11

0D12

0D13

12011911811711611511411311211111010910810710610510410310210110099989796959493929190898887868584838281

TDOI/O91I/O90I/O89I/O88I/O87I/O86I/O85I/O84GNDI/O83I/O82I/O81I/O80I/O79I/O78I/O77I/O76I3/CLK3GNDVCCI2/CLK2I/O75I/O74I/O73I/O72I/O71I/O70I/O69I/O68GNDI/O67I/O66I/O65I/O64I/O63I/O62I/O61I/O60TMS

3A83A93A103A113A123A133A143A15

3B133B123B113B83B53B43B33B2

2B22B32B42B52B82B112B122B13

2A152A142A132A122A112A102A92A8

M5-128M5LV-128

M5-128M5LV-128

M5-128M5LV-128

M5-256M5LV-256

M5-256M5LV-256

M5-256M5LV-256

M5-256M5LV-256

M5-192

M5-192

M5-192

M5-192

M5-128M5LV-128

2A122A132A142A152B152B142B132B12

2B112B82B52B42B32B22B12B0

2C02C12C22C32C42C52C82C11

2C122C132C142C152D152D142D132D12

0D140D150C140C130C120C110C100C9

0C80C70C60C50C40C30C20C1

1C11C21C31C41C51C61C71C8

1C91C101C111C121C131C141D151D14

20446G-021



Pin Designations

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

MACH 5 Family 33



160-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAMTop View


12345678910111213141516171819202122232425262728293031323334353637383940

TDII/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7

GNDI/O8I/O9

I/O10I/O11I/O12I/O13I/O14I/O15

I0/CLK0VCC

GNDI1/CLK1

I/O16I/O17I/O18I/O19I/O20I/O21I/O22I/O23GNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31TCK

0A20A30A40A70A8

0A110A120A13

0D130D120D110D80D70D40D30D2

1D21D31D41D71D8

1D111D121D13

1A131A121A111A81A71A41A31A2

0A20A30A40A70A8

0A110A120A13

0D130D120D110D80D70D40D30D2

1D21D31D41D71D8

1D111D121D13

1A131A121A111A81A71A41A31A2

0A20A30A40A70A8

0A110A120A13

0D130D120D110D80D70D40D30D2

1D21D31D41D71D8

1D111D121D13

1A151A141A131A121A111A101A91A8

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

GN

DV

CC

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

GN

DV

CC

I/O40

I/O41

I/O42

I/O43

I/O44

I/O45

VC

CG

ND

GN

DV

CC

I/O46

I/O47

I/O48

I/O49

I/O50

I/O51

VC

CG

ND

I/O52

I/O53

I/O54

I/O55

I/O56

I/O57

I/O58

I/O59

VC

CG

ND

2A13

2A12

2A11

2A8

2A7

2A4

2A3

2A2

2B3

2B4

2B7

2B8

2B11

2B12

3B12

3B11

3B8

3B7

3B4

3B3

3A2

3A3

3A4

3A7

3A8

3A11

3A12

3A13

1B2

1B3

1B4

1B7

1B8

1B11

1B12

1B13

2A12

2A11

2A8

2A7

2A4

2A3

2B3

2B4

2B7

2B8

2B11

2B12

3B13

3B12

3B11

3B8

3B7

3B4

3B3

3B2

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

1B3

1B4

1B7

1B8

1B11

1B12

2B12

2B11

2B8

2B7

2B4

2B3

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

GN

DV

CC

I/O11

9I/O

118

I/O11

7I/O

116

I/O11

5I/O

114

I/O11

3I/O

112

GN

DV

CC

I/O11

1I/O

110

I/O10

9I/O

108

I/O10

7I/O

106

VC

CG

ND

GN

DV

CC

I/O10

5I/O

104

I/O10

3I/O

102

I/O10

1I/O

100

VC

CG

ND

I/O99

I/O98

I/O97

I/O96

I/O95

I/O94

I/O93

I/O92

VC

CG

ND

7A13

7A12

7A11

7A8

7A7

7A4

7A3

7A2

7B3

7B4

7B7

7B8

7B11

7B12

6B12

6B11

6B8

6B7

6B4

6B3

6A2

6A3

6A4

6A7

6A8

6A11

6A12

6A13

0B2

0B3

0B4

0B7

0B8

0B11

0B12

0B13

5A12

5A11

5A8

5A7

5A4

5A3

5B3

5B4

5B7

5B8

5B11

5B12

4B13

4B12

4B11

4B8

4B7

4B4

4B3

4B2

0B2

0B3

0B4

0B7

0B8

0B11

0B12

0B13

4A12

4A11

4A8

4A7

4A4

4A3

4B3

4B4

4B7

4B8

4B11

4B12

3B13

3B12

3B11

3B8

3B7

3B4

3B3

3B2

12011911811711611511411311211111010910810710610510410310210110099989796959493929190898887868584838281

TDOI/O91I/O90I/O89I/O88I/O87I/O86I/O85I/O84GNDI/O83I/O82I/O81I/O80I/O79I/O78I/O77I/O76I3/CLK3GNDVCCI2/CLK2I/O75I/O74I/O73I/O72I/O71I/O70I/O69I/O68GNDI/O67I/O66I/O65I/O64I/O63I/O62I/O61I/O60TMS

5A25A35A45A75A85A115A125A13

5D135D125D115D85D75D45D35D2

4D24D34D44D74D84D114D124D13

4A134A124A114A84A74A44A34A2

M5-320*M5LV-320

M5-384*M5LV-384

M5-384*M5LV-384

M5-384*M5LV-384

M5-384*M5LV-384

M5-512*M5LV-512

M5-512*M5LV-512

M5-512*M5LV-512

M5-512*M5LV-512

M5-320*M5LV-320

M5-320*M5LV-320

M5-320*M5LV-320

4A24A34A44A74A84A114A124A13

4D134D124D114D84D74D44D34D2

3D23D33D43D73D83D113D123D13

3A133A123A113A83A73A43A33A2

3A23A33A43A73A83A113A123A13

3D133D123D113D83D73D43D33D2

2D22D32D42D72D82D112D122D13

2A152A142A132A122A112A102A92A8


20446G-022



Pin Designations

Macrocell (0-15)

PAL Block (A-D)

Segment (0-7)

34 MACH 5 Family




208-Pin PQFP (256 Macrocells)

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152

TDII/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7VCC

GNDI/O8I/O9

I/O10I/O11I/O12I/O13I/O14I/O15GNDI/O16I/O17I/O18I/O19

I0/CLK0VCC

GNDI1/CLK1

I/O20I/O21I/O22I/O23GNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31GNDVCC


0A80A9

0A100A110A120A130A140A15

0B130B120B110B10

0B90B80B70B6

0B50B40B30B2

1B21B31B41B5

1B61B71B81B9

1B101B111B121B13

1A151A141A131A121A111A10

1A91A8

TDOI/O119I/O118I/O117I/O116I/O115I/O114I/O113I/O112VCCGNDI/O111I/O110I/O109I/O108I/O107I/O106I/O105I/O104GNDI/O103I/O102I/O101I/O100I3/CLK3GNDVCCI2/CLK2I/O99I/O98I/O97I/O96GNDI/O95I/O94I/O93I/O92I/O91I/O90I/O89I/O88GNDVCCI/O87I/O86I/O85I/O84I/O83I/O82I/O81I/O80TMS

3A83A93A103A112A123A133A143A15

3B133B123B113B103B93B83B73B6

3B53B43B33B2

2B22B32B42B5

2B62B72B82B92B102B112B122B13

2A152A142A132A122A112A102A92A8

M5-256M5LV-256

M5-256M5LV-256

M5-256M5LV-256

M5-256M5LV-256

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

101

102

103

104

GN

DI/O

40I/O

41I/O

42I/O

43I/O

44I/O

45I/O

46I/O

47G

ND

VC

CI/O

48I/O

49I/O

50I/O

51I/O

52I/O

53I/O

54I/O

55G

ND

I/O56

I/O57

I/O58

I/O59

VC

CG

ND

GN

DV

CC

I/O60

I/O61

I/O62

I/O63

GN

DI/O

64I/O

65I/O

66I/O

67I/O

68I/O

69I/O

70I/O

71V

CC

GN

DI/O

72I/O

73I/O

74I/O

75I/O

76I/O

77I/O

78I/O

79G

ND

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

1D2

1D3

1D4

1D5

1D6

1D7

1D8

1D9

1D10

1D11

1D12

1D13

2D13

2D12

2D11

2D10

2D9

2D8

2D7

2D6

2D5

2D4

2D3

2D2

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

GN

DI/O

159

I/O15

8I/O

157

I/O15

6I/O

155

I/O15

4I/O

153

I/O15

2G

ND

VC

CI/O

151

I/O15

0I/O

149

I/O14

8I/O

147

I/O14

6I/O

145

I/O14

4G

ND

I/O14

3I/O

142

I/O14

1I/O

140

VC

CG

ND

GN

DV

CC

I/O13

9I/O

138

I/O13

7I/O

136

GN

DI/O

135

I/O13

4I/O

133

I/O13

2I/O

131

I/O13

0I/O

129

I/O12

8V

CC

GN

DI/O

127

I/O12

6I/O

125

I/O12

4I/O

123

I/O12

2I/O

121

I/O12

0G

ND

0A7

0A6

0A5

0A4

0A3

0A2

0A1

0A0

0D2

0D3

0D4

0D5

0D6

0D7

0D8

0D9

0D10

0D11

0D12

0D13

3D13

3D12

3D11

3D10

3D9

3D8

3D7

3D6

3D5

3D4

3D3

3D2

3A0

3A1

3A2

3A3

3A4

3A5

3A6

3A7

156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108107106105

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

20446G-023



Pin Designations

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

MACH 5 Family 35



208-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAMTop View


12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152

TDII/O0I/O1I/O2I/O3I/O4I/O5I/O6I/O7VCC

GNDI/O8I/O9

I/O10I/O11I/O12I/O13I/O14I/O15GNDI/O16I/O17I/O18I/O19

I0/CLK0VCC

GNDI1/CLK1

I/O20I/O21I/O22I/O23GNDI/O24I/O25I/O26I/O27I/O28I/O29I/O30I/O31GNDVCC


0A20A30A40A70A8

0A110A120A13

0D150D140D130D120D110D100D90D8

0D70D40D30D2

1D21D31D41D7

1D81D9

1D101D111D121D131D141D15

1A131A121A111A81A71A41A31A2

0A20A30A40A70A8

0A110A120A13

0D150D140D130D120D110D100D90D8

0D70D40D30D2

1D21D31D41D7

1D81D9

1D101D111D121D131D141D15

1A131A121A111A81A71A41A31A2

0A20A30A40A70A8

0A110A120A13

0D150D140D130D120D110D100D90D8

0D70D40D30D2

1D21D31D41D7

1D81D9

1D101D111D121D131D141D15

1A151A141A131A121A111A101A91A8

TDOI/O119I/O118I/O117I/O116I/O115I/O114I/O113I/O112VCCGNDI/O111I/O110I/O109I/O108I/O107I/O106I/O105I/O104GNDI/O103I/O102I/O101I/O100I3/CLK3GNDVCCI2/CLK2I/O99I/O98I/O97I/O96GNDI/O95I/O94I/O93I/O92I/O91I/O90I/O89I/O88GNDVCCI/O87I/O86I/O85I/O84I/O83I/O82I/O81I/O80TMS

5A25A35A45A75A85A115A125A13

5D155D145D135D125D115D105D95D8

5D75D45D35D2

4D24D34D44D7

4D84D94D104D114D124D134D144D15

4A134A124A114A84A74A44A34A2

4A24A34A44A74A84A114A124A13

4D154D144D134D124D114D104D94D8

4D74D44D34D2

3D23D33D43D7

3D83D93D103D113D123D133D143D15

3A133A123A113A83A73A43A33A2

3A23A33A43A73A83A113A123A13

3D153D143D133D123D113D103D93D8

3D73D43D33D2

2D22D32D42D7

2D82D92D102D112D122D132D142D15

2A152A142A132A122A112A102A92A8

M5-384M5LV-384

M5-384M5LV-384

M5-384M5LV-384

M5-384M5LV-384

M5-320M5LV-320

M5-320M5LV-320

M5-320M5LV-320

M5-320M5LV-320

M5-512M5LV-512

M5-512M5LV-512

M5-512M5LV-512

M5-512M5LV-512

53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100

101

102

103

104

GN

DI/O

40I/O

41I/O

42I/O

43I/O

44I/O

45I/O

46I/O

47G

ND

VC

CI/O

48I/O

49I/O

50I/O

51I/O

52I/O

53I/O

54I/O

55G

ND

I/O56

I/O57

I/O58

I/O59

VC

CG

ND

GN

DV

CC

I/O60

I/O61

I/O62

I/O63

GN

DI/O

64I/O

65I/O

66I/O

67I/O

68I/O

69I/O

70I/O

71V

CC

GN

DI/O

72I/O

73I/O

74I/O

75I/O

76I/O

77I/O

78I/O

79G

ND

2A13

2A12

2A11

2A8

2A7

2A4

2A3

2A2

2B0

2B1

2B2

2B3

2B4

2B5

2B6

2B7

2B8

2B11

2B12

2B13

3B13

3B12

3B11

3B8

3B7

3B6

3B5

3B4

3B3

3B2

3B1

3B0

3A2

3A3

3A4

3A7

3A8

3A11

3A12

3A13

1B2

1B3

1B4

1B7

1B8

1B11

1B12

1B13

2A15

2A14

2A13

2A12

2A11

2A10

2A9

2A8

2A7

2A4

2A3

2A2

2B2

2B3

2B4

2B7

2B8

2B9

2B10

2B11

2B12

2B13

2B14

2B15

3B13

3B12

3B11

3B8

3B7

3B4

3B3

3B2

1A7

1A6

1A5

1A4

1A3

1A2

1A1

1A0

1B0

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

1B11

1B12

1B13

2B13

2B12

2B11

2B8

2B7

2B6

2B5

2B4

2B3

2B2

2B1

2B0

2A0

2A1

2A2

2A3

2A4

2A5

2A6

2A7

GN

DI/O

159

I/O15

8I/O

157

I/O15

6I/O

155

I/O15

4I/O

153

I/O15

2G

ND

VC

CI/O

151

I/O15

0I/O

149

I/O14

8I/O

147

I/O14

6I/O

145

I/O14

4G

ND

I/O14

3I/O

142

I/O14

1I/O

140

VC

CG

ND

GN

DV

CC

I/O13

9I/O

138

I/O13

7I/O

136

GN

DI/O

135

I/O13

4I/O

133

I/O13

2I/O

131

I/O13

0I/O

129

I/O12

8V

CC

GN

DI/O

127

I/O12

6I/O

125

I/O12

4I/O

123

I/O12

2I/O

121

I/O12

0G

ND

7A13

7A12

7A11

7A8

7A7

7A4

7A3

7A2

7B0

7B1

7B2

7B3

7B4

7B5

7B6

7B7

7B8

7B11

7B12

7B13

6B13

6B12

6B11

6B8

6B7

6B6

6B5

6B4

6B3

6B2

6B1

6B0

6A2

6A3

6A4

6A7

6A8

6A11

6A12

6A13

0B2

0B3

0B4

0B7

0B8

0B11

0B12

0B13

5A15

5A14

5A13

5A12

5A11

5A10

5A9

5A8

5A7

5A4

5A3

5A2

5B2

5B3

5B4

5B7

5B8

5B9

5B10

5B11

5B12

5B13

5B14

5B15

4B13

4B12

4B11

4B8

4B7

4B4

4B3

4B2

0B2

0B3

0B4

0B7

0B8

0B11

0B12

0B13

4A15

4A14

4A13

4A12

4A11

4A10

4A9

4A8

4A7

4A4

4A3

4A2

4B2

4B3

4B4

4B7

4B8

4B9

4B10

4B11

4B12

4B13

4B14

4B15

3B13

3B12

3B11

3B8

3B7

3B4

3B3

3B2

156155154153152151150149148147146145144143142141140139138137136135134133132131130129128127126125124123122121120119118117116115114113112111110109108107106105

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

20446G-024



Pin Designations

Macrocell (0-15)

PAL Block (A-D)

Segment (0-7)

36 MACH 5 Family



256-BALL BGA CONNECTION DIAGRAM — M5-320Bottom View (I/O Pin-outs)

256-Ball BGA20

1918

1716

1514

1312

1110

98

76

54

32

1

AG

ND

I/O11

GN

DI/O

44I/O

58G

ND

I/O70

I/O76

GN

DG

ND

GN

DG

ND

I/O10

8I/O

116

GN

DI/O

128

I/O13

4G

ND

GN

DG

ND

A

BG

ND

I/O12

I/O28

I/O45

I/O59

I/O64

I/O71

I/O77

I/O84

I/O90

I/O96

I/O10

2I/O

109

I/O11

7I/O

122

I/O12

9I/O

135

I/O14

8I/O

164

GN

DB

CI/O

0I/O

13V

CC

I/O46

I/O60

I/O65

I/O72

I/O78

I/O85

I/O91

I/O97

I/O10

3I/O

110

I/O11

8I/O

123

I/O13

0I/O

136

VC

CI/O

165

I/O18

1C

DI/O

1I/O

14I/O

29V

CC

VC

CI/O

66V

CC

I/O79

I/O86

I/O92

I/O98

I/O10

4I/O

111

VC

CI/O

124

VC

CV

CC

I/O14

9I/O

166

I/O18

2D

EI/O

2I/O

15I/O

30T

DI

TD

OI/O

150

I/O16

7I/O

183

E

FG

ND

I/O16

I/O31

I/O47

I/O13

7I/O

151

I/O16

8G

ND

F

GI/O

3I/O

17I/O

32V

CC

VC

CI/O

152

I/O16

9I/O

184

G

HG

ND

I/O18

I/O33

I/O48

I/O13

8I/O

153

I/O17

0G

ND

H

JI/O

4I/O

19I/O

34I/O

49I/O

139

I/O15

4I/O

171

I/O18

5J

KG

ND

IO/C

LK0

I/O35

I/O50

I/O14

0I/O

155

I3/C

LK3

I/O18

6K

LI/O

5I1

/CLK

1I/O

36I/O

51I/O

141

I/O15

6I2

/CLK

2G

ND

L

MI/O

6I/O

20I/O

37I/O

52I/O

142

I/O15

7I/O

172

I/O18

7M

NG

ND

I/O21

I/O38

I/O53

I/O14

3I/O

158

I/O17

3G

ND

N

PI/O

7I/O

22I/O

39V

CC

VC

CI/O

159

I/O17

4I/O

188

P

RG

ND

I/O23

I/O40

I/O54

I/O14

4I/O

160

I/O17

5G

ND

R

TI/O

8I/O

24I/O

41T

CK

TM

SI/O

161

I/O17

6I/O

189

T

UI/O

9I/O

25I/O

42V

CC

VC

CI/O

67V

CC

I/O80

I/O87

I/O93

I/O99

I/O10

5I/O

112

VC

CI/O

125

VC

CV

CC

I/O16

2I/O

177

I/O19

0U

VI/O

10I/O

26V

CC

I/O55

I/O61

I/O68

I/O73

I/O81

I/O88

I/O94

I/O10

0I/O

106

I/O11

3I/O

119

I/O12

6I/O

131

I/O14

5V

CC

I/O17

8I/O

191

V

WG

ND

I/O27

I/O43

I/O56

I/O62

I/O69

I/O74

I/O82

I/O89

I/O95

I/O10

1I/O

107

I/O11

4I/O

120

I/O12

7I/O

132

I/O14

6I/O

163

I/O17

9G

ND

W

YG

ND

GN

DG

ND

I/O57

I/O63

GN

DI/O

75I/O

83G

ND

GN

DG

ND

GN

DI/O

115

I/O12

1G

ND

I/O13

3I/O

147

GN

DI/O

180

GN

DY

2019

1817

1615

1413

1211

109

87

65

43

21

20446G-026

CLK = ClockGND = GroundI = InputI/O = Input/OutputNC = No ConnectVCC = Supply VoltageTDI = Test Data InTCK = Test ClockTMS = Test Mode SelectTDO = Test Data Out

Pin Designations

MACH 5 Family 37



256-BALL BGA CONNECTION DIAGRAM — M5-320Bottom View (Macrocell Association)

256-Ball BGA20

1918

1716

1514

1312

1110

98

76

54

32

1

AG

ND

0B2

GN

D0B

134A

14G

ND

4A8

4A4

GN

DG

ND

GN

DG

ND

4B4

4B8

GN

D4B

143B

13G

ND

GN

DG

ND

A

BG

ND

0A3

0B8

0B11

4A15

4A11

4A10

4A6

4A3

4A0

4B0

4B3

4B6

4B10

4B11

4B15

3B11

3B8

3B2

GN

DB

C0D

150A

8V

CC

0B3

0B4

0B12

4A13

4A9

4A5

4A1

4B1

4B5

4B9

4B13

3B12

3B4

3B3

VC

C3A

33A

11C

D0D

130A

110A

2V

CC

VC

C0B

7V

CC

4A12

4A7

4A2

4B2

4B7

4B12

VC

C3B

7V

CC

VC

C3A

23A

83D

15D

E0D

100A

130A

4T

DI

TD

O3A

43A

133D

12E

FG

ND

0D12

0A12

0A7

3A7

3A12

3D13

GN

DF

G0D

70D

80D

14V

CC

VC

C3D

143D

93D

7G

HG

ND

0D4

0D9

0D11

3D11

3D10

3D8

GN

DH

J0D

20D

30D

50D

63D

63D

53D

43D

3J

KG

ND

IO/C

LK0

0D0

0D1

3D1

3D0

I3/C

LK3

3D2

K

L1D

2I1

/CLK

11D

01D

12D

12D

0I2

/CLK

2G

ND

L

M1D

31D

41D

51D

62D

62D

52D

32D

2M

NG

ND

1D8

1D10

1D11

2D11

2D9

2D4

GN

DN

P1D

71D

91D

14V

CC

VC

C2D

142D

82D

7P

RG

ND

1D13

1A14

1A11

2A11

2A14

2D12

GN

DR

T1D

121A

151A

10T

CK

TM

S2A

102A

152D

10T

U1D

151A

121A

8V

CC

VC

C1A

4V

CC

1B3

1B8

1B13

2B13

2B8

2B3

VC

C2A

4V

CC

VC

C2A

82A

132D

13U

V1A

131A

9V

CC

1A6

1A5

1A1

1B2

1B6

1B10

1B14

2B14

2B10

2B6

2B2

2A1

2A5

2A6

VC

C2A

122D

15V

WG

ND

1A7

1A3

1A2

1B0

1B4

1B5

1B9

1B12

1B15

2B15

2B12

2B9

2B5

2B4

2B0

2A2

2A3

2A9

GN

DW

YG

ND

GN

DG

ND

1A0

1B1

GN

D1B

71B

11G

ND

GN

DG

ND

GN

D2B

112B

7G

ND

2B1

2A0

GN

D2A

7G

ND

Y

2019

1817

1615

1413

1211

109

87

65

43

21

20446G-029


Pin Designations

4 D 15

Macrocell (0-15)

PAL Block (A-D)

Segment (0-4)

38 MACH 5 Family



352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512Bottom View (I/O Pin-outs)

352-Ball BGA

2625

2423

2221

2019

1817

1615

1413

1211

109

87

65

43

21

AN

CG

ND

NC

I/O51

GN

DI/O

73I/O

80I/O

87G

ND

I/O10

1N

CI/O

114

GN

DI/O

128

I/O13

4I/O

142

GN

DI/O

156

I/O16

2G

ND

NC

GN

DN

CG

ND

NC

NC

A

BN

CG

ND

NC

I/O52

I/O68

I/O74

I/O81

I/O88

I/O95

I/O10

2I/O

107

I/O11

5I/O

122

I/O12

9I/O

135

I/O14

3I/O

150

I/O15

7I/O

163

I/O16

9I/O

176

I/O18

3I/O

188

GN

DN

CN

CB

CG

ND

I/O11

TD

II/O

53I/O

69I/O

75I/O

82I/O

89I/O

96I/O

103

I/O10

8I/O

116

I/O12

3I/O

130

I/O13

6I/O

144

I/O15

1I/O

158

I/O16

4I/O

170

I/O17

7I/O

184

NC

NC

NC

NC

C

DI/O

0I/O

12I/O

32V

CC

I/O70

I/O76

I/O83

I/O90

VC

CI/O

104

I/O10

9I/O

117

VC

CI/O

131

I/O13

7I/O

145

VC

CI/O

159

I/O16

5I/O

171

I/O17

8V

CC

TD

OI/O

205

I/O22

4G

ND

D

EN

CI/O

13I/O

33I/O

54I/O

189

I/O20

6I/O

225

NC

E

FG

ND

I/O14

I/O34

I/O55

I/O19

0I/O

207

I/O22

6I/O

245

F

GI/O

1I/O

15I/O

35V

CC

I/O19

1I/O

208

I/O22

7G

ND

G

HI/O

2I/O

16I/O

36I/O

56V

CC

I/O20

9I/O

228

I/O24

6H

JG

ND

I/O17

I/O37

VC

CI/O

192

I/O21

0I/O

229

I/O24

7J

KI/O

3I/O

18I/O

38I/O

57V

CC

I/O21

1I/O

230

GN

DK

LI/O

4I/O

19I/O

39I/O

58I/O

193

I/O21

2I/O

231

I/O24

8L

MI/O

5I/O

20I/O

40I/O

59I/O

194

I/O21

3I/O

232

I/O24

9M

NG

ND

I/O21

I0/C

LK0

VC

CI/O

195

I/O21

4I/O

233

I3/C

LK3

N

PI1

/CLK

1I/O

22I/O

41I/O

60V

CC

I2C

LK2

I/O23

4G

ND

P

RI/O

6I/O

23I/O

42I/O

61I/O

196

I/O21

5I/O

235

I/O25

0R

TI/O

7I/O

24I/O

43I/O

62I/O

197

I/O21

6I/O

236

I/O25

1T

UG

ND

I/O25

I/O44

VC

CI/O

198

I/O21

7I/O

237

I/O25

2U

VI/O

8I/O

26I/O

45I/O

63V

CC

I/O21

8I/O

238

GN

DV

WI/O

9I/O

27I/O

46V

CC

I/O19

9I/O

219

I/O23

9I/O

253

W

YG

ND

I/O28

I/O47

I/O64

VC

CI/O

220

I/O24

0I/O

254

Y

AA

I/O10

I/O29

I/O48

I/O65

I/O20

0I/O

221

I/O24

1G

ND

AA

AB

NC

I/O30

I/O49

I/O66

I/O20

1I/O

222

I/O24

2N

CA

B

AC

GN

DI/O

31I/O

50T

CK

VC

CI/O

77I/O

84I/O

91I/O

97V

CC

I/O11

0I/O

118

I/O12

4V

CC

I/O13

8I/O

146

I/O15

2V

CC

I/O16

6I/O

172

I/O17

9I/O

185

VC

CI/O

223

I/O24

3I/O

255

AC

AD

NC

NC

NC

NC

I/O71

I/O78

I/O85

I/O92

I/O98

I/O10

5I/O

111

I/O11

9I/O

125

I/O13

2I/O

139

I/O14

7I/O

153

I/O16

0I/O

167

I/O17

3I/O

180

I/O18

6I/O

202

TM

SI/O

244

GN

DA

D

AE

NC

NC

GN

DI/O

67I/O

72I/O

79I/O

86I/O

93I/O

99I/O

106

I/O11

2I/O

120

I/O12

6I/O

133

I/O14

0I/O

148

I/O15

4I/O

161

I/O16

8I/O

174

I/O18

1I/O

187

I/O20

3N

CG

ND

NC

AE

AF

NC

NC

GN

DN

CG

ND

NC

GN

DI/O

94I/O

100

GN

DI/O

113

I/O12

1I/O

127

GN

DI/O

141

I/O14

9I/O

155

GN

DN

CI/O

175

I/O18

2G

ND

I/O20

4N

CG

ND

NC

AF

2625

2423

2221

2019

1817

1615

1413

1211

109

87

65

43

21

20446G-030


Pin Designations

MACH 5 Family 39



352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512Bottom View (Macrocell Association)

352-Ball BGA

2625

2423

2221

2019

1817

1615

1413

1211

109

87

65

43

21

AN

CG

ND

NC

7A10

GN

D7A

57A

07B

1G

ND

7B7

NC

7B14

GN

D6B

146B

106B

6G

ND

6B1

6A1

GN

DN

CG

ND

NC

GN

DN

CN

CA

BN

CG

ND

NC

7A13

7A9

7A6

7A2

7B0

7B3

7B6

7B10

7B13

7B15

6B13

6B9

6B5

6B2

6A0

6A4

6A6

6A9

6A12

6A14

GN

DN

CN

CB

CG

ND

0A1

TD

I7A

147A

117A

77A

37A

17B

27B

57B

97B

126B

156B

126B

86B

46B

06A

26A

56A

86A

106A

13N

CN

CN

CN

CC

D0A

60A

30A

2V

CC

7A15

7A12

7A8

7A4

VC

C7B

47B

87B

11V

CC

6B11

6B7

6B3

VC

C6A

36A

76A

116A

15V

CC

TD

O5A

15A

2G

ND

D

EN

C0A

80A

50A

05A

05A

45A

5N

CE

FG

ND

0A9

0A7

0A4

5A3

5A7

5A9

5A12

F

G0A

130A

120A

10V

CC

5A6

5A8

5A14

GN

DG

H0D

150A

150A

140A

11V

CC

5A10

5A15

5D15

H

JG

ND

0D13

0D14

VC

C5A

115A

135D

135D

11J

K0D

90D

100D

110D

12V

CC

5D14

5D10

GN

DK

L0D

50D

60D

70D

85D

125D

95D

85D

6L

M0D

10D

20D

40D

35D

75D

55D

45D

3M

NG

ND

0D0

I0/C

LK0

VC

C5D

25D

15D

0I3

/CLK

3N

PI1

/CLK

11D

01D

11D

2V

CC

I2/C

LK2

4D0

GN

DP

R1D

31D

41D

51D

74D

34D

44D

24D

1R

T1D

61D

81D

91D

124D

84D

74D

64D

5T

UG

ND

1D10

1D14

VC

C4D

124D

114D

104D

9U

V1D

111D

131A

131A

11V

CC

4D14

4D13

GN

DV

W1D

151A

151A

10V

CC

4A11

4A14

4A15

4D15

W

YG

ND

1A14

1A8

1A6

VC

C4A

104A

124A

13Y

AA

1A12

1A9

1A7

1A3

4A4

4A7

4A9

GN

DA

A

AB

NC

1A5

1A4

1A0

4A0

4A5

4A8

NC

AB

AC

GN

D1A

21A

1T

CK

VC

C2A

152A

112A

72A

3V

CC

2B3

2B7

2B11

VC

C3B

113B

73B

3V

CC

3A2

3A6

3A10

3A14

VC

C4A

24A

34A

6A

C

AD

NC

NC

NC

NC

2A13

2A10

2A8

2A5

2A2

2B0

2B4

2B8

2B12

2B15

3B12

3B8

3B4

3B1

3A1

3A4

3A8

3A11

3A15

TM

S4A

1G

ND

AD

AE

NC

NC

GN

D2A

142A

122A

92A

62A

42A

02B

22B

52B

92B

133B

153B

133B

93B

53B

23B

03A

33A

73A

93A

13N

CG

ND

NC

AE

AF

NC

NC

GN

DN

CG

ND

NC

GN

D2A

12B

1G

ND

2B6

2B10

2B14

GN

D3B

143B

103B

6G

ND

NC

3A0

3A5

GN

D3A

12N

CG

ND

NC

AF

2625

2423

2221

2019

1817

1615

1413

1211

109

87

65

43

21

20446G-031


Pin Designations

7 D 15

Macrocell (0-15)

PAL Block (A-D)

Segment (0-7)

40 MACH 5 Family



5V M5 ORDERING INFORMATION1,2

Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combina-tion of the elements below.

.

Device Marking

Actual device marking differs from the ordering part number (OPN).All MACH devices are dual-marked with both Commercial andIndustrial grades. The Industrial grade is slower, i.e., M5-512/256-7AC-10AI.

1. M5-128/104-xxYC/1 and M5-128/104-xxYI/1 have beendiscontinued per PCN #06-07. Contact Rochester Electronics foravailable inventory.

.

Valid Combinations

Valid Combinations list configurations planned to be supported involume for this device. Consult the local Lattice sales office toconfirm availability of specific valid combinations and to check onnewly released combinations.

FAMILY TYPEM5- = MACH 5 (5-V VCC)

M5- 512 /256 -7 SA C

MACROCELL DENSITY128 = 128 Macrocells192 = 192 Macrocells256 = 256 Macrocells320 = 320 Macrocells384 = 384 Macrocells512 = 512 Macrocells

I/Os/68 = 68 I/Os in 100-pin PQFP or TQFP

/104 = 104 I/Os in 144-pin PQFP or TQFP/120 = 120 I/Os in 160-pin PQFP/160 = 160 I/Os in 208-pin PQFP/192 = 192 I/Os in 256-ball BGA/256 = 256 I/Os in 352-ball BGA

OPERATING CONDITIONSC = Commercial (0°C to +70°C)I = Industrial (-40°C to +85°C)

PACKAGE TYPEY = Plastic Quad Flat Pack (PQFP)V = Thin Quad Flat Pack (TQFP)SA = Ball Grid Array (BGA)

SPEED-5 = 5.5 ns tPD-6 = 6.5 ns tPD-7 = 7.5 ns tPD-10 = 10 ns tPD-12 = 12 ns tPD-15 = 15 ns tPD-20 = 20 ns tPD

Note:1. See below for valid device/package combinations.

2. M5-128/1, M5-192/1 and M5-256/1 recommended for new designs.

PROGRAMMING DESIGNATORBlank = Initial Algorithm/1 = First Revision

Valid Combinations

M5-128/68

Commercial:

-5, -7, -10, -12, -15

Industrial:

-7, -10, -12, -15, -20

YC, VC, YI, VI

M5-128/104 YC1, YI1

M5-128/120 YC, YI

M5-192/68 VC, VI

M5-192/120 YC, YI

M5-256/68 VC, VI

M5-256/120 YC, YI

M5-256/160 YC, YI

Valid Combinations

M5-320/160 Commercial:

-6, -7, -10, -12, -15

Industrial:

-7, -10, -12, -15, -20

YC, YI

M5-320/192 SAC, SAI

M5-384/160 YC, YI

M5-512/160 YC, YI

M5-512/256 SAC, SAI

MACH 5 Family 41



3.3V M5LV ORDERING INFORMATION1

Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combina-tion of the elements below.

Device Marking

Actual device marking differs from the ordering part number (OPN).All MACH devices are dual-marked with both Commercial andIndustrial grades. The Industrial grade is slower, i.e., M5LV-512/256-7AC-10AI.

Valid Combinations

Valid Combinations list configurations planned to be supported involume for this device. Consult the local Lattice sales office toconfirm availability of specific valid combinations and to check onnewly released combinations.

FAMILY TYPEM5LV- = MACH 5 Low Voltage (3.3-V VCC)

M5LV- 512 /256 -7 SA C

MACROCELL DENSITY128 = 128 Macrocells256 = 256 Macrocells320 = 320 Macrocells384 = 384 Macrocells512 = 512 Macrocells

I/Os/68 = 68 I/Os in 100-pin PQFP or TQFP

/74 = 74 I/Os in 100-pin TQFP/104 = 104 I/Os in 144-pin PQFP or TQFP/120 = 120 I/Os in 160-pin PQFP/160 = 160 I/Os in 208-pin PQFP/256 = 256 I/Os in 352-ball BGA

OPERATING CONDITIONSC = Commercial (0°C to +70°C)I = Industrial (-40°C to +85°C)

PACKAGE TYPEY = Plastic Quad Flat Pack (PQFP)V = Thin Quad Flat Pack (TQFP)SA = Ball Grid Array (BGA)

SPEED-5 = 5.5 ns tPD-6 = 6.5 ns tPD-7 = 7.5 ns tPD-10 = 10 ns tPD-12 = 12 ns tPD-15 = 15 ns tPD-20 = 20 ns tPD

Note:1. See below for valid device/package combinations.

Valid Combinations

M5LV-128/68

Commercial:

-5, -7, -10, -12

Industrial:

-7, -10, -12, -15

VC, VI

M5LV-128/74 VC, VI

M5LV-128/104 VC, VI

M5LV-128/120 YC, YI

M5LV-256/68 YC, YI

M5LV-256/74 VC, VI

M5LV-256/104 VC, VI

M5LV-256/120 YC, YI

M5LV-256/160 YC, YI

Valid Combinations

M5LV-320/120Commercial:

-6, -7, -10, -12, -15

Industrial:

-10, -12, -15, -20

YC, YI

M5LV-320/160 YC, YI

M5LV-384/120 YC, YI

M5LV-384/160 YC, YI

M5LV-512/120 YC, YI

M5LV-512/160 YC, YI

M5LV-512/256 SAC, SAI

42 MACH 5 Family

mach 5 cpld family

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