MALVINO

ElectronicPRINCIPLES

SIXTH EDITION

Chapter 14

MOSFETs

Depletion-mode MOSFET

n

Source

Gate

Drain

VDD

VGG

p

n

Source

Gate

Drain

VDD

VGG

p

Since the gate is insulated, this device can also be operated in the enhancement mode.

Metaloxide

insulator

(depletion mode) (enhancement mode)

MOSFETs

• Current flows through a narrow channel between the gate and substrate.

• SiO2 insulates the gate from the channel.

• Depletion mode forces the carriers from the channel.

• Enhancement mode attracts carriers into the channel.

• E-MOSFETs are normally-off devices.

n

Source

Gate

Drain

VDD

p

n

n-channel E-MOSFET

G

S

D

VGG

Gate bias enhances the channel and turns the device on.

n-channel E-MOSFET• The p-substrate extends all the way to the

silicon dioxide.

• No n-channel exists between the source and drain.

• This transistor is normally off when the gate voltage is zero.

• A positive gate voltage attracts electrons into the p-region to create an n-type inversion layer and turns the device on.

Source

Gate

Drain

VDD

p

n

p-channel E-MOSFET

G

S

D

VGG

Gate bias enhances the channel and turns the device on.

p

• The n-substrate extends all the way to the silicon dioxide.

• No p-channel exists between the source and drain.

• This transistor is normally off when the gate voltage is zero.

• A negative gate voltage attracts holes into the n-region to create an p-type inversion layer and turns the device on.

p-channel E-MOSFET

VDS

ID

+15 V

+10 V

+5 V

VGS(th)

n-channel E-MOSFET drain curves

Ohmic regionConstant current region

n-channel E-MOSFET transconductance curve

VGS(th) VGS(on)

ID(sat)

VGS

ID

Active

Ohmic

Gate breakdown

• The SiO2 insulating layer is very thin.

• It is easily destroyed by excessive gate-source voltage.

• VGS(max) ratings are typically in tens of volts.

• Circuit transients and static discharges can cause damage.

• Some devices have built-in gate protection.

ID(on)

VGS = VGS(on)

Drain-source on resistance

VDS(on)

Qtest

RDS(on) =VDS(on)

ID(on)

ID(on)

VGS = VGS(on)

Biasing in the ohmic region

VDD

Qtest

ID(sat) RD

+VDD

VGS

Q

ID(sat) < ID(on) when VGS = VGS(on) ensures saturation

Passive and active loads

RD

+VDD

vin

vout

+VDD

vin

vout

Q2

Q1

Passive load Active load(for Q1, VGS = VDS)

VDS

ID

+15 V

+10 V

+5 V

VGS = VDS produces a two-terminal curve

5 V 10 V 15 V

VGS

+VDD

vin

vout

Q2

Q1

It’s desirable that RDSQ2(on) << RDQ1.

Active loading in a digital inverter

0 V

+VDD

VDS(active)

ID(active)

RDQ1 =

0 V

+VDD

(The ideal output swings from 0 volts to +VDD.)

+VDD

vin vout

Q1 (p-channel)

Complementary MOS (CMOS) inverter

Q2 (n-channel)

PD(static) 0

0 V

+VDD

0 V

+VDD

CMOS inverter input-output graph

VDD

vin

vout

VDDVDD

2

VDD

2Crossover point PD(dynamic) 0

High-power EMOS

• Use different channel geometries to extend ratings

• Brand names such as VMOS, TMOS and hexFET

• No thermal runaway

• Can operate in parallel without current hogging

• Faster switching due to no minority carriers

dc-to-ac converter

vac

0 V

+VGS(on)

PowerFET

dc-to-dc converter

vdc

0 V

+VGS(on)

PowerFET