mani srivastava ucla - ee department room: 6731-h boelter hall email: [email protected] tel:...
TRANSCRIPT
![Page 1: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/1.jpg)
Mani SrivastavaUCLA - EE DepartmentRoom: 6731-H Boelter HallEmail: [email protected]: 310-267-2098WWW: http://www.ee.ucla.edu/~mbs
Copyright 2003 Mani Srivastava
High-level Synthesisof Embedded Hardware
EE202A (Fall 2003): Lecture #9
Note: Several slides in this Lecture are from
Prof. Miodrag Potkonjak, UCLA CS
![Page 2: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/2.jpg)
Copyright 2003 Mani Srivastava2
Overview
High Level Synthesis
Allocation, Assignment and Scheduling
Estimations
Transformations
![Page 3: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/3.jpg)
Copyright 2003 Mani Srivastava3
Synthesis ProcessALGORITHM
HIGH-LEVEL SYNTHESIS
S1 S3 S4S2
0.0 200.0 4 00.0 600. 0Freq
-120 .0
-100 .0
-80 .0
-60 .0
-40 .0
-20 .0
Am
pl
(db
)
++
++
D
D
++
++
D
D
c1 c2
c3
c4 c5
c6
kIN
+
+
D
D
++
+
D
D
+
++c1
c2 c3
c4
c5
c6 c7
c8
k
d
IN OUT
APPLICATION
interconnect
ASICGP signal
MCM
processor
memory
ARCHITECTURE
LOGIC AND PHYSICAL SYNTHESIS
![Page 4: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/4.jpg)
Copyright 2003 Mani Srivastava6
Typical High-Level Synthesis System
![Page 5: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/5.jpg)
Copyright 2003 Mani Srivastava7
High Level Synthesis Resource Allocation - How Much? Scheduling - When? Assignment - Where? Module Selection Template Matching & Operation Chaining Clock Selection Partitioning Transformations
![Page 6: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/6.jpg)
Copyright 2003 Mani Srivastava8
Allocation, Assignment, and Scheduling
D
+
-
>>
>>
+
-
>>
+ >>
+
>>
+
Allocation: How Much?2 adders
Assignment: Where?
Schedule: When?
Shifter 1
Time Slot 4
1 shifter24 registers
D
Techniques Well Understood and Mature
![Page 7: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/7.jpg)
Copyright 2003 Mani Srivastava9
Scheduling and Assignment
+
*3*2
3
+
*1
2
+1 1
2
3
3
4 4
+
*3*2
3
+2
+1 2
3
4
1
2 3
4 control steps
+ * * + *
*1
Schedule 1 Schedule 2
1 +1
2 +2
3 +3 *1
4 *2 *3
Control Step
1 +3
2 +1 *2
3 +2 *3
4 *1
Control Step
![Page 8: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/8.jpg)
Copyright 2003 Mani Srivastava10
High Level Synthesis
DD
***
+ +
Signal Flow Database
MAPPING
GRAPHICS
ESTIMATIONS
TRANSFORMATIONSSCHEDULING
func fir (In) : Out =begin
endOut = In@1 * a;
DD
***
+ +
Adder
Mult
Time 1 2 3 4xx x
x xx
Min Bounds:2 adders1 multiplier16 registers
D
***
++reg
regmult
C
TEMPLATE MATCHING
DD
***
+ +
+
![Page 9: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/9.jpg)
Copyright 2003 Mani Srivastava11
Algorithm Description
![Page 10: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/10.jpg)
Copyright 2003 Mani Srivastava12
Control Data Flow Graph (CDFG)
![Page 11: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/11.jpg)
Copyright 2003 Mani Srivastava13
Precedence Graph
![Page 12: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/12.jpg)
Copyright 2003 Mani Srivastava14
Sequence Graph: Start and End Nodes
![Page 13: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/13.jpg)
Copyright 2003 Mani Srivastava15
Hierarchy in Sequence Graphs
![Page 14: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/14.jpg)
Copyright 2003 Mani Srivastava16
Hierarchy in Sequence Graphs (contd.)
![Page 15: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/15.jpg)
Copyright 2003 Mani Srivastava17
Hierarchy in Sequence Graphs (contd.)
![Page 16: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/16.jpg)
Copyright 2003 Mani Srivastava18
Implementation
Control/DataFlow Graph
(CDFG)Implementation
RegReg
Multiplier
Adder
RegReg2 1 1 ...2 3 2 ...
4 3 2 ...
0 4 7 ...
4 7 9 ...
![Page 17: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/17.jpg)
Copyright 2003 Mani Srivastava19
Timing Constraints
Time measured in “cycles” or “control steps” problem?
Max & min timing constraints
![Page 18: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/18.jpg)
Copyright 2003 Mani Srivastava20
Constraint Graphs
![Page 19: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/19.jpg)
Copyright 2003 Mani Srivastava21
Operations with Unknown Delays
Unknown but bounded e.g.
Conditionals loops
Unknown and unbounded e.g.
I/O operations synchronization
Completion signal Called “anchor nodes”
Need to schedule relative to these anchors
![Page 20: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/20.jpg)
Copyright 2003 Mani Srivastava22
Scheduling Under Timing Constraints
Feasible constraint graph Timing constraints satisfied when execution delays of all
the anchors is zero Necessary for existence of schedule
Well-posed constraint graph Timing constraints satisfied for all values of execution
delays Implies feasibility
Feasible constraint graph is well-posed or can be made well-posed iff no cycles with unbounded weight exist
![Page 21: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/21.jpg)
Copyright 2003 Mani Srivastava23
Ill-posed (a, b) vs. Well-posed (c) Timing Constraints
![Page 22: Mani Srivastava UCLA - EE Department Room: 6731-H Boelter Hall Email: mbs@ee.ucla.edu Tel: 310-267-2098 WWW: mbs Copyright 2003](https://reader036.vdocument.in/reader036/viewer/2022070308/551c42e1550346a5458b460c/html5/thumbnails/22.jpg)
Copyright 2003 Mani Srivastava24
Conclusions
High Level Synthesis Connects Behavioral Description and Structural
Description Scheduling, Estimations, Transformations High Level of Abstraction, High Impact on the
Final Design